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/Linux-v5.10/Documentation/devicetree/bindings/sound/
Damlogic,t9015.yaml17 const: 0
54 reg = <0x32000 0x14>;
55 #sound-dai-cells = <0>;
/Linux-v5.10/arch/arm/include/debug/
Dsti.S9 #define STIH41X_COMMS_BASE 0xfed00000
10 #define STIH41X_ASC2_BASE (STIH41X_COMMS_BASE+0x32000)
12 #define STIH41X_SBC_LPM_BASE 0xfe400000
13 #define STIH41X_SBC_COMMS_BASE (STIH41X_SBC_LPM_BASE + 0x100000)
14 #define STIH41X_SBC_ASC1_BASE (STIH41X_SBC_COMMS_BASE + 0x31000)
17 #define VIRT_ADDRESS(x) (x - 0x1000000)
31 #define ASC_TX_BUF_OFF 0x04
32 #define ASC_CTRL_OFF 0x0c
33 #define ASC_STA_OFF 0x14
/Linux-v5.10/arch/arm/mach-omap1/
Dsram-init.c23 #define OMAP1_SRAM_PA 0x20000000
24 #define SRAM_BOOTLOADER_SZ 0x80
39 omap_sram_size = 0x32000; /* 200K */ in omap_detect_and_map_sram()
41 omap_sram_size = 0x30000; /* 192K */ in omap_detect_and_map_sram()
44 omap_sram_size = 0x4000; /* 16K */ in omap_detect_and_map_sram()
47 omap_sram_size = 0x4000; in omap_detect_and_map_sram()
61 ckctl |= 0x2000; in omap_sram_reprogram_clock()
72 return 0; in omap_sram_init()
/Linux-v5.10/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
155 const: 0
169 const: 0
203 const: 0
294 "^(pru|rtu|txpru)@[0-9a-f]+$":
335 pruss: pruss@0 {
337 reg = <0x0 0x80000>;
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Drda8810pl.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
30 reg = <0x100000 0x10000>;
40 ranges = <0x0 0x10000000 0xfffffff>;
44 reg = <0x1a08000 0x1000>;
55 ranges = <0x0 0x20800000 0x100000>;
57 intc: interrupt-controller@0 {
59 reg = <0x0 0x1000>;
69 ranges = <0x0 0x20900000 0x100000>;
[all …]
Domap5-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
Domap4-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
Ddm814x.dtsi35 #size-cells = <0>;
36 cpu@0 {
39 reg = <0>;
69 reg = <0x47400000 0x1000>;
77 reg = <0x47401300 0x100>;
80 #phy-cells = <0>;
85 reg = <0x47401400 0x400
86 0x47401000 0x200>;
98 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
99 &cppi41dma 2 0 &cppi41dma 3 0
[all …]
Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
10 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
11 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
12 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
13 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
14 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
[all …]
Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
4 reg = <0x4a000000 0x800>,
5 <0x4a000800 0x800>,
6 <0x4a001000 0x1000>;
10 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
11 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
12 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
13 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
14 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
15 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
[all …]
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
13 segment@0 { /* 0x4a000000 */
17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
18 <0x00000800 0x00000800 0x000800>, /* ap 1 */
[all …]
Dam33xx-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
3 reg = <0x44c00000 0x800>,
4 <0x44c00800 0x800>,
5 <0x44c01000 0x400>,
6 <0x44c01400 0x400>;
10 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
11 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
12 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
14 segment@0 { /* 0x44c00000 */
18 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/Linux-v5.10/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
Dhal_bt_coexist.c86 u8 bt_rssi_state = 0; in rtl8723e_dm_bt_check_coex_rssi_state1()
213 long undecoratedsmoothed_pwdb = 0; in rtl8723e_dm_bt_check_coex_rssi_state()
214 u8 bt_rssi_state = 0; in rtl8723e_dm_bt_check_coex_rssi_state()
336 long undecoratedsmoothed_pwdb = 0; in rtl8723e_dm_bt_get_rx_ss()
356 u8 h2c_parameter[3] = {0}; in rtl8723e_dm_bt_balance()
361 h2c_parameter[0] = ms0; in rtl8723e_dm_bt_balance()
364 h2c_parameter[2] = 0; in rtl8723e_dm_bt_balance()
365 h2c_parameter[1] = 0; in rtl8723e_dm_bt_balance()
366 h2c_parameter[0] = 0; in rtl8723e_dm_bt_balance()
371 "[DM][BT], Balance=[%s:%dms:%dms], write 0xc=0x%x\n", in rtl8723e_dm_bt_balance()
[all …]
/Linux-v5.10/arch/powerpc/boot/dts/fsl/
Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/Linux-v5.10/arch/arm64/boot/dts/amlogic/
Dmeson-g12-common.dtsi100 reg = <0x0 0x05000000 0x0 0x300000>;
107 size = <0x0 0x10000000>;
108 alignment = <0x0 0x400000>;
125 reg = <0x0 0xfc000000 0x0 0x400000
126 0x0 0xff648000 0x0 0x2000
127 0x0 0xfc400000 0x0 0x200000>;
131 interrupt-map-mask = <0 0 0 0>;
132 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
133 bus-range = <0x0 0xff>;
137 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
[all …]
/Linux-v5.10/arch/arm64/boot/dts/qcom/
Dmsm8996.dtsi22 #clock-cells = <0>;
29 #clock-cells = <0>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
42 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
66 reg = <0x0 0x100>;
80 reg = <0x0 0x101>;
112 CPU_SLEEP_0: cpu-sleep-0 {
115 arm,psci-suspend-param = <0x00000004>;
[all …]
/Linux-v5.10/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/Linux-v5.10/sound/pci/rme9652/
Dhdsp.c34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
75 #define HDSP_resetPointer 0
76 #define HDSP_freqReg 0
91 #define HDSP_statusRegister 0
132 #define HDSP_TMS 0x01
133 #define HDSP_TCK 0x02
134 #define HDSP_TDI 0x04
135 #define HDSP_JTAG 0x08
136 #define HDSP_PWDN 0x10
137 #define HDSP_PROGRAM 0x020
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x10A9
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x10B0
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 …SDMA0_DEC_START 0x0000
32 …ne mmSDMA0_DEC_START_BASE_IDX 0
33 …SDMA0_PG_CNTL 0x0016
34 …ne mmSDMA0_PG_CNTL_BASE_IDX 0
35 …SDMA0_PG_CTX_LO 0x0017
[all …]
Dgc_10_3_0_offset.h25 …SQ_DEBUG_STS_GLOBAL 0x10A9
26 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
27 …SQ_DEBUG_STS_GLOBAL2 0x10B0
28 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
31 // base address: 0x4980
32 …SDMA0_DEC_START 0x0000
33 …ne mmSDMA0_DEC_START_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …ne mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
[all …]