Lines Matching +full:0 +full:x32000
1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
13 segment@0 { /* 0x4a000000 */
17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
18 <0x00000800 0x00000800 0x000800>, /* ap 1 */
19 <0x00001000 0x00001000 0x001000>, /* ap 2 */
20 <0x00002000 0x00002000 0x002000>, /* ap 3 */
21 <0x00004000 0x00004000 0x001000>, /* ap 4 */
22 <0x00005000 0x00005000 0x001000>, /* ap 5 */
23 <0x00006000 0x00006000 0x001000>, /* ap 6 */
24 <0x00008000 0x00008000 0x002000>, /* ap 7 */
25 <0x0000a000 0x0000a000 0x001000>, /* ap 8 */
26 <0x00056000 0x00056000 0x001000>, /* ap 9 */
27 <0x00057000 0x00057000 0x001000>, /* ap 10 */
28 <0x0005e000 0x0005e000 0x002000>, /* ap 11 */
29 <0x00060000 0x00060000 0x001000>, /* ap 12 */
30 <0x00080000 0x00080000 0x008000>, /* ap 13 */
31 <0x00088000 0x00088000 0x001000>, /* ap 14 */
32 <0x000a0000 0x000a0000 0x008000>, /* ap 15 */
33 <0x000a8000 0x000a8000 0x001000>, /* ap 16 */
34 <0x000d9000 0x000d9000 0x001000>, /* ap 17 */
35 <0x000da000 0x000da000 0x001000>, /* ap 18 */
36 <0x000dd000 0x000dd000 0x001000>, /* ap 19 */
37 <0x000de000 0x000de000 0x001000>, /* ap 20 */
38 <0x000e0000 0x000e0000 0x001000>, /* ap 21 */
39 <0x000e1000 0x000e1000 0x001000>, /* ap 22 */
40 <0x000f4000 0x000f4000 0x001000>, /* ap 23 */
41 <0x000f5000 0x000f5000 0x001000>, /* ap 24 */
42 <0x000f6000 0x000f6000 0x001000>, /* ap 25 */
43 <0x000f7000 0x000f7000 0x001000>, /* ap 26 */
44 <0x00090000 0x00090000 0x008000>, /* ap 59 */
45 <0x00098000 0x00098000 0x001000>; /* ap 60 */
47 target-module@2000 { /* 0x4a002000, ap 3 08.0 */
49 reg = <0x2000 0x4>;
53 ranges = <0x0 0x2000 0x2000>;
55 scm: scm@0 {
57 reg = <0 0x2000>;
60 ranges = <0 0 0x2000>;
62 scm_conf: scm_conf@0 {
64 reg = <0x0 0x1400>;
67 ranges = <0 0x0 0x1400>;
71 reg = <0xe00 0x4>;
82 reg = <0x554 0x4>;
88 #size-cells = <0>;
95 reg = <0x1400 0x0468>;
97 #size-cells = <0>;
102 pinctrl-single,function-mask = <0x3fffffff>;
107 reg = <0x1c04 0x0020>;
113 reg = <0x1c24 0x0024>;
118 reg = <0xb78 0xfc>;
121 ti,dma-safe-map = <0>;
127 reg = <0xc78 0x7c>;
130 ti,dma-safe-map = <0>;
136 target-module@5000 { /* 0x4a005000, ap 5 10.0 */
138 reg = <0x5000 0x4>;
142 ranges = <0x0 0x5000 0x1000>;
144 cm_core_aon: cm_core_aon@0 {
149 reg = <0 0x2000>;
150 ranges = <0 0 0x2000>;
154 #size-cells = <0>;
162 target-module@8000 { /* 0x4a008000, ap 7 0e.0 */
164 reg = <0x8000 0x4>;
168 ranges = <0x0 0x8000 0x2000>;
170 cm_core: cm_core@0 {
174 reg = <0 0x3000>;
175 ranges = <0 0 0x3000>;
179 #size-cells = <0>;
187 target-module@56000 { /* 0x4a056000, ap 9 02.0 */
189 reg = <0x56000 0x4>,
190 <0x5602c 0x4>,
191 <0x56028 0x4>;
207 clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
211 ranges = <0x0 0x56000 0x1000>;
213 sdma: dma-controller@0 {
215 reg = <0x0 0x1000>;
226 target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
231 ranges = <0x0 0x5e000 0x2000>;
234 target-module@80000 { /* 0x4a080000, ap 13 20.0 */
236 reg = <0x80000 0x4>,
237 <0x80010 0x4>,
238 <0x80014 0x4>;
247 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
251 ranges = <0x0 0x80000 0x8000>;
253 ocp2scp@0 {
257 ranges = <0 0 0x8000>;
258 reg = <0x0 0x20>;
262 reg = <0x4000 0x400>;
263 syscon-phy-power = <&scm_conf 0x300>;
268 #phy-cells = <0>;
274 reg = <0x5000 0x400>;
275 syscon-phy-power = <&scm_conf 0xe74>;
280 #phy-cells = <0>;
285 reg = <0x4400 0x80>,
286 <0x4800 0x64>,
287 <0x4c00 0x40>;
289 syscon-phy-power = <&scm_conf 0x370>;
296 #phy-cells = <0>;
301 target-module@90000 { /* 0x4a090000, ap 59 42.0 */
303 reg = <0x90000 0x4>,
304 <0x90010 0x4>,
305 <0x90014 0x4>;
314 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
318 ranges = <0x0 0x90000 0x8000>;
320 ocp2scp@0 {
324 ranges = <0 0 0x8000>;
325 reg = <0x0 0x20>;
329 reg = <0x4000 0x80>, /* phy_rx */
330 <0x4400 0x64>; /* phy_tx */
332 syscon-phy-power = <&scm_conf_pcie 0x1c>;
333 syscon-pcs = <&scm_conf_pcie 0x10>;
344 #phy-cells = <0>;
349 reg = <0x5000 0x80>, /* phy_rx */
350 <0x5400 0x64>; /* phy_tx */
352 syscon-phy-power = <&scm_conf_pcie 0x20>;
353 syscon-pcs = <&scm_conf_pcie 0x10>;
364 #phy-cells = <0>;
370 reg = <0x6000 0x80>, /* phy_rx */
371 <0x6400 0x64>, /* phy_tx */
372 <0x6800 0x40>; /* pll_ctrl */
374 syscon-phy-power = <&scm_conf 0x374>;
378 syscon-pllreset = <&scm_conf 0x3fc>;
379 #phy-cells = <0>;
384 target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
389 ranges = <0x0 0xa0000 0x8000>;
392 target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
394 reg = <0xd9038 0x4>;
402 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
406 ranges = <0x0 0xd9000 0x1000>;
411 target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
413 reg = <0xdd038 0x4>;
421 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
425 ranges = <0x0 0xdd000 0x1000>;
430 target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
435 ranges = <0x0 0xe0000 0x1000>;
438 target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
440 reg = <0xf4000 0x4>,
441 <0xf4010 0x4>;
448 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
452 ranges = <0x0 0xf4000 0x1000>;
454 mailbox1: mailbox@0 {
456 reg = <0x0 0x200>;
467 target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
469 reg = <0xf6000 0x4>,
470 <0xf6010 0x4>,
471 <0xf6014 0x4>;
481 clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
485 ranges = <0x0 0xf6000 0x1000>;
487 hwspinlock: spinlock@0 {
489 reg = <0x0 0x1000>;
495 segment@100000 { /* 0x4a100000 */
499 ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
500 <0x00003000 0x00103000 0x001000>, /* ap 28 */
501 <0x00008000 0x00108000 0x001000>, /* ap 29 */
502 <0x00009000 0x00109000 0x001000>, /* ap 30 */
503 <0x00040000 0x00140000 0x010000>, /* ap 31 */
504 <0x00050000 0x00150000 0x001000>, /* ap 32 */
505 <0x00051000 0x00151000 0x001000>, /* ap 33 */
506 <0x00052000 0x00152000 0x001000>, /* ap 34 */
507 <0x00053000 0x00153000 0x001000>, /* ap 35 */
508 <0x00054000 0x00154000 0x001000>, /* ap 36 */
509 <0x00055000 0x00155000 0x001000>, /* ap 37 */
510 <0x00056000 0x00156000 0x001000>, /* ap 38 */
511 <0x00057000 0x00157000 0x001000>, /* ap 39 */
512 <0x00058000 0x00158000 0x001000>, /* ap 40 */
513 <0x0005b000 0x0015b000 0x001000>, /* ap 41 */
514 <0x0005c000 0x0015c000 0x001000>, /* ap 42 */
515 <0x0005d000 0x0015d000 0x001000>, /* ap 45 */
516 <0x0005e000 0x0015e000 0x001000>, /* ap 46 */
517 <0x0005f000 0x0015f000 0x001000>, /* ap 47 */
518 <0x00060000 0x00160000 0x001000>, /* ap 48 */
519 <0x00061000 0x00161000 0x001000>, /* ap 49 */
520 <0x00062000 0x00162000 0x001000>, /* ap 50 */
521 <0x00063000 0x00163000 0x001000>, /* ap 51 */
522 <0x00064000 0x00164000 0x001000>, /* ap 52 */
523 <0x00065000 0x00165000 0x001000>, /* ap 53 */
524 <0x00066000 0x00166000 0x001000>, /* ap 54 */
525 <0x00067000 0x00167000 0x001000>, /* ap 55 */
526 <0x00068000 0x00168000 0x001000>, /* ap 56 */
527 <0x0006d000 0x0016d000 0x001000>, /* ap 57 */
528 <0x0006e000 0x0016e000 0x001000>, /* ap 58 */
529 <0x00071000 0x00171000 0x001000>, /* ap 61 */
530 <0x00072000 0x00172000 0x001000>, /* ap 62 */
531 <0x00073000 0x00173000 0x001000>, /* ap 63 */
532 <0x00074000 0x00174000 0x001000>, /* ap 64 */
533 <0x00075000 0x00175000 0x001000>, /* ap 65 */
534 <0x00076000 0x00176000 0x001000>, /* ap 66 */
535 <0x00077000 0x00177000 0x001000>, /* ap 67 */
536 <0x00078000 0x00178000 0x001000>, /* ap 68 */
537 <0x00081000 0x00181000 0x001000>, /* ap 69 */
538 <0x00082000 0x00182000 0x001000>, /* ap 70 */
539 <0x00083000 0x00183000 0x001000>, /* ap 71 */
540 <0x00084000 0x00184000 0x001000>, /* ap 72 */
541 <0x00085000 0x00185000 0x001000>, /* ap 73 */
542 <0x00086000 0x00186000 0x001000>, /* ap 74 */
543 <0x00087000 0x00187000 0x001000>, /* ap 75 */
544 <0x00088000 0x00188000 0x001000>, /* ap 76 */
545 <0x00069000 0x00169000 0x001000>, /* ap 103 */
546 <0x0006a000 0x0016a000 0x001000>, /* ap 104 */
547 <0x00079000 0x00179000 0x001000>, /* ap 105 */
548 <0x0007a000 0x0017a000 0x001000>, /* ap 106 */
549 <0x0006b000 0x0016b000 0x001000>, /* ap 107 */
550 <0x0006c000 0x0016c000 0x001000>, /* ap 108 */
551 <0x0007b000 0x0017b000 0x001000>, /* ap 121 */
552 <0x0007c000 0x0017c000 0x001000>, /* ap 122 */
553 <0x0007d000 0x0017d000 0x001000>, /* ap 123 */
554 <0x0007e000 0x0017e000 0x001000>, /* ap 124 */
555 <0x00059000 0x00159000 0x001000>, /* ap 125 */
556 <0x0005a000 0x0015a000 0x001000>; /* ap 126 */
558 target-module@2000 { /* 0x4a102000, ap 27 3c.0 */
563 ranges = <0x0 0x2000 0x1000>;
566 target-module@8000 { /* 0x4a108000, ap 29 1e.0 */
571 ranges = <0x0 0x8000 0x1000>;
574 target-module@40000 { /* 0x4a140000, ap 31 06.0 */
579 ranges = <0x0 0x40000 0x10000>;
582 target-module@51000 { /* 0x4a151000, ap 33 50.0 */
587 ranges = <0x0 0x51000 0x1000>;
590 target-module@53000 { /* 0x4a153000, ap 35 54.0 */
595 ranges = <0x0 0x53000 0x1000>;
598 target-module@55000 { /* 0x4a155000, ap 37 46.0 */
603 ranges = <0x0 0x55000 0x1000>;
606 target-module@57000 { /* 0x4a157000, ap 39 58.0 */
611 ranges = <0x0 0x57000 0x1000>;
614 target-module@59000 { /* 0x4a159000, ap 125 6a.0 */
619 ranges = <0x0 0x59000 0x1000>;
622 target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */
627 ranges = <0x0 0x5b000 0x1000>;
630 target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */
635 ranges = <0x0 0x5d000 0x1000>;
638 target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */
643 ranges = <0x0 0x5f000 0x1000>;
646 target-module@61000 { /* 0x4a161000, ap 49 32.0 */
651 ranges = <0x0 0x61000 0x1000>;
654 target-module@63000 { /* 0x4a163000, ap 51 5c.0 */
659 ranges = <0x0 0x63000 0x1000>;
662 target-module@65000 { /* 0x4a165000, ap 53 4e.0 */
667 ranges = <0x0 0x65000 0x1000>;
670 target-module@67000 { /* 0x4a167000, ap 55 5e.0 */
675 ranges = <0x0 0x67000 0x1000>;
678 target-module@69000 { /* 0x4a169000, ap 103 4a.0 */
683 ranges = <0x0 0x69000 0x1000>;
686 target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */
691 ranges = <0x0 0x6b000 0x1000>;
694 target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */
699 ranges = <0x0 0x6d000 0x1000>;
702 target-module@71000 { /* 0x4a171000, ap 61 48.0 */
707 ranges = <0x0 0x71000 0x1000>;
710 target-module@73000 { /* 0x4a173000, ap 63 2a.0 */
715 ranges = <0x0 0x73000 0x1000>;
718 target-module@75000 { /* 0x4a175000, ap 65 64.0 */
723 ranges = <0x0 0x75000 0x1000>;
726 target-module@77000 { /* 0x4a177000, ap 67 66.0 */
731 ranges = <0x0 0x77000 0x1000>;
734 target-module@79000 { /* 0x4a179000, ap 105 34.0 */
739 ranges = <0x0 0x79000 0x1000>;
742 target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */
747 ranges = <0x0 0x7b000 0x1000>;
750 target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */
755 ranges = <0x0 0x7d000 0x1000>;
758 target-module@81000 { /* 0x4a181000, ap 69 26.0 */
763 ranges = <0x0 0x81000 0x1000>;
766 target-module@83000 { /* 0x4a183000, ap 71 2e.0 */
771 ranges = <0x0 0x83000 0x1000>;
774 target-module@85000 { /* 0x4a185000, ap 73 36.0 */
779 ranges = <0x0 0x85000 0x1000>;
782 target-module@87000 { /* 0x4a187000, ap 75 74.0 */
787 ranges = <0x0 0x87000 0x1000>;
791 segment@200000 { /* 0x4a200000 */
795 ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
796 <0x00019000 0x00219000 0x001000>, /* ap 44 */
797 <0x00000000 0x00200000 0x001000>, /* ap 77 */
798 <0x00001000 0x00201000 0x001000>, /* ap 78 */
799 <0x0000a000 0x0020a000 0x001000>, /* ap 79 */
800 <0x0000b000 0x0020b000 0x001000>, /* ap 80 */
801 <0x0000c000 0x0020c000 0x001000>, /* ap 81 */
802 <0x0000d000 0x0020d000 0x001000>, /* ap 82 */
803 <0x0000e000 0x0020e000 0x001000>, /* ap 83 */
804 <0x0000f000 0x0020f000 0x001000>, /* ap 84 */
805 <0x00010000 0x00210000 0x001000>, /* ap 85 */
806 <0x00011000 0x00211000 0x001000>, /* ap 86 */
807 <0x00012000 0x00212000 0x001000>, /* ap 87 */
808 <0x00013000 0x00213000 0x001000>, /* ap 88 */
809 <0x00014000 0x00214000 0x001000>, /* ap 89 */
810 <0x00015000 0x00215000 0x001000>, /* ap 90 */
811 <0x0002a000 0x0022a000 0x001000>, /* ap 91 */
812 <0x0002b000 0x0022b000 0x001000>, /* ap 92 */
813 <0x0001c000 0x0021c000 0x001000>, /* ap 93 */
814 <0x0001d000 0x0021d000 0x001000>, /* ap 94 */
815 <0x0001e000 0x0021e000 0x001000>, /* ap 95 */
816 <0x0001f000 0x0021f000 0x001000>, /* ap 96 */
817 <0x00020000 0x00220000 0x001000>, /* ap 97 */
818 <0x00021000 0x00221000 0x001000>, /* ap 98 */
819 <0x00024000 0x00224000 0x001000>, /* ap 99 */
820 <0x00025000 0x00225000 0x001000>, /* ap 100 */
821 <0x00026000 0x00226000 0x001000>, /* ap 101 */
822 <0x00027000 0x00227000 0x001000>, /* ap 102 */
823 <0x0002c000 0x0022c000 0x001000>, /* ap 109 */
824 <0x0002d000 0x0022d000 0x001000>, /* ap 110 */
825 <0x0002e000 0x0022e000 0x001000>, /* ap 111 */
826 <0x0002f000 0x0022f000 0x001000>, /* ap 112 */
827 <0x00030000 0x00230000 0x001000>, /* ap 113 */
828 <0x00031000 0x00231000 0x001000>, /* ap 114 */
829 <0x00032000 0x00232000 0x001000>, /* ap 115 */
830 <0x00033000 0x00233000 0x001000>, /* ap 116 */
831 <0x00034000 0x00234000 0x001000>, /* ap 117 */
832 <0x00035000 0x00235000 0x001000>, /* ap 118 */
833 <0x00036000 0x00236000 0x001000>, /* ap 119 */
834 <0x00037000 0x00237000 0x001000>, /* ap 120 */
835 <0x0001a000 0x0021a000 0x001000>, /* ap 127 */
836 <0x0001b000 0x0021b000 0x001000>; /* ap 128 */
838 target-module@0 { /* 0x4a200000, ap 77 3e.0 */
843 ranges = <0x0 0x0 0x1000>;
846 target-module@a000 { /* 0x4a20a000, ap 79 30.0 */
851 ranges = <0x0 0xa000 0x1000>;
854 target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */
859 ranges = <0x0 0xc000 0x1000>;
862 target-module@e000 { /* 0x4a20e000, ap 83 22.0 */
867 ranges = <0x0 0xe000 0x1000>;
870 target-module@10000 { /* 0x4a210000, ap 85 14.0 */
875 ranges = <0x0 0x10000 0x1000>;
878 target-module@12000 { /* 0x4a212000, ap 87 16.0 */
883 ranges = <0x0 0x12000 0x1000>;
886 target-module@14000 { /* 0x4a214000, ap 89 1c.0 */
891 ranges = <0x0 0x14000 0x1000>;
894 target-module@18000 { /* 0x4a218000, ap 43 12.0 */
899 ranges = <0x0 0x18000 0x1000>;
902 target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */
907 ranges = <0x0 0x1a000 0x1000>;
910 target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */
915 ranges = <0x0 0x1c000 0x1000>;
918 target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */
923 ranges = <0x0 0x1e000 0x1000>;
926 target-module@20000 { /* 0x4a220000, ap 97 24.0 */
931 ranges = <0x0 0x20000 0x1000>;
934 target-module@24000 { /* 0x4a224000, ap 99 44.0 */
939 ranges = <0x0 0x24000 0x1000>;
942 target-module@26000 { /* 0x4a226000, ap 101 2c.0 */
947 ranges = <0x0 0x26000 0x1000>;
950 target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */
955 ranges = <0x0 0x2a000 0x1000>;
958 target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */
963 ranges = <0x0 0x2c000 0x1000>;
966 target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */
971 ranges = <0x0 0x2e000 0x1000>;
974 target-module@30000 { /* 0x4a230000, ap 113 70.0 */
979 ranges = <0x0 0x30000 0x1000>;
982 target-module@32000 { /* 0x4a232000, ap 115 5a.0 */
987 ranges = <0x0 0x32000 0x1000>;
990 target-module@34000 { /* 0x4a234000, ap 117 76.1 */
995 ranges = <0x0 0x34000 0x1000>;
998 target-module@36000 { /* 0x4a236000, ap 119 62.0 */
1003 ranges = <0x0 0x36000 0x1000>;
1008 &l4_per1 { /* 0x48000000 */
1010 reg = <0x48000000 0x800>,
1011 <0x48000800 0x800>,
1012 <0x48001000 0x400>,
1013 <0x48001400 0x400>,
1014 <0x48001800 0x400>,
1015 <0x48001c00 0x400>;
1019 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1020 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1022 segment@0 { /* 0x48000000 */
1026 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1027 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1028 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1029 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1030 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1031 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1032 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1033 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1034 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1035 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1036 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1037 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1038 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1039 <0x00055000 0x00055000 0x001000>, /* ap 13 */
1040 <0x00056000 0x00056000 0x001000>, /* ap 14 */
1041 <0x00057000 0x00057000 0x001000>, /* ap 15 */
1042 <0x00058000 0x00058000 0x001000>, /* ap 16 */
1043 <0x00059000 0x00059000 0x001000>, /* ap 17 */
1044 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
1045 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
1046 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
1047 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
1048 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
1049 <0x00060000 0x00060000 0x001000>, /* ap 23 */
1050 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
1051 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
1052 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
1053 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
1054 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
1055 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
1056 <0x00070000 0x00070000 0x001000>, /* ap 30 */
1057 <0x00071000 0x00071000 0x001000>, /* ap 31 */
1058 <0x00072000 0x00072000 0x001000>, /* ap 32 */
1059 <0x00073000 0x00073000 0x001000>, /* ap 33 */
1060 <0x00061000 0x00061000 0x001000>, /* ap 34 */
1061 <0x00053000 0x00053000 0x001000>, /* ap 35 */
1062 <0x00054000 0x00054000 0x001000>, /* ap 36 */
1063 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
1064 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
1065 <0x00078000 0x00078000 0x001000>, /* ap 39 */
1066 <0x00079000 0x00079000 0x001000>, /* ap 40 */
1067 <0x00086000 0x00086000 0x001000>, /* ap 41 */
1068 <0x00087000 0x00087000 0x001000>, /* ap 42 */
1069 <0x00088000 0x00088000 0x001000>, /* ap 43 */
1070 <0x00089000 0x00089000 0x001000>, /* ap 44 */
1071 <0x00051000 0x00051000 0x001000>, /* ap 45 */
1072 <0x00052000 0x00052000 0x001000>, /* ap 46 */
1073 <0x00098000 0x00098000 0x001000>, /* ap 47 */
1074 <0x00099000 0x00099000 0x001000>, /* ap 48 */
1075 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
1076 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
1077 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
1078 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
1079 <0x00068000 0x00068000 0x001000>, /* ap 53 */
1080 <0x00069000 0x00069000 0x001000>, /* ap 54 */
1081 <0x00090000 0x00090000 0x002000>, /* ap 55 */
1082 <0x00092000 0x00092000 0x001000>, /* ap 56 */
1083 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1084 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1085 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1086 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1087 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1088 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1089 <0x00066000 0x00066000 0x001000>, /* ap 63 */
1090 <0x00067000 0x00067000 0x001000>, /* ap 64 */
1091 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1092 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1093 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1094 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1095 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1096 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1097 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1098 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1099 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1100 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1101 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1102 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1103 <0x00001400 0x00001400 0x000400>, /* ap 77 */
1104 <0x00001800 0x00001800 0x000400>, /* ap 78 */
1105 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1106 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1107 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1108 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1109 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1110 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1112 target-module@20000 { /* 0x48020000, ap 3 04.0 */
1114 reg = <0x20050 0x4>,
1115 <0x20054 0x4>,
1116 <0x20058 0x4>;
1127 clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1131 ranges = <0x0 0x20000 0x1000>;
1133 uart3: serial@0 {
1135 reg = <0x0 0x100>;
1144 target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1146 reg = <0x32000 0x4>,
1147 <0x32010 0x4>;
1156 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1160 ranges = <0x0 0x32000 0x1000>;
1162 timer2: timer@0 {
1164 reg = <0x0 0x80>;
1171 target-module@34000 { /* 0x48034000, ap 7 46.0 */
1173 reg = <0x34000 0x4>,
1174 <0x34010 0x4>;
1183 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1187 ranges = <0x0 0x34000 0x1000>;
1189 timer3: timer@0 {
1191 reg = <0x0 0x80>;
1198 target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1200 reg = <0x36000 0x4>,
1201 <0x36010 0x4>;
1210 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1214 ranges = <0x0 0x36000 0x1000>;
1216 timer4: timer@0 {
1218 reg = <0x0 0x80>;
1225 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1227 reg = <0x3e000 0x4>,
1228 <0x3e010 0x4>;
1237 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1241 ranges = <0x0 0x3e000 0x1000>;
1243 timer9: timer@0 {
1245 reg = <0x0 0x80>;
1252 gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1254 reg = <0x51000 0x4>,
1255 <0x51010 0x4>,
1256 <0x51114 0x4>;
1267 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1272 ranges = <0x0 0x51000 0x1000>;
1274 gpio7: gpio@0 {
1276 reg = <0x0 0x200>;
1285 target-module@53000 { /* 0x48053000, ap 35 36.0 */
1287 reg = <0x53000 0x4>,
1288 <0x53010 0x4>,
1289 <0x53114 0x4>;
1300 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1305 ranges = <0x0 0x53000 0x1000>;
1307 gpio8: gpio@0 {
1309 reg = <0x0 0x200>;
1318 target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1320 reg = <0x55000 0x4>,
1321 <0x55010 0x4>,
1322 <0x55114 0x4>;
1333 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1338 ranges = <0x0 0x55000 0x1000>;
1340 gpio2: gpio@0 {
1342 reg = <0x0 0x200>;
1351 target-module@57000 { /* 0x48057000, ap 15 06.0 */
1353 reg = <0x57000 0x4>,
1354 <0x57010 0x4>,
1355 <0x57114 0x4>;
1366 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1371 ranges = <0x0 0x57000 0x1000>;
1373 gpio3: gpio@0 {
1375 reg = <0x0 0x200>;
1384 target-module@59000 { /* 0x48059000, ap 17 16.0 */
1386 reg = <0x59000 0x4>,
1387 <0x59010 0x4>,
1388 <0x59114 0x4>;
1399 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1404 ranges = <0x0 0x59000 0x1000>;
1406 gpio4: gpio@0 {
1408 reg = <0x0 0x200>;
1417 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1419 reg = <0x5b000 0x4>,
1420 <0x5b010 0x4>,
1421 <0x5b114 0x4>;
1432 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1437 ranges = <0x0 0x5b000 0x1000>;
1439 gpio5: gpio@0 {
1441 reg = <0x0 0x200>;
1450 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1452 reg = <0x5d000 0x4>,
1453 <0x5d010 0x4>,
1454 <0x5d114 0x4>;
1465 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1470 ranges = <0x0 0x5d000 0x1000>;
1472 gpio6: gpio@0 {
1474 reg = <0x0 0x200>;
1483 target-module@60000 { /* 0x48060000, ap 23 32.0 */
1485 reg = <0x60000 0x8>,
1486 <0x60010 0x8>,
1487 <0x60090 0x8>;
1499 clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1503 ranges = <0x0 0x60000 0x1000>;
1505 i2c3: i2c@0 {
1507 reg = <0x0 0x100>;
1510 #size-cells = <0>;
1515 target-module@66000 { /* 0x48066000, ap 63 14.0 */
1517 reg = <0x66050 0x4>,
1518 <0x66054 0x4>,
1519 <0x66058 0x4>;
1530 clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1534 ranges = <0x0 0x66000 0x1000>;
1536 uart5: serial@0 {
1538 reg = <0x0 0x100>;
1547 target-module@68000 { /* 0x48068000, ap 53 1c.0 */
1549 reg = <0x68050 0x4>,
1550 <0x68054 0x4>,
1551 <0x68058 0x4>;
1562 clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1566 ranges = <0x0 0x68000 0x1000>;
1568 uart6: serial@0 {
1570 reg = <0x0 0x100>;
1579 target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
1581 reg = <0x6a050 0x4>,
1582 <0x6a054 0x4>,
1583 <0x6a058 0x4>;
1594 clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1598 ranges = <0x0 0x6a000 0x1000>;
1600 uart1: serial@0 {
1602 reg = <0x0 0x100>;
1611 target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
1613 reg = <0x6c050 0x4>,
1614 <0x6c054 0x4>,
1615 <0x6c058 0x4>;
1626 clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1630 ranges = <0x0 0x6c000 0x1000>;
1632 uart2: serial@0 {
1634 reg = <0x0 0x100>;
1643 target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
1645 reg = <0x6e050 0x4>,
1646 <0x6e054 0x4>,
1647 <0x6e058 0x4>;
1658 clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1662 ranges = <0x0 0x6e000 0x1000>;
1664 uart4: serial@0 {
1666 reg = <0x0 0x100>;
1675 target-module@70000 { /* 0x48070000, ap 30 22.0 */
1677 reg = <0x70000 0x8>,
1678 <0x70010 0x8>,
1679 <0x70090 0x8>;
1691 clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1695 ranges = <0x0 0x70000 0x1000>;
1697 i2c1: i2c@0 {
1699 reg = <0x0 0x100>;
1702 #size-cells = <0>;
1707 target-module@72000 { /* 0x48072000, ap 32 2a.0 */
1709 reg = <0x72000 0x8>,
1710 <0x72010 0x8>,
1711 <0x72090 0x8>;
1723 clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1727 ranges = <0x0 0x72000 0x1000>;
1729 i2c2: i2c@0 {
1731 reg = <0x0 0x100>;
1734 #size-cells = <0>;
1739 target-module@78000 { /* 0x48078000, ap 39 0a.0 */
1741 reg = <0x78000 0x4>,
1742 <0x78010 0x4>,
1743 <0x78014 0x4>;
1754 clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1758 ranges = <0x0 0x78000 0x1000>;
1760 elm: elm@0 {
1762 reg = <0x0 0xfc0>; /* device IO registers */
1768 target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
1770 reg = <0x7a000 0x8>,
1771 <0x7a010 0x8>,
1772 <0x7a090 0x8>;
1784 clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1788 ranges = <0x0 0x7a000 0x1000>;
1790 i2c4: i2c@0 {
1792 reg = <0x0 0x100>;
1795 #size-cells = <0>;
1800 target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
1802 reg = <0x7c000 0x8>,
1803 <0x7c010 0x8>,
1804 <0x7c090 0x8>;
1816 clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1820 ranges = <0x0 0x7c000 0x1000>;
1822 i2c5: i2c@0 {
1824 reg = <0x0 0x100>;
1827 #size-cells = <0>;
1832 target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1834 reg = <0x86000 0x4>,
1835 <0x86010 0x4>;
1844 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1848 ranges = <0x0 0x86000 0x1000>;
1850 timer10: timer@0 {
1852 reg = <0x0 0x80>;
1859 target-module@88000 { /* 0x48088000, ap 43 66.0 */
1861 reg = <0x88000 0x4>,
1862 <0x88010 0x4>;
1871 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1875 ranges = <0x0 0x88000 0x1000>;
1877 timer11: timer@0 {
1879 reg = <0x0 0x80>;
1886 target-module@90000 { /* 0x48090000, ap 55 12.0 */
1888 reg = <0x91fe0 0x4>,
1889 <0x91fe4 0x4>;
1895 clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1899 ranges = <0x0 0x90000 0x2000>;
1901 rng: rng@0 {
1903 reg = <0x0 0x2000>;
1910 target-module@98000 { /* 0x48098000, ap 47 08.0 */
1912 reg = <0x98000 0x4>,
1913 <0x98010 0x4>;
1922 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1926 ranges = <0x0 0x98000 0x1000>;
1928 mcspi1: spi@0 {
1930 reg = <0x0 0x200>;
1933 #size-cells = <0>;
1949 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1951 reg = <0x9a000 0x4>,
1952 <0x9a010 0x4>;
1961 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1965 ranges = <0x0 0x9a000 0x1000>;
1967 mcspi2: spi@0 {
1969 reg = <0x0 0x200>;
1972 #size-cells = <0>;
1983 target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
1985 reg = <0x9c000 0x4>,
1986 <0x9c010 0x4>;
1999 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2003 ranges = <0x0 0x9c000 0x1000>;
2005 mmc1: mmc@0 {
2007 reg = <0x0 0x400>;
2017 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
2022 ranges = <0x0 0xa2000 0x1000>;
2025 target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
2030 ranges = <0x00000000 0x000a4000 0x00001000>,
2031 <0x00001000 0x000a5000 0x00001000>;
2034 des_target: target-module@a5000 { /* 0x480a5000 */
2036 reg = <0xa5030 0x4>,
2037 <0xa5034 0x4>,
2038 <0xa5038 0x4>;
2048 clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
2052 ranges = <0 0xa5000 0x00001000>;
2054 des: des@0 {
2056 reg = <0 0xa0>;
2065 target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
2070 ranges = <0x0 0xa8000 0x4000>;
2073 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
2075 reg = <0xad000 0x4>,
2076 <0xad010 0x4>;
2089 clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2093 ranges = <0x0 0xad000 0x1000>;
2095 mmc3: mmc@0 {
2097 reg = <0x0 0x400>;
2103 sdhci-caps-mask = <0x0 0x400000>;
2107 target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
2109 reg = <0xb2000 0x4>,
2110 <0xb2014 0x4>,
2111 <0xb2018 0x4>;
2118 clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2122 ranges = <0x0 0xb2000 0x1000>;
2124 hdqw1w: 1w@0 {
2126 reg = <0x0 0x1000>;
2131 target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
2133 reg = <0xb4000 0x4>,
2134 <0xb4010 0x4>;
2147 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2151 ranges = <0x0 0xb4000 0x1000>;
2153 mmc2: mmc@0 {
2155 reg = <0x0 0x400>;
2160 sdhci-caps-mask = <0x7 0x0>;
2167 target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
2169 reg = <0xb8000 0x4>,
2170 <0xb8010 0x4>;
2179 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2183 ranges = <0x0 0xb8000 0x1000>;
2185 mcspi3: spi@0 {
2187 reg = <0x0 0x200>;
2190 #size-cells = <0>;
2198 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2200 reg = <0xba000 0x4>,
2201 <0xba010 0x4>;
2210 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2214 ranges = <0x0 0xba000 0x1000>;
2216 mcspi4: spi@0 {
2218 reg = <0x0 0x200>;
2221 #size-cells = <0>;
2229 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2231 reg = <0xd1000 0x4>,
2232 <0xd1010 0x4>;
2245 clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2249 ranges = <0x0 0xd1000 0x1000>;
2251 mmc4: mmc@0 {
2253 reg = <0x0 0x400>;
2258 sdhci-caps-mask = <0x0 0x400000>;
2262 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2267 ranges = <0x0 0xd5000 0x1000>;
2271 segment@200000 { /* 0x48200000 */
2278 &l4_per2 { /* 0x48400000 */
2280 reg = <0x48400000 0x800>,
2281 <0x48400800 0x800>,
2282 <0x48401000 0x400>,
2283 <0x48401400 0x400>,
2284 <0x48401800 0x400>;
2288 ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */
2289 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2290 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2291 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2292 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2293 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2294 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2295 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2296 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2298 segment@0 { /* 0x48400000 */
2302 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2303 <0x00001000 0x00001000 0x000400>, /* ap 1 */
2304 <0x00000800 0x00000800 0x000800>, /* ap 2 */
2305 <0x00084000 0x00084000 0x004000>, /* ap 3 */
2306 <0x00001400 0x00001400 0x000400>, /* ap 4 */
2307 <0x00001800 0x00001800 0x000400>, /* ap 5 */
2308 <0x00088000 0x00088000 0x001000>, /* ap 6 */
2309 <0x0002c000 0x0002c000 0x001000>, /* ap 7 */
2310 <0x0002d000 0x0002d000 0x001000>, /* ap 8 */
2311 <0x00060000 0x00060000 0x002000>, /* ap 9 */
2312 <0x00062000 0x00062000 0x001000>, /* ap 10 */
2313 <0x00064000 0x00064000 0x002000>, /* ap 11 */
2314 <0x00066000 0x00066000 0x001000>, /* ap 12 */
2315 <0x00068000 0x00068000 0x002000>, /* ap 13 */
2316 <0x0006a000 0x0006a000 0x001000>, /* ap 14 */
2317 <0x0006c000 0x0006c000 0x002000>, /* ap 15 */
2318 <0x0006e000 0x0006e000 0x001000>, /* ap 16 */
2319 <0x00036000 0x00036000 0x001000>, /* ap 17 */
2320 <0x00037000 0x00037000 0x001000>, /* ap 18 */
2321 <0x00070000 0x00070000 0x002000>, /* ap 19 */
2322 <0x00072000 0x00072000 0x001000>, /* ap 20 */
2323 <0x0003a000 0x0003a000 0x001000>, /* ap 21 */
2324 <0x0003b000 0x0003b000 0x001000>, /* ap 22 */
2325 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
2326 <0x0003d000 0x0003d000 0x001000>, /* ap 24 */
2327 <0x0003e000 0x0003e000 0x001000>, /* ap 25 */
2328 <0x0003f000 0x0003f000 0x001000>, /* ap 26 */
2329 <0x00040000 0x00040000 0x001000>, /* ap 27 */
2330 <0x00041000 0x00041000 0x001000>, /* ap 28 */
2331 <0x00042000 0x00042000 0x001000>, /* ap 29 */
2332 <0x00043000 0x00043000 0x001000>, /* ap 30 */
2333 <0x00080000 0x00080000 0x002000>, /* ap 31 */
2334 <0x00082000 0x00082000 0x001000>, /* ap 32 */
2335 <0x0004a000 0x0004a000 0x001000>, /* ap 33 */
2336 <0x0004b000 0x0004b000 0x001000>, /* ap 34 */
2337 <0x00074000 0x00074000 0x002000>, /* ap 35 */
2338 <0x00076000 0x00076000 0x001000>, /* ap 36 */
2339 <0x00050000 0x00050000 0x001000>, /* ap 37 */
2340 <0x00051000 0x00051000 0x001000>, /* ap 38 */
2341 <0x00078000 0x00078000 0x002000>, /* ap 39 */
2342 <0x0007a000 0x0007a000 0x001000>, /* ap 40 */
2343 <0x00054000 0x00054000 0x001000>, /* ap 41 */
2344 <0x00055000 0x00055000 0x001000>, /* ap 42 */
2345 <0x0007c000 0x0007c000 0x002000>, /* ap 43 */
2346 <0x0007e000 0x0007e000 0x001000>, /* ap 44 */
2347 <0x0004c000 0x0004c000 0x001000>, /* ap 45 */
2348 <0x0004d000 0x0004d000 0x001000>, /* ap 46 */
2349 <0x00020000 0x00020000 0x001000>, /* ap 47 */
2350 <0x00021000 0x00021000 0x001000>, /* ap 48 */
2351 <0x00022000 0x00022000 0x001000>, /* ap 49 */
2352 <0x00023000 0x00023000 0x001000>, /* ap 50 */
2353 <0x00024000 0x00024000 0x001000>, /* ap 51 */
2354 <0x00025000 0x00025000 0x001000>, /* ap 52 */
2355 <0x00046000 0x00046000 0x001000>, /* ap 53 */
2356 <0x00047000 0x00047000 0x001000>, /* ap 54 */
2357 <0x00048000 0x00048000 0x001000>, /* ap 55 */
2358 <0x00049000 0x00049000 0x001000>, /* ap 56 */
2359 <0x00058000 0x00058000 0x002000>, /* ap 57 */
2360 <0x0005a000 0x0005a000 0x001000>, /* ap 58 */
2361 <0x0005b000 0x0005b000 0x001000>, /* ap 59 */
2362 <0x0005c000 0x0005c000 0x001000>, /* ap 60 */
2363 <0x0005d000 0x0005d000 0x001000>, /* ap 61 */
2364 <0x0005e000 0x0005e000 0x001000>, /* ap 62 */
2365 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2366 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2367 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2368 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2369 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2370 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2371 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2372 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2374 target-module@20000 { /* 0x48420000, ap 47 02.0 */
2376 reg = <0x20050 0x4>,
2377 <0x20054 0x4>,
2378 <0x20058 0x4>;
2389 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2393 ranges = <0x0 0x20000 0x1000>;
2395 uart7: serial@0 {
2397 reg = <0x0 0x100>;
2404 target-module@22000 { /* 0x48422000, ap 49 0a.0 */
2406 reg = <0x22050 0x4>,
2407 <0x22054 0x4>,
2408 <0x22058 0x4>;
2419 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2423 ranges = <0x0 0x22000 0x1000>;
2425 uart8: serial@0 {
2427 reg = <0x0 0x100>;
2434 target-module@24000 { /* 0x48424000, ap 51 12.0 */
2436 reg = <0x24050 0x4>,
2437 <0x24054 0x4>,
2438 <0x24058 0x4>;
2449 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2453 ranges = <0x0 0x24000 0x1000>;
2455 uart9: serial@0 {
2457 reg = <0x0 0x100>;
2464 target-module@2c000 { /* 0x4842c000, ap 7 18.0 */
2469 ranges = <0x0 0x2c000 0x1000>;
2472 target-module@36000 { /* 0x48436000, ap 17 06.0 */
2477 ranges = <0x0 0x36000 0x1000>;
2480 target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */
2485 ranges = <0x0 0x3a000 0x1000>;
2488 atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
2490 reg = <0x3c000 0x4>;
2492 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2496 ranges = <0x0 0x3c000 0x1000>;
2498 atl: atl@0 {
2500 reg = <0x0 0x3ff>;
2509 target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
2511 reg = <0x3e000 0x4>,
2512 <0x3e004 0x4>;
2519 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2523 ranges = <0x0 0x3e000 0x1000>;
2525 epwmss0: epwmss@0 {
2527 reg = <0x0 0x30>;
2531 ranges = <0 0 0x1000>;
2537 reg = <0x100 0x80>;
2547 reg = <0x200 0x80>;
2555 target-module@40000 { /* 0x48440000, ap 27 38.0 */
2557 reg = <0x40000 0x4>,
2558 <0x40004 0x4>;
2565 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2569 ranges = <0x0 0x40000 0x1000>;
2571 epwmss1: epwmss@0 {
2573 reg = <0x0 0x30>;
2577 ranges = <0 0 0x1000>;
2583 reg = <0x100 0x80>;
2593 reg = <0x200 0x80>;
2601 target-module@42000 { /* 0x48442000, ap 29 20.0 */
2603 reg = <0x42000 0x4>,
2604 <0x42004 0x4>;
2611 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2615 ranges = <0x0 0x42000 0x1000>;
2617 epwmss2: epwmss@0 {
2619 reg = <0x0 0x30>;
2623 ranges = <0 0 0x1000>;
2629 reg = <0x100 0x80>;
2639 reg = <0x200 0x80>;
2647 target-module@46000 { /* 0x48446000, ap 53 40.0 */
2652 ranges = <0x0 0x46000 0x1000>;
2655 target-module@48000 { /* 0x48448000, ap 55 48.0 */
2660 ranges = <0x0 0x48000 0x1000>;
2663 target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */
2668 ranges = <0x0 0x4a000 0x1000>;
2671 target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */
2676 ranges = <0x0 0x4c000 0x1000>;
2679 target-module@50000 { /* 0x48450000, ap 37 24.0 */
2684 ranges = <0x0 0x50000 0x1000>;
2687 target-module@54000 { /* 0x48454000, ap 41 2c.0 */
2692 ranges = <0x0 0x54000 0x1000>;
2695 target-module@58000 { /* 0x48458000, ap 57 28.0 */
2700 ranges = <0x0 0x58000 0x2000>;
2703 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
2708 ranges = <0x0 0x5b000 0x1000>;
2711 target-module@5d000 { /* 0x4845d000, ap 61 22.0 */
2716 ranges = <0x0 0x5d000 0x1000>;
2719 target-module@60000 { /* 0x48460000, ap 9 0e.0 */
2721 reg = <0x60000 0x4>,
2722 <0x60004 0x4>;
2728 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2734 ranges = <0x0 0x60000 0x2000>,
2735 <0x45800000 0x45800000 0x400000>;
2737 mcasp1: mcasp@0 {
2739 reg = <0x0 0x2000>,
2740 <0x45800000 0x1000>; /* L3 data port */
2747 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2755 target-module@64000 { /* 0x48464000, ap 11 1e.0 */
2757 reg = <0x64000 0x4>,
2758 <0x64004 0x4>;
2764 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2770 ranges = <0x0 0x64000 0x2000>,
2771 <0x45c00000 0x45c00000 0x400000>;
2773 mcasp2: mcasp@0 {
2775 reg = <0x0 0x2000>,
2776 <0x45c00000 0x1000>; /* L3 data port */
2783 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2791 target-module@68000 { /* 0x48468000, ap 13 26.0 */
2793 reg = <0x68000 0x4>,
2794 <0x68004 0x4>;
2800 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2805 ranges = <0x0 0x68000 0x2000>,
2806 <0x46000000 0x46000000 0x400000>;
2808 mcasp3: mcasp@0 {
2810 reg = <0x0 0x2000>,
2811 <0x46000000 0x1000>; /* L3 data port */
2818 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2825 target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
2827 reg = <0x6c000 0x4>,
2828 <0x6c004 0x4>;
2834 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2839 ranges = <0x0 0x6c000 0x2000>,
2840 <0x48436000 0x48436000 0x400000>;
2842 mcasp4: mcasp@0 {
2844 reg = <0x0 0x2000>,
2845 <0x48436000 0x1000>; /* L3 data port */
2852 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2859 target-module@70000 { /* 0x48470000, ap 19 36.0 */
2861 reg = <0x70000 0x4>,
2862 <0x70004 0x4>;
2868 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2873 ranges = <0x0 0x70000 0x2000>,
2874 <0x4843a000 0x4843a000 0x400000>;
2876 mcasp5: mcasp@0 {
2878 reg = <0x0 0x2000>,
2879 <0x4843a000 0x1000>; /* L3 data port */
2886 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2893 target-module@74000 { /* 0x48474000, ap 35 14.0 */
2895 reg = <0x74000 0x4>,
2896 <0x74004 0x4>;
2902 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2907 ranges = <0x0 0x74000 0x2000>,
2908 <0x4844c000 0x4844c000 0x400000>;
2910 mcasp6: mcasp@0 {
2912 reg = <0x0 0x2000>,
2913 <0x4844c000 0x1000>; /* L3 data port */
2920 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2927 target-module@78000 { /* 0x48478000, ap 39 0c.0 */
2929 reg = <0x78000 0x4>,
2930 <0x78004 0x4>;
2936 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2941 ranges = <0x0 0x78000 0x2000>,
2942 <0x48450000 0x48450000 0x400000>;
2944 mcasp7: mcasp@0 {
2946 reg = <0x0 0x2000>,
2947 <0x48450000 0x1000>; /* L3 data port */
2954 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2961 target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
2963 reg = <0x7c000 0x4>,
2964 <0x7c004 0x4>;
2970 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2975 ranges = <0x0 0x7c000 0x2000>,
2976 <0x48454000 0x48454000 0x400000>;
2978 mcasp8: mcasp@0 {
2980 reg = <0x0 0x2000>,
2981 <0x48454000 0x1000>; /* L3 data port */
2988 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2995 target-module@80000 { /* 0x48480000, ap 31 16.0 */
2997 reg = <0x80020 0x4>;
2999 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
3003 ranges = <0x0 0x80000 0x2000>;
3005 dcan2: can@0 {
3007 reg = <0x0 0x2000>;
3008 syscon-raminit = <&scm_conf 0x558 1>;
3015 target-module@84000 { /* 0x48484000, ap 3 10.0 */
3017 reg = <0x85200 0x4>,
3018 <0x85208 0x4>,
3019 <0x85204 0x4>;
3021 ti,sysc-mask = <0>;
3027 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3031 ranges = <0x0 0x84000 0x4000>;
3041 mac_sw: switch@0 {
3043 reg = <0x0 0x4000>;
3044 ranges = <0 0 0x4000>;
3060 #size-cells = <0>;
3082 #size-cells = <0>;
3084 reg = <0x1000 0x100>;
3096 &l4_per3 { /* 0x48800000 */
3098 reg = <0x48800000 0x800>,
3099 <0x48800800 0x800>,
3100 <0x48801000 0x400>,
3101 <0x48801400 0x400>,
3102 <0x48801800 0x400>;
3106 ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */
3108 segment@0 { /* 0x48800000 */
3112 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
3113 <0x00000800 0x00000800 0x000800>, /* ap 1 */
3114 <0x00001000 0x00001000 0x000400>, /* ap 2 */
3115 <0x00001400 0x00001400 0x000400>, /* ap 3 */
3116 <0x00001800 0x00001800 0x000400>, /* ap 4 */
3117 <0x00020000 0x00020000 0x001000>, /* ap 5 */
3118 <0x00021000 0x00021000 0x001000>, /* ap 6 */
3119 <0x00022000 0x00022000 0x001000>, /* ap 7 */
3120 <0x00023000 0x00023000 0x001000>, /* ap 8 */
3121 <0x00024000 0x00024000 0x001000>, /* ap 9 */
3122 <0x00025000 0x00025000 0x001000>, /* ap 10 */
3123 <0x00026000 0x00026000 0x001000>, /* ap 11 */
3124 <0x00027000 0x00027000 0x001000>, /* ap 12 */
3125 <0x00028000 0x00028000 0x001000>, /* ap 13 */
3126 <0x00029000 0x00029000 0x001000>, /* ap 14 */
3127 <0x0002a000 0x0002a000 0x001000>, /* ap 15 */
3128 <0x0002b000 0x0002b000 0x001000>, /* ap 16 */
3129 <0x0002c000 0x0002c000 0x001000>, /* ap 17 */
3130 <0x0002d000 0x0002d000 0x001000>, /* ap 18 */
3131 <0x0002e000 0x0002e000 0x001000>, /* ap 19 */
3132 <0x0002f000 0x0002f000 0x001000>, /* ap 20 */
3133 <0x00170000 0x00170000 0x010000>, /* ap 21 */
3134 <0x00180000 0x00180000 0x001000>, /* ap 22 */
3135 <0x00190000 0x00190000 0x010000>, /* ap 23 */
3136 <0x001a0000 0x001a0000 0x001000>, /* ap 24 */
3137 <0x001b0000 0x001b0000 0x010000>, /* ap 25 */
3138 <0x001c0000 0x001c0000 0x001000>, /* ap 26 */
3139 <0x001d0000 0x001d0000 0x010000>, /* ap 27 */
3140 <0x001e0000 0x001e0000 0x001000>, /* ap 28 */
3141 <0x00038000 0x00038000 0x001000>, /* ap 29 */
3142 <0x00039000 0x00039000 0x001000>, /* ap 30 */
3143 <0x0005c000 0x0005c000 0x001000>, /* ap 31 */
3144 <0x0005d000 0x0005d000 0x001000>, /* ap 32 */
3145 <0x0003a000 0x0003a000 0x001000>, /* ap 33 */
3146 <0x0003b000 0x0003b000 0x001000>, /* ap 34 */
3147 <0x0003c000 0x0003c000 0x001000>, /* ap 35 */
3148 <0x0003d000 0x0003d000 0x001000>, /* ap 36 */
3149 <0x0003e000 0x0003e000 0x001000>, /* ap 37 */
3150 <0x0003f000 0x0003f000 0x001000>, /* ap 38 */
3151 <0x00040000 0x00040000 0x001000>, /* ap 39 */
3152 <0x00041000 0x00041000 0x001000>, /* ap 40 */
3153 <0x00042000 0x00042000 0x001000>, /* ap 41 */
3154 <0x00043000 0x00043000 0x001000>, /* ap 42 */
3155 <0x00044000 0x00044000 0x001000>, /* ap 43 */
3156 <0x00045000 0x00045000 0x001000>, /* ap 44 */
3157 <0x00046000 0x00046000 0x001000>, /* ap 45 */
3158 <0x00047000 0x00047000 0x001000>, /* ap 46 */
3159 <0x00048000 0x00048000 0x001000>, /* ap 47 */
3160 <0x00049000 0x00049000 0x001000>, /* ap 48 */
3161 <0x0004a000 0x0004a000 0x001000>, /* ap 49 */
3162 <0x0004b000 0x0004b000 0x001000>, /* ap 50 */
3163 <0x0004c000 0x0004c000 0x001000>, /* ap 51 */
3164 <0x0004d000 0x0004d000 0x001000>, /* ap 52 */
3165 <0x0004e000 0x0004e000 0x001000>, /* ap 53 */
3166 <0x0004f000 0x0004f000 0x001000>, /* ap 54 */
3167 <0x00050000 0x00050000 0x001000>, /* ap 55 */
3168 <0x00051000 0x00051000 0x001000>, /* ap 56 */
3169 <0x00052000 0x00052000 0x001000>, /* ap 57 */
3170 <0x00053000 0x00053000 0x001000>, /* ap 58 */
3171 <0x00054000 0x00054000 0x001000>, /* ap 59 */
3172 <0x00055000 0x00055000 0x001000>, /* ap 60 */
3173 <0x00056000 0x00056000 0x001000>, /* ap 61 */
3174 <0x00057000 0x00057000 0x001000>, /* ap 62 */
3175 <0x00058000 0x00058000 0x001000>, /* ap 63 */
3176 <0x00059000 0x00059000 0x001000>, /* ap 64 */
3177 <0x0005a000 0x0005a000 0x001000>, /* ap 65 */
3178 <0x0005b000 0x0005b000 0x001000>, /* ap 66 */
3179 <0x00064000 0x00064000 0x001000>, /* ap 67 */
3180 <0x00065000 0x00065000 0x001000>, /* ap 68 */
3181 <0x0005e000 0x0005e000 0x001000>, /* ap 69 */
3182 <0x0005f000 0x0005f000 0x001000>, /* ap 70 */
3183 <0x00060000 0x00060000 0x001000>, /* ap 71 */
3184 <0x00061000 0x00061000 0x001000>, /* ap 72 */
3185 <0x00062000 0x00062000 0x001000>, /* ap 73 */
3186 <0x00063000 0x00063000 0x001000>, /* ap 74 */
3187 <0x00140000 0x00140000 0x020000>, /* ap 75 */
3188 <0x00160000 0x00160000 0x001000>, /* ap 76 */
3189 <0x00016000 0x00016000 0x001000>, /* ap 77 */
3190 <0x00017000 0x00017000 0x001000>, /* ap 78 */
3191 <0x000c0000 0x000c0000 0x020000>, /* ap 79 */
3192 <0x000e0000 0x000e0000 0x001000>, /* ap 80 */
3193 <0x00004000 0x00004000 0x001000>, /* ap 81 */
3194 <0x00005000 0x00005000 0x001000>, /* ap 82 */
3195 <0x00080000 0x00080000 0x020000>, /* ap 83 */
3196 <0x000a0000 0x000a0000 0x001000>, /* ap 84 */
3197 <0x00100000 0x00100000 0x020000>, /* ap 85 */
3198 <0x00120000 0x00120000 0x001000>, /* ap 86 */
3199 <0x00010000 0x00010000 0x001000>, /* ap 87 */
3200 <0x00011000 0x00011000 0x001000>, /* ap 88 */
3201 <0x0000a000 0x0000a000 0x001000>, /* ap 89 */
3202 <0x0000b000 0x0000b000 0x001000>, /* ap 90 */
3203 <0x0001c000 0x0001c000 0x001000>, /* ap 91 */
3204 <0x0001d000 0x0001d000 0x001000>, /* ap 92 */
3205 <0x0001e000 0x0001e000 0x001000>, /* ap 93 */
3206 <0x0001f000 0x0001f000 0x001000>, /* ap 94 */
3207 <0x00002000 0x00002000 0x001000>, /* ap 95 */
3208 <0x00003000 0x00003000 0x001000>; /* ap 96 */
3210 target-module@2000 { /* 0x48802000, ap 95 7c.0 */
3212 reg = <0x2000 0x4>,
3213 <0x2010 0x4>;
3220 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3224 ranges = <0x0 0x2000 0x1000>;
3226 mailbox13: mailbox@0 {
3228 reg = <0x0 0x200>;
3240 target-module@4000 { /* 0x48804000, ap 81 20.0 */
3245 ranges = <0x0 0x4000 0x1000>;
3248 target-module@a000 { /* 0x4880a000, ap 89 18.0 */
3253 ranges = <0x0 0xa000 0x1000>;
3256 target-module@10000 { /* 0x48810000, ap 87 28.0 */
3261 ranges = <0x0 0x10000 0x1000>;
3264 target-module@16000 { /* 0x48816000, ap 77 1e.0 */
3269 ranges = <0x0 0x16000 0x1000>;
3272 target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */
3277 ranges = <0x0 0x1c000 0x1000>;
3280 target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */
3285 ranges = <0x0 0x1e000 0x1000>;
3288 target-module@20000 { /* 0x48820000, ap 5 08.0 */
3290 reg = <0x20000 0x4>,
3291 <0x20010 0x4>;
3300 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3304 ranges = <0x0 0x20000 0x1000>;
3306 timer5: timer@0 {
3308 reg = <0x0 0x80>;
3315 target-module@22000 { /* 0x48822000, ap 7 24.0 */
3317 reg = <0x22000 0x4>,
3318 <0x22010 0x4>;
3327 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3331 ranges = <0x0 0x22000 0x1000>;
3333 timer6: timer@0 {
3335 reg = <0x0 0x80>;
3342 target-module@24000 { /* 0x48824000, ap 9 26.0 */
3344 reg = <0x24000 0x4>,
3345 <0x24010 0x4>;
3354 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3358 ranges = <0x0 0x24000 0x1000>;
3360 timer7: timer@0 {
3362 reg = <0x0 0x80>;
3369 target-module@26000 { /* 0x48826000, ap 11 0c.0 */
3371 reg = <0x26000 0x4>,
3372 <0x26010 0x4>;
3381 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3385 ranges = <0x0 0x26000 0x1000>;
3387 timer8: timer@0 {
3389 reg = <0x0 0x80>;
3396 target-module@28000 { /* 0x48828000, ap 13 16.0 */
3398 reg = <0x28000 0x4>,
3399 <0x28010 0x4>;
3408 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3412 ranges = <0x0 0x28000 0x1000>;
3414 timer13: timer@0 {
3416 reg = <0x0 0x80>;
3424 target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
3426 reg = <0x2a000 0x4>,
3427 <0x2a010 0x4>;
3436 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3440 ranges = <0x0 0x2a000 0x1000>;
3442 timer14: timer@0 {
3444 reg = <0x0 0x80>;
3452 target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
3454 reg = <0x2c000 0x4>,
3455 <0x2c010 0x4>;
3464 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3468 ranges = <0x0 0x2c000 0x1000>;
3470 timer15: timer@0 {
3472 reg = <0x0 0x80>;
3480 target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
3482 reg = <0x2e000 0x4>,
3483 <0x2e010 0x4>;
3492 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3496 ranges = <0x0 0x2e000 0x1000>;
3498 timer16: timer@0 {
3500 reg = <0x0 0x80>;
3508 rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
3510 reg = <0x38074 0x4>,
3511 <0x38078 0x4>;
3518 clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3522 ranges = <0x0 0x38000 0x1000>;
3524 rtc: rtc@0 {
3526 reg = <0x0 0x100>;
3533 target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
3535 reg = <0x3a000 0x4>,
3536 <0x3a010 0x4>;
3543 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3547 ranges = <0x0 0x3a000 0x1000>;
3549 mailbox2: mailbox@0 {
3551 reg = <0x0 0x200>;
3563 target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
3565 reg = <0x3c000 0x4>,
3566 <0x3c010 0x4>;
3573 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3577 ranges = <0x0 0x3c000 0x1000>;
3579 mailbox3: mailbox@0 {
3581 reg = <0x0 0x200>;
3593 target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
3595 reg = <0x3e000 0x4>,
3596 <0x3e010 0x4>;
3603 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3607 ranges = <0x0 0x3e000 0x1000>;
3609 mailbox4: mailbox@0 {
3611 reg = <0x0 0x200>;
3623 target-module@40000 { /* 0x48840000, ap 39 64.0 */
3625 reg = <0x40000 0x4>,
3626 <0x40010 0x4>;
3633 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3637 ranges = <0x0 0x40000 0x1000>;
3639 mailbox5: mailbox@0 {
3641 reg = <0x0 0x200>;
3653 target-module@42000 { /* 0x48842000, ap 41 4e.0 */
3655 reg = <0x42000 0x4>,
3656 <0x42010 0x4>;
3663 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3667 ranges = <0x0 0x42000 0x1000>;
3669 mailbox6: mailbox@0 {
3671 reg = <0x0 0x200>;
3683 target-module@44000 { /* 0x48844000, ap 43 42.0 */
3685 reg = <0x44000 0x4>,
3686 <0x44010 0x4>;
3693 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3697 ranges = <0x0 0x44000 0x1000>;
3699 mailbox7: mailbox@0 {
3701 reg = <0x0 0x200>;
3713 target-module@46000 { /* 0x48846000, ap 45 48.0 */
3715 reg = <0x46000 0x4>,
3716 <0x46010 0x4>;
3723 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3727 ranges = <0x0 0x46000 0x1000>;
3729 mailbox8: mailbox@0 {
3731 reg = <0x0 0x200>;
3743 target-module@48000 { /* 0x48848000, ap 47 36.0 */
3748 ranges = <0x0 0x48000 0x1000>;
3751 target-module@4a000 { /* 0x4884a000, ap 49 38.0 */
3756 ranges = <0x0 0x4a000 0x1000>;
3759 target-module@4c000 { /* 0x4884c000, ap 51 44.0 */
3764 ranges = <0x0 0x4c000 0x1000>;
3767 target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */
3772 ranges = <0x0 0x4e000 0x1000>;
3775 target-module@50000 { /* 0x48850000, ap 55 40.0 */
3780 ranges = <0x0 0x50000 0x1000>;
3783 target-module@52000 { /* 0x48852000, ap 57 54.0 */
3788 ranges = <0x0 0x52000 0x1000>;
3791 target-module@54000 { /* 0x48854000, ap 59 1a.0 */
3796 ranges = <0x0 0x54000 0x1000>;
3799 target-module@56000 { /* 0x48856000, ap 61 22.0 */
3804 ranges = <0x0 0x56000 0x1000>;
3807 target-module@58000 { /* 0x48858000, ap 63 2a.0 */
3812 ranges = <0x0 0x58000 0x1000>;
3815 target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */
3820 ranges = <0x0 0x5a000 0x1000>;
3823 target-module@5c000 { /* 0x4885c000, ap 31 32.0 */
3828 ranges = <0x0 0x5c000 0x1000>;
3831 target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
3833 reg = <0x5e000 0x4>,
3834 <0x5e010 0x4>;
3841 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3845 ranges = <0x0 0x5e000 0x1000>;
3847 mailbox9: mailbox@0 {
3849 reg = <0x0 0x200>;
3861 target-module@60000 { /* 0x48860000, ap 71 4a.0 */
3863 reg = <0x60000 0x4>,
3864 <0x60010 0x4>;
3871 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3875 ranges = <0x0 0x60000 0x1000>;
3877 mailbox10: mailbox@0 {
3879 reg = <0x0 0x200>;
3891 target-module@62000 { /* 0x48862000, ap 73 74.0 */
3893 reg = <0x62000 0x4>,
3894 <0x62010 0x4>;
3901 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3905 ranges = <0x0 0x62000 0x1000>;
3907 mailbox11: mailbox@0 {
3909 reg = <0x0 0x200>;
3921 target-module@64000 { /* 0x48864000, ap 67 52.0 */
3923 reg = <0x64000 0x4>,
3924 <0x64010 0x4>;
3931 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3935 ranges = <0x0 0x64000 0x1000>;
3937 mailbox12: mailbox@0 {
3939 reg = <0x0 0x200>;
3951 target-module@80000 { /* 0x48880000, ap 83 0e.1 */
3953 reg = <0x80000 0x4>,
3954 <0x80010 0x4>;
3966 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
3970 ranges = <0x0 0x80000 0x20000>;
3972 omap_dwc3_1: omap_dwc3_1@0 {
3974 reg = <0x0 0x10000>;
3979 ranges = <0 0 0x20000>;
3983 reg = <0x10000 0x17000>;
4000 target-module@c0000 { /* 0x488c0000, ap 79 06.0 */
4002 reg = <0xc0000 0x4>,
4003 <0xc0010 0x4>;
4015 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4019 ranges = <0x0 0xc0000 0x20000>;
4021 omap_dwc3_2: omap_dwc3_2@0 {
4023 reg = <0x0 0x10000>;
4028 ranges = <0 0 0x20000>;
4032 reg = <0x10000 0x17000>;
4050 usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */
4052 reg = <0x100000 0x4>,
4053 <0x100010 0x4>;
4065 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4069 ranges = <0x0 0x100000 0x20000>;
4071 omap_dwc3_3: omap_dwc3_3@0 {
4073 reg = <0x0 0x10000>;
4078 ranges = <0 0 0x20000>;
4083 reg = <0x10000 0x17000>;
4098 usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
4100 reg = <0x140000 0x4>,
4101 <0x140010 0x4>;
4113 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
4117 ranges = <0x0 0x140000 0x20000>;
4120 target-module@170000 { /* 0x48970000, ap 21 0a.0 */
4122 reg = <0x170010 0x4>;
4130 clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
4134 ranges = <0x0 0x170000 0x10000>;
4138 target-module@190000 { /* 0x48990000, ap 23 2e.0 */
4140 reg = <0x190010 0x4>;
4148 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
4152 ranges = <0x0 0x190000 0x10000>;
4156 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
4158 reg = <0x1b0000 0x4>,
4159 <0x1b0010 0x4>;
4167 clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
4171 ranges = <0x0 0x1b0000 0x10000>;
4175 target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
4177 reg = <0x1d0010 0x4>;
4185 clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
4189 ranges = <0x0 0x1d0000 0x10000>;
4191 vpe: vpe@0 {
4193 reg = <0x0000 0x120>,
4194 <0x0700 0x80>,
4195 <0x5700 0x18>,
4196 <0xd000 0x400>;
4207 &l4_wkup { /* 0x4ae00000 */
4209 reg = <0x4ae00000 0x800>,
4210 <0x4ae00800 0x800>,
4211 <0x4ae01000 0x1000>;
4215 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
4216 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
4217 <0x00020000 0x4ae20000 0x010000>, /* segment 2 */
4218 <0x00030000 0x4ae30000 0x010000>; /* segment 3 */
4220 segment@0 { /* 0x4ae00000 */
4224 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
4225 <0x00001000 0x00001000 0x001000>, /* ap 1 */
4226 <0x00000800 0x00000800 0x000800>, /* ap 2 */
4227 <0x00006000 0x00006000 0x002000>, /* ap 3 */
4228 <0x00008000 0x00008000 0x001000>, /* ap 4 */
4229 <0x00004000 0x00004000 0x001000>, /* ap 15 */
4230 <0x00005000 0x00005000 0x001000>, /* ap 16 */
4231 <0x0000c000 0x0000c000 0x001000>, /* ap 17 */
4232 <0x0000d000 0x0000d000 0x001000>; /* ap 18 */
4234 target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
4236 reg = <0x4000 0x4>,
4237 <0x4010 0x4>;
4244 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4248 ranges = <0x0 0x4000 0x1000>;
4250 counter32k: counter@0 {
4252 reg = <0x0 0x40>;
4256 target-module@6000 { /* 0x4ae06000, ap 3 10.0 */
4258 reg = <0x6000 0x4>;
4262 ranges = <0x0 0x6000 0x2000>;
4264 prm: prm@0 {
4266 reg = <0 0x3000>;
4270 ranges = <0 0 0x3000>;
4274 #size-cells = <0>;
4282 target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */
4284 reg = <0xc000 0x4>;
4288 ranges = <0x0 0xc000 0x1000>;
4290 scm_wkup: scm_conf@0 {
4292 reg = <0 0x1000>;
4297 segment@10000 { /* 0x4ae10000 */
4301 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
4302 <0x00001000 0x00011000 0x001000>, /* ap 6 */
4303 <0x00004000 0x00014000 0x001000>, /* ap 7 */
4304 <0x00005000 0x00015000 0x001000>, /* ap 8 */
4305 <0x00008000 0x00018000 0x001000>, /* ap 9 */
4306 <0x00009000 0x00019000 0x001000>, /* ap 10 */
4307 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
4308 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
4310 target-module@0 { /* 0x4ae10000, ap 5 20.0 */
4312 reg = <0x0 0x4>,
4313 <0x10 0x4>,
4314 <0x114 0x4>;
4325 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4330 ranges = <0x0 0x0 0x1000>;
4332 gpio1: gpio@0 {
4334 reg = <0x0 0x200>;
4343 target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
4345 reg = <0x4000 0x4>,
4346 <0x4010 0x4>,
4347 <0x4014 0x4>;
4357 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4361 ranges = <0x0 0x4000 0x1000>;
4363 wdt2: wdt@0 {
4365 reg = <0x0 0x80>;
4370 timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
4372 reg = <0x8000 0x4>,
4373 <0x8010 0x4>;
4382 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4386 ranges = <0x0 0x8000 0x1000>;
4388 timer1: timer@0 {
4390 reg = <0x0 0x80>;
4398 target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */
4403 ranges = <0x0 0xc000 0x1000>;
4407 segment@20000 { /* 0x4ae20000 */
4411 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
4412 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
4413 <0x00000000 0x00020000 0x001000>, /* ap 19 */
4414 <0x00001000 0x00021000 0x001000>, /* ap 20 */
4415 <0x00002000 0x00022000 0x001000>, /* ap 21 */
4416 <0x00003000 0x00023000 0x001000>, /* ap 22 */
4417 <0x00007000 0x00027000 0x000400>, /* ap 23 */
4418 <0x00008000 0x00028000 0x000800>, /* ap 24 */
4419 <0x00009000 0x00029000 0x000100>, /* ap 25 */
4420 <0x00008800 0x00028800 0x000200>, /* ap 26 */
4421 <0x00008a00 0x00028a00 0x000100>, /* ap 27 */
4422 <0x0000b000 0x0002b000 0x001000>, /* ap 28 */
4423 <0x0000c000 0x0002c000 0x001000>, /* ap 29 */
4424 <0x0000f000 0x0002f000 0x001000>; /* ap 32 */
4426 target-module@0 { /* 0x4ae20000, ap 19 08.0 */
4428 reg = <0x0 0x4>,
4429 <0x10 0x4>;
4438 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4442 ranges = <0x0 0x0 0x1000>;
4444 timer12: timer@0 {
4446 reg = <0x0 0x80>;
4453 target-module@2000 { /* 0x4ae22000, ap 21 18.0 */
4458 ranges = <0x0 0x2000 0x1000>;
4461 target-module@6000 { /* 0x4ae26000, ap 13 48.0 */
4466 ranges = <0x00000000 0x00006000 0x00001000>,
4467 <0x00001000 0x00007000 0x00000400>,
4468 <0x00002000 0x00008000 0x00000800>,
4469 <0x00002800 0x00008800 0x00000200>,
4470 <0x00002a00 0x00008a00 0x00000100>,
4471 <0x00003000 0x00009000 0x00000100>;
4474 target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */
4476 reg = <0xb050 0x4>,
4477 <0xb054 0x4>,
4478 <0xb058 0x4>;
4489 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4493 ranges = <0x0 0xb000 0x1000>;
4495 uart10: serial@0 {
4497 reg = <0x0 0x100>;
4504 target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */
4509 ranges = <0x0 0xf000 0x1000>;
4513 segment@30000 { /* 0x4ae30000 */
4517 ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */
4518 <0x0000e000 0x0003e000 0x001000>, /* ap 31 */
4519 <0x00000000 0x00030000 0x001000>, /* ap 33 */
4520 <0x00001000 0x00031000 0x001000>, /* ap 34 */
4521 <0x00002000 0x00032000 0x001000>, /* ap 35 */
4522 <0x00003000 0x00033000 0x001000>, /* ap 36 */
4523 <0x00004000 0x00034000 0x001000>, /* ap 37 */
4524 <0x00005000 0x00035000 0x001000>, /* ap 38 */
4525 <0x00006000 0x00036000 0x001000>, /* ap 39 */
4526 <0x00007000 0x00037000 0x001000>, /* ap 40 */
4527 <0x00008000 0x00038000 0x001000>, /* ap 41 */
4528 <0x00009000 0x00039000 0x001000>, /* ap 42 */
4529 <0x0000a000 0x0003a000 0x001000>; /* ap 43 */
4531 target-module@1000 { /* 0x4ae31000, ap 34 60.0 */
4536 ranges = <0x0 0x1000 0x1000>;
4539 target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */
4544 ranges = <0x0 0x3000 0x1000>;
4547 target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */
4552 ranges = <0x0 0x5000 0x1000>;
4555 target-module@7000 { /* 0x4ae37000, ap 40 68.0 */
4560 ranges = <0x0 0x7000 0x1000>;
4563 target-module@9000 { /* 0x4ae39000, ap 42 70.0 */
4568 ranges = <0x0 0x9000 0x1000>;
4571 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */
4573 reg = <0xc020 0x4>;
4575 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4579 ranges = <0x0 0xc000 0x2000>;
4581 dcan1: can@0 {
4583 reg = <0x0 0x2000>;
4584 syscon-raminit = <&scm_conf 0x558 0>;