1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8996.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/soc/qcom,apr.h>
10
11/ {
12	interrupt-parent = <&intc>;
13
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	chosen { };
18
19	clocks {
20		xo_board: xo_board {
21			compatible = "fixed-clock";
22			#clock-cells = <0>;
23			clock-frequency = <19200000>;
24			clock-output-names = "xo_board";
25		};
26
27		sleep_clk: sleep_clk {
28			compatible = "fixed-clock";
29			#clock-cells = <0>;
30			clock-frequency = <32764>;
31			clock-output-names = "sleep_clk";
32		};
33	};
34
35	cpus {
36		#address-cells = <2>;
37		#size-cells = <0>;
38
39		CPU0: cpu@0 {
40			device_type = "cpu";
41			compatible = "qcom,kryo";
42			reg = <0x0 0x0>;
43			enable-method = "psci";
44			cpu-idle-states = <&CPU_SLEEP_0>;
45			capacity-dmips-mhz = <1024>;
46			next-level-cache = <&L2_0>;
47			L2_0: l2-cache {
48			      compatible = "cache";
49			      cache-level = <2>;
50			};
51		};
52
53		CPU1: cpu@1 {
54			device_type = "cpu";
55			compatible = "qcom,kryo";
56			reg = <0x0 0x1>;
57			enable-method = "psci";
58			cpu-idle-states = <&CPU_SLEEP_0>;
59			capacity-dmips-mhz = <1024>;
60			next-level-cache = <&L2_0>;
61		};
62
63		CPU2: cpu@100 {
64			device_type = "cpu";
65			compatible = "qcom,kryo";
66			reg = <0x0 0x100>;
67			enable-method = "psci";
68			cpu-idle-states = <&CPU_SLEEP_0>;
69			capacity-dmips-mhz = <1024>;
70			next-level-cache = <&L2_1>;
71			L2_1: l2-cache {
72			      compatible = "cache";
73			      cache-level = <2>;
74			};
75		};
76
77		CPU3: cpu@101 {
78			device_type = "cpu";
79			compatible = "qcom,kryo";
80			reg = <0x0 0x101>;
81			enable-method = "psci";
82			cpu-idle-states = <&CPU_SLEEP_0>;
83			capacity-dmips-mhz = <1024>;
84			next-level-cache = <&L2_1>;
85		};
86
87		cpu-map {
88			cluster0 {
89				core0 {
90					cpu = <&CPU0>;
91				};
92
93				core1 {
94					cpu = <&CPU1>;
95				};
96			};
97
98			cluster1 {
99				core0 {
100					cpu = <&CPU2>;
101				};
102
103				core1 {
104					cpu = <&CPU3>;
105				};
106			};
107		};
108
109		idle-states {
110			entry-method = "psci";
111
112			CPU_SLEEP_0: cpu-sleep-0 {
113				compatible = "arm,idle-state";
114				idle-state-name = "standalone-power-collapse";
115				arm,psci-suspend-param = <0x00000004>;
116				entry-latency-us = <130>;
117				exit-latency-us = <80>;
118				min-residency-us = <300>;
119			};
120		};
121	};
122
123	firmware {
124		scm {
125			compatible = "qcom,scm-msm8996";
126			qcom,dload-mode = <&tcsr 0x13000>;
127		};
128	};
129
130	tcsr_mutex: hwlock {
131		compatible = "qcom,tcsr-mutex";
132		syscon = <&tcsr_mutex_regs 0 0x1000>;
133		#hwlock-cells = <1>;
134	};
135
136	memory {
137		device_type = "memory";
138		/* We expect the bootloader to fill in the reg */
139		reg = <0 0 0 0>;
140	};
141
142	psci {
143		compatible = "arm,psci-1.0";
144		method = "smc";
145	};
146
147	reserved-memory {
148		#address-cells = <2>;
149		#size-cells = <2>;
150		ranges;
151
152		mba_region: mba@91500000 {
153			reg = <0x0 0x91500000 0x0 0x200000>;
154			no-map;
155		};
156
157		slpi_region: slpi@90b00000 {
158			reg = <0x0 0x90b00000 0x0 0xa00000>;
159			no-map;
160		};
161
162		venus_region: venus@90400000 {
163			reg = <0x0 0x90400000 0x0 0x700000>;
164			no-map;
165		};
166
167		adsp_region: adsp@8ea00000 {
168			reg = <0x0 0x8ea00000 0x0 0x1a00000>;
169			no-map;
170		};
171
172		mpss_region: mpss@88800000 {
173			reg = <0x0 0x88800000 0x0 0x6200000>;
174			no-map;
175		};
176
177		smem_mem: smem-mem@86000000 {
178			reg = <0x0 0x86000000 0x0 0x200000>;
179			no-map;
180		};
181
182		memory@85800000 {
183			reg = <0x0 0x85800000 0x0 0x800000>;
184			no-map;
185		};
186
187		memory@86200000 {
188			reg = <0x0 0x86200000 0x0 0x2600000>;
189			no-map;
190		};
191
192		rmtfs@86700000 {
193			compatible = "qcom,rmtfs-mem";
194
195			size = <0x0 0x200000>;
196			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
197			no-map;
198
199			qcom,client-id = <1>;
200			qcom,vmid = <15>;
201		};
202
203		zap_shader_region: gpu@8f200000 {
204			compatible = "shared-dma-pool";
205			reg = <0x0 0x90b00000 0x0 0xa00000>;
206			no-map;
207		};
208	};
209
210	rpm-glink {
211		compatible = "qcom,glink-rpm";
212
213		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
214
215		qcom,rpm-msg-ram = <&rpm_msg_ram>;
216
217		mboxes = <&apcs_glb 0>;
218
219		rpm_requests: rpm-requests {
220			compatible = "qcom,rpm-msm8996";
221			qcom,glink-channels = "rpm_requests";
222
223			rpmcc: qcom,rpmcc {
224				compatible = "qcom,rpmcc-msm8996";
225				#clock-cells = <1>;
226			};
227
228			rpmpd: power-controller {
229				compatible = "qcom,msm8996-rpmpd";
230				#power-domain-cells = <1>;
231				operating-points-v2 = <&rpmpd_opp_table>;
232
233				rpmpd_opp_table: opp-table {
234					compatible = "operating-points-v2";
235
236					rpmpd_opp1: opp1 {
237						opp-level = <1>;
238					};
239
240					rpmpd_opp2: opp2 {
241						opp-level = <2>;
242					};
243
244					rpmpd_opp3: opp3 {
245						opp-level = <3>;
246					};
247
248					rpmpd_opp4: opp4 {
249						opp-level = <4>;
250					};
251
252					rpmpd_opp5: opp5 {
253						opp-level = <5>;
254					};
255
256					rpmpd_opp6: opp6 {
257						opp-level = <6>;
258					};
259				};
260			};
261		};
262	};
263
264	smem {
265		compatible = "qcom,smem";
266		memory-region = <&smem_mem>;
267		hwlocks = <&tcsr_mutex 3>;
268	};
269
270	smp2p-adsp {
271		compatible = "qcom,smp2p";
272		qcom,smem = <443>, <429>;
273
274		interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
275
276		mboxes = <&apcs_glb 10>;
277
278		qcom,local-pid = <0>;
279		qcom,remote-pid = <2>;
280
281		smp2p_adsp_out: master-kernel {
282			qcom,entry-name = "master-kernel";
283			#qcom,smem-state-cells = <1>;
284		};
285
286		smp2p_adsp_in: slave-kernel {
287			qcom,entry-name = "slave-kernel";
288
289			interrupt-controller;
290			#interrupt-cells = <2>;
291		};
292	};
293
294	smp2p-modem {
295		compatible = "qcom,smp2p";
296		qcom,smem = <435>, <428>;
297
298		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
299
300		mboxes = <&apcs_glb 14>;
301
302		qcom,local-pid = <0>;
303		qcom,remote-pid = <1>;
304
305		modem_smp2p_out: master-kernel {
306			qcom,entry-name = "master-kernel";
307			#qcom,smem-state-cells = <1>;
308		};
309
310		modem_smp2p_in: slave-kernel {
311			qcom,entry-name = "slave-kernel";
312
313			interrupt-controller;
314			#interrupt-cells = <2>;
315		};
316	};
317
318	smp2p-slpi {
319		compatible = "qcom,smp2p";
320		qcom,smem = <481>, <430>;
321
322		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
323
324		mboxes = <&apcs_glb 26>;
325
326		qcom,local-pid = <0>;
327		qcom,remote-pid = <3>;
328
329		smp2p_slpi_in: slave-kernel {
330			qcom,entry-name = "slave-kernel";
331			interrupt-controller;
332			#interrupt-cells = <2>;
333		};
334
335		smp2p_slpi_out: master-kernel {
336			qcom,entry-name = "master-kernel";
337			#qcom,smem-state-cells = <1>;
338		};
339	};
340
341	soc: soc {
342		#address-cells = <1>;
343		#size-cells = <1>;
344		ranges = <0 0 0 0xffffffff>;
345		compatible = "simple-bus";
346
347		pcie_phy: phy@34000 {
348			compatible = "qcom,msm8996-qmp-pcie-phy";
349			reg = <0x00034000 0x488>;
350			#clock-cells = <1>;
351			#address-cells = <1>;
352			#size-cells = <1>;
353			ranges;
354
355			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
356				<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
357				<&gcc GCC_PCIE_CLKREF_CLK>;
358			clock-names = "aux", "cfg_ahb", "ref";
359
360			resets = <&gcc GCC_PCIE_PHY_BCR>,
361				<&gcc GCC_PCIE_PHY_COM_BCR>,
362				<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
363			reset-names = "phy", "common", "cfg";
364			status = "disabled";
365
366			pciephy_0: lane@35000 {
367				reg = <0x00035000 0x130>,
368				      <0x00035200 0x200>,
369				      <0x00035400 0x1dc>;
370				#phy-cells = <0>;
371
372				clock-output-names = "pcie_0_pipe_clk_src";
373				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
374				clock-names = "pipe0";
375				resets = <&gcc GCC_PCIE_0_PHY_BCR>;
376				reset-names = "lane0";
377			};
378
379			pciephy_1: lane@36000 {
380				reg = <0x00036000 0x130>,
381				      <0x00036200 0x200>,
382				      <0x00036400 0x1dc>;
383				#phy-cells = <0>;
384
385				clock-output-names = "pcie_1_pipe_clk_src";
386				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
387				clock-names = "pipe1";
388				resets = <&gcc GCC_PCIE_1_PHY_BCR>;
389				reset-names = "lane1";
390			};
391
392			pciephy_2: lane@37000 {
393				reg = <0x00037000 0x130>,
394				      <0x00037200 0x200>,
395				      <0x00037400 0x1dc>;
396				#phy-cells = <0>;
397
398				clock-output-names = "pcie_2_pipe_clk_src";
399				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
400				clock-names = "pipe2";
401				resets = <&gcc GCC_PCIE_2_PHY_BCR>;
402				reset-names = "lane2";
403			};
404		};
405
406		rpm_msg_ram: memory@68000 {
407			compatible = "qcom,rpm-msg-ram";
408			reg = <0x00068000 0x6000>;
409		};
410
411		qfprom@74000 {
412			compatible = "qcom,qfprom";
413			reg = <0x00074000 0x8ff>;
414			#address-cells = <1>;
415			#size-cells = <1>;
416
417			qusb2p_hstx_trim: hstx_trim@24e {
418				reg = <0x24e 0x2>;
419				bits = <5 4>;
420			};
421
422			qusb2s_hstx_trim: hstx_trim@24f {
423				reg = <0x24f 0x1>;
424				bits = <1 4>;
425			};
426
427			gpu_speed_bin: gpu_speed_bin@133 {
428				reg = <0x133 0x1>;
429				bits = <5 3>;
430			};
431		};
432
433		rng: rng@83000 {
434			compatible = "qcom,prng-ee";
435			reg = <0x00083000 0x1000>;
436			clocks = <&gcc GCC_PRNG_AHB_CLK>;
437			clock-names = "core";
438		};
439
440		gcc: clock-controller@300000 {
441			compatible = "qcom,gcc-msm8996";
442			#clock-cells = <1>;
443			#reset-cells = <1>;
444			#power-domain-cells = <1>;
445			reg = <0x00300000 0x90000>;
446
447			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
448			clock-names = "cxo2";
449		};
450
451		tsens0: thermal-sensor@4a9000 {
452			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
453			reg = <0x004a9000 0x1000>, /* TM */
454			      <0x004a8000 0x1000>; /* SROT */
455			#qcom,sensors = <13>;
456			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
457				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
458			interrupt-names = "uplow", "critical";
459			#thermal-sensor-cells = <1>;
460		};
461
462		tsens1: thermal-sensor@4ad000 {
463			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
464			reg = <0x004ad000 0x1000>, /* TM */
465			      <0x004ac000 0x1000>; /* SROT */
466			#qcom,sensors = <8>;
467			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
468				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
469			interrupt-names = "uplow", "critical";
470			#thermal-sensor-cells = <1>;
471		};
472
473		tcsr_mutex_regs: syscon@740000 {
474			compatible = "syscon";
475			reg = <0x00740000 0x20000>;
476		};
477
478		tcsr: syscon@7a0000 {
479			compatible = "qcom,tcsr-msm8996", "syscon";
480			reg = <0x007a0000 0x18000>;
481		};
482
483		mmcc: clock-controller@8c0000 {
484			compatible = "qcom,mmcc-msm8996";
485			#clock-cells = <1>;
486			#reset-cells = <1>;
487			#power-domain-cells = <1>;
488			reg = <0x008c0000 0x40000>;
489			assigned-clocks = <&mmcc MMPLL9_PLL>,
490					  <&mmcc MMPLL1_PLL>,
491					  <&mmcc MMPLL3_PLL>,
492					  <&mmcc MMPLL4_PLL>,
493					  <&mmcc MMPLL5_PLL>;
494			assigned-clock-rates = <624000000>,
495					       <810000000>,
496					       <980000000>,
497					       <960000000>,
498					       <825000000>;
499		};
500
501		mdss: mdss@900000 {
502			compatible = "qcom,mdss";
503
504			reg = <0x00900000 0x1000>,
505			      <0x009b0000 0x1040>,
506			      <0x009b8000 0x1040>;
507			reg-names = "mdss_phys",
508				    "vbif_phys",
509				    "vbif_nrt_phys";
510
511			power-domains = <&mmcc MDSS_GDSC>;
512			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
513
514			interrupt-controller;
515			#interrupt-cells = <1>;
516
517			clocks = <&mmcc MDSS_AHB_CLK>;
518			clock-names = "iface";
519
520			#address-cells = <1>;
521			#size-cells = <1>;
522			ranges;
523
524			mdp: mdp@901000 {
525				compatible = "qcom,mdp5";
526				reg = <0x00901000 0x90000>;
527				reg-names = "mdp_phys";
528
529				interrupt-parent = <&mdss>;
530				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
531
532				clocks = <&mmcc MDSS_AHB_CLK>,
533					 <&mmcc MDSS_AXI_CLK>,
534					 <&mmcc MDSS_MDP_CLK>,
535					 <&mmcc SMMU_MDP_AXI_CLK>,
536					 <&mmcc MDSS_VSYNC_CLK>;
537				clock-names = "iface",
538					      "bus",
539					      "core",
540					      "iommu",
541					      "vsync";
542
543				iommus = <&mdp_smmu 0>;
544
545				ports {
546					#address-cells = <1>;
547					#size-cells = <0>;
548
549					port@0 {
550						reg = <0>;
551						mdp5_intf3_out: endpoint {
552							remote-endpoint = <&hdmi_in>;
553						};
554					};
555				};
556			};
557
558			hdmi: hdmi-tx@9a0000 {
559				compatible = "qcom,hdmi-tx-8996";
560				reg =	<0x009a0000 0x50c>,
561					<0x00070000 0x6158>,
562					<0x009e0000 0xfff>;
563				reg-names = "core_physical",
564					    "qfprom_physical",
565					    "hdcp_physical";
566
567				interrupt-parent = <&mdss>;
568				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
569
570				clocks = <&mmcc MDSS_MDP_CLK>,
571					 <&mmcc MDSS_AHB_CLK>,
572					 <&mmcc MDSS_HDMI_CLK>,
573					 <&mmcc MDSS_HDMI_AHB_CLK>,
574					 <&mmcc MDSS_EXTPCLK_CLK>;
575				clock-names =
576					"mdp_core",
577					"iface",
578					"core",
579					"alt_iface",
580					"extp";
581
582				phys = <&hdmi_phy>;
583				phy-names = "hdmi_phy";
584				#sound-dai-cells = <1>;
585
586				ports {
587					#address-cells = <1>;
588					#size-cells = <0>;
589
590					port@0 {
591						reg = <0>;
592						hdmi_in: endpoint {
593							remote-endpoint = <&mdp5_intf3_out>;
594						};
595					};
596				};
597			};
598
599			hdmi_phy: hdmi-phy@9a0600 {
600				#phy-cells = <0>;
601				compatible = "qcom,hdmi-phy-8996";
602				reg = <0x009a0600 0x1c4>,
603				      <0x009a0a00 0x124>,
604				      <0x009a0c00 0x124>,
605				      <0x009a0e00 0x124>,
606				      <0x009a1000 0x124>,
607				      <0x009a1200 0x0c8>;
608				reg-names = "hdmi_pll",
609					    "hdmi_tx_l0",
610					    "hdmi_tx_l1",
611					    "hdmi_tx_l2",
612					    "hdmi_tx_l3",
613					    "hdmi_phy";
614
615				clocks = <&mmcc MDSS_AHB_CLK>,
616					 <&gcc GCC_HDMI_CLKREF_CLK>;
617				clock-names = "iface",
618					      "ref";
619			};
620		};
621		gpu@b00000 {
622			compatible = "qcom,adreno-530.2", "qcom,adreno";
623			#stream-id-cells = <16>;
624
625			reg = <0x00b00000 0x3f000>;
626			reg-names = "kgsl_3d0_reg_memory";
627
628			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
629
630			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
631				<&mmcc GPU_AHB_CLK>,
632				<&mmcc GPU_GX_RBBMTIMER_CLK>,
633				<&gcc GCC_BIMC_GFX_CLK>,
634				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
635
636			clock-names = "core",
637				"iface",
638				"rbbmtimer",
639				"mem",
640				"mem_iface";
641
642			power-domains = <&mmcc GPU_GX_GDSC>;
643			iommus = <&adreno_smmu 0>;
644
645			nvmem-cells = <&gpu_speed_bin>;
646			nvmem-cell-names = "speed_bin";
647
648			qcom,gpu-quirk-two-pass-use-wfi;
649			qcom,gpu-quirk-fault-detect-mask;
650
651			operating-points-v2 = <&gpu_opp_table>;
652
653			gpu_opp_table: opp-table {
654				compatible  ="operating-points-v2";
655
656				/*
657				 * 624Mhz and 560Mhz are only available on speed
658				 * bin (1 << 0). All the rest are available on
659				 * all bins of the hardware
660				 */
661				opp-624000000 {
662					opp-hz = /bits/ 64 <624000000>;
663					opp-supported-hw = <0x01>;
664				};
665				opp-560000000 {
666					opp-hz = /bits/ 64 <560000000>;
667					opp-supported-hw = <0x01>;
668				};
669				opp-510000000 {
670					opp-hz = /bits/ 64 <510000000>;
671					opp-supported-hw = <0xFF>;
672				};
673				opp-401800000 {
674					opp-hz = /bits/ 64 <401800000>;
675					opp-supported-hw = <0xFF>;
676				};
677				opp-315000000 {
678					opp-hz = /bits/ 64 <315000000>;
679					opp-supported-hw = <0xFF>;
680				};
681				opp-214000000 {
682					opp-hz = /bits/ 64 <214000000>;
683					opp-supported-hw = <0xFF>;
684				};
685				opp-133000000 {
686					opp-hz = /bits/ 64 <133000000>;
687					opp-supported-hw = <0xFF>;
688				};
689			};
690
691			zap-shader {
692				memory-region = <&zap_shader_region>;
693			};
694		};
695
696		msmgpio: pinctrl@1010000 {
697			compatible = "qcom,msm8996-pinctrl";
698			reg = <0x01010000 0x300000>;
699			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
700			gpio-controller;
701			gpio-ranges = <&msmgpio 0 0 150>;
702			#gpio-cells = <2>;
703			interrupt-controller;
704			#interrupt-cells = <2>;
705		};
706
707		spmi_bus: qcom,spmi@400f000 {
708			compatible = "qcom,spmi-pmic-arb";
709			reg = <0x0400f000 0x1000>,
710			      <0x04400000 0x800000>,
711			      <0x04c00000 0x800000>,
712			      <0x05800000 0x200000>,
713			      <0x0400a000 0x002100>;
714			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
715			interrupt-names = "periph_irq";
716			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
717			qcom,ee = <0>;
718			qcom,channel = <0>;
719			#address-cells = <2>;
720			#size-cells = <0>;
721			interrupt-controller;
722			#interrupt-cells = <4>;
723		};
724
725		agnoc@0 {
726			power-domains = <&gcc AGGRE0_NOC_GDSC>;
727			compatible = "simple-pm-bus";
728			#address-cells = <1>;
729			#size-cells = <1>;
730			ranges;
731
732			pcie0: pcie@600000 {
733				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
734				status = "disabled";
735				power-domains = <&gcc PCIE0_GDSC>;
736				bus-range = <0x00 0xff>;
737				num-lanes = <1>;
738
739				reg = <0x00600000 0x2000>,
740				      <0x0c000000 0xf1d>,
741				      <0x0c000f20 0xa8>,
742				      <0x0c100000 0x100000>;
743				reg-names = "parf", "dbi", "elbi","config";
744
745				phys = <&pciephy_0>;
746				phy-names = "pciephy";
747
748				#address-cells = <3>;
749				#size-cells = <2>;
750				ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
751					<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
752
753				interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
754				interrupt-names = "msi";
755				#interrupt-cells = <1>;
756				interrupt-map-mask = <0 0 0 0x7>;
757				interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
758						<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
759						<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
760						<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
761
762				pinctrl-names = "default", "sleep";
763				pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
764				pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
765
766				linux,pci-domain = <0>;
767
768				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
769					<&gcc GCC_PCIE_0_AUX_CLK>,
770					<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
771					<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
772					<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
773
774				clock-names =  "pipe",
775						"aux",
776						"cfg",
777						"bus_master",
778						"bus_slave";
779
780			};
781
782			pcie1: pcie@608000 {
783				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
784				power-domains = <&gcc PCIE1_GDSC>;
785				bus-range = <0x00 0xff>;
786				num-lanes = <1>;
787
788				status  = "disabled";
789
790				reg = <0x00608000 0x2000>,
791				      <0x0d000000 0xf1d>,
792				      <0x0d000f20 0xa8>,
793				      <0x0d100000 0x100000>;
794
795				reg-names = "parf", "dbi", "elbi","config";
796
797				phys = <&pciephy_1>;
798				phy-names = "pciephy";
799
800				#address-cells = <3>;
801				#size-cells = <2>;
802				ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
803					<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
804
805				interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
806				interrupt-names = "msi";
807				#interrupt-cells = <1>;
808				interrupt-map-mask = <0 0 0 0x7>;
809				interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
810						<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
811						<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
812						<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
813
814				pinctrl-names = "default", "sleep";
815				pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
816				pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
817
818				linux,pci-domain = <1>;
819
820				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
821					<&gcc GCC_PCIE_1_AUX_CLK>,
822					<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
823					<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
824					<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
825
826				clock-names =  "pipe",
827						"aux",
828						"cfg",
829						"bus_master",
830						"bus_slave";
831			};
832
833			pcie2: pcie@610000 {
834				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
835				power-domains = <&gcc PCIE2_GDSC>;
836				bus-range = <0x00 0xff>;
837				num-lanes = <1>;
838				status = "disabled";
839				reg = <0x00610000 0x2000>,
840				      <0x0e000000 0xf1d>,
841				      <0x0e000f20 0xa8>,
842				      <0x0e100000 0x100000>;
843
844				reg-names = "parf", "dbi", "elbi","config";
845
846				phys = <&pciephy_2>;
847				phy-names = "pciephy";
848
849				#address-cells = <3>;
850				#size-cells = <2>;
851				ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
852					<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
853
854				device_type = "pci";
855
856				interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
857				interrupt-names = "msi";
858				#interrupt-cells = <1>;
859				interrupt-map-mask = <0 0 0 0x7>;
860				interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
861						<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
862						<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
863						<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
864
865				pinctrl-names = "default", "sleep";
866				pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
867				pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
868
869				linux,pci-domain = <2>;
870				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
871					<&gcc GCC_PCIE_2_AUX_CLK>,
872					<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
873					<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
874					<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
875
876				clock-names =  "pipe",
877						"aux",
878						"cfg",
879						"bus_master",
880						"bus_slave";
881			};
882		};
883
884		ufshc: ufshc@624000 {
885			compatible = "qcom,ufshc";
886			reg = <0x00624000 0x2500>;
887			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
888
889			phys = <&ufsphy_lane>;
890			phy-names = "ufsphy";
891
892			power-domains = <&gcc UFS_GDSC>;
893
894			clock-names =
895				"core_clk_src",
896				"core_clk",
897				"bus_clk",
898				"bus_aggr_clk",
899				"iface_clk",
900				"core_clk_unipro_src",
901				"core_clk_unipro",
902				"core_clk_ice",
903				"ref_clk",
904				"tx_lane0_sync_clk",
905				"rx_lane0_sync_clk";
906			clocks =
907				<&gcc UFS_AXI_CLK_SRC>,
908				<&gcc GCC_UFS_AXI_CLK>,
909				<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
910				<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
911				<&gcc GCC_UFS_AHB_CLK>,
912				<&gcc UFS_ICE_CORE_CLK_SRC>,
913				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
914				<&gcc GCC_UFS_ICE_CORE_CLK>,
915				<&rpmcc RPM_SMD_LN_BB_CLK>,
916				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
917				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
918			freq-table-hz =
919				<100000000 200000000>,
920				<0 0>,
921				<0 0>,
922				<0 0>,
923				<0 0>,
924				<150000000 300000000>,
925				<0 0>,
926				<0 0>,
927				<0 0>,
928				<0 0>,
929				<0 0>;
930
931			lanes-per-direction = <1>;
932			#reset-cells = <1>;
933			status = "disabled";
934
935			ufs_variant {
936				compatible = "qcom,ufs_variant";
937			};
938		};
939
940		ufsphy: phy@627000 {
941			compatible = "qcom,msm8996-qmp-ufs-phy";
942			reg = <0x00627000 0x1c4>;
943			#address-cells = <1>;
944			#size-cells = <1>;
945			ranges;
946
947			clocks = <&gcc GCC_UFS_CLKREF_CLK>;
948			clock-names = "ref";
949
950			resets = <&ufshc 0>;
951			reset-names = "ufsphy";
952			status = "disabled";
953
954			ufsphy_lane: lanes@627400 {
955				reg = <0x627400 0x12c>,
956				      <0x627600 0x200>,
957				      <0x627c00 0x1b4>;
958				#phy-cells = <0>;
959			};
960		};
961
962		camss: camss@a00000 {
963			compatible = "qcom,msm8996-camss";
964			reg = <0x00a34000 0x1000>,
965			      <0x00a00030 0x4>,
966			      <0x00a35000 0x1000>,
967			      <0x00a00038 0x4>,
968			      <0x00a36000 0x1000>,
969			      <0x00a00040 0x4>,
970			      <0x00a30000 0x100>,
971			      <0x00a30400 0x100>,
972			      <0x00a30800 0x100>,
973			      <0x00a30c00 0x100>,
974			      <0x00a31000 0x500>,
975			      <0x00a00020 0x10>,
976			      <0x00a10000 0x1000>,
977			      <0x00a14000 0x1000>;
978			reg-names = "csiphy0",
979				"csiphy0_clk_mux",
980				"csiphy1",
981				"csiphy1_clk_mux",
982				"csiphy2",
983				"csiphy2_clk_mux",
984				"csid0",
985				"csid1",
986				"csid2",
987				"csid3",
988				"ispif",
989				"csi_clk_mux",
990				"vfe0",
991				"vfe1";
992			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
993				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
994				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
995				<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
996				<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
997				<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
998				<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
999				<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1000				<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1001				<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1002			interrupt-names = "csiphy0",
1003				"csiphy1",
1004				"csiphy2",
1005				"csid0",
1006				"csid1",
1007				"csid2",
1008				"csid3",
1009				"ispif",
1010				"vfe0",
1011				"vfe1";
1012			power-domains = <&mmcc VFE0_GDSC>,
1013					<&mmcc VFE1_GDSC>;
1014			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1015				<&mmcc CAMSS_ISPIF_AHB_CLK>,
1016				<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1017				<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1018				<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1019				<&mmcc CAMSS_CSI0_AHB_CLK>,
1020				<&mmcc CAMSS_CSI0_CLK>,
1021				<&mmcc CAMSS_CSI0PHY_CLK>,
1022				<&mmcc CAMSS_CSI0PIX_CLK>,
1023				<&mmcc CAMSS_CSI0RDI_CLK>,
1024				<&mmcc CAMSS_CSI1_AHB_CLK>,
1025				<&mmcc CAMSS_CSI1_CLK>,
1026				<&mmcc CAMSS_CSI1PHY_CLK>,
1027				<&mmcc CAMSS_CSI1PIX_CLK>,
1028				<&mmcc CAMSS_CSI1RDI_CLK>,
1029				<&mmcc CAMSS_CSI2_AHB_CLK>,
1030				<&mmcc CAMSS_CSI2_CLK>,
1031				<&mmcc CAMSS_CSI2PHY_CLK>,
1032				<&mmcc CAMSS_CSI2PIX_CLK>,
1033				<&mmcc CAMSS_CSI2RDI_CLK>,
1034				<&mmcc CAMSS_CSI3_AHB_CLK>,
1035				<&mmcc CAMSS_CSI3_CLK>,
1036				<&mmcc CAMSS_CSI3PHY_CLK>,
1037				<&mmcc CAMSS_CSI3PIX_CLK>,
1038				<&mmcc CAMSS_CSI3RDI_CLK>,
1039				<&mmcc CAMSS_AHB_CLK>,
1040				<&mmcc CAMSS_VFE0_CLK>,
1041				<&mmcc CAMSS_CSI_VFE0_CLK>,
1042				<&mmcc CAMSS_VFE0_AHB_CLK>,
1043				<&mmcc CAMSS_VFE0_STREAM_CLK>,
1044				<&mmcc CAMSS_VFE1_CLK>,
1045				<&mmcc CAMSS_CSI_VFE1_CLK>,
1046				<&mmcc CAMSS_VFE1_AHB_CLK>,
1047				<&mmcc CAMSS_VFE1_STREAM_CLK>,
1048				<&mmcc CAMSS_VFE_AHB_CLK>,
1049				<&mmcc CAMSS_VFE_AXI_CLK>;
1050			clock-names = "top_ahb",
1051				"ispif_ahb",
1052				"csiphy0_timer",
1053				"csiphy1_timer",
1054				"csiphy2_timer",
1055				"csi0_ahb",
1056				"csi0",
1057				"csi0_phy",
1058				"csi0_pix",
1059				"csi0_rdi",
1060				"csi1_ahb",
1061				"csi1",
1062				"csi1_phy",
1063				"csi1_pix",
1064				"csi1_rdi",
1065				"csi2_ahb",
1066				"csi2",
1067				"csi2_phy",
1068				"csi2_pix",
1069				"csi2_rdi",
1070				"csi3_ahb",
1071				"csi3",
1072				"csi3_phy",
1073				"csi3_pix",
1074				"csi3_rdi",
1075				"ahb",
1076				"vfe0",
1077				"csi_vfe0",
1078				"vfe0_ahb",
1079				"vfe0_stream",
1080				"vfe1",
1081				"csi_vfe1",
1082				"vfe1_ahb",
1083				"vfe1_stream",
1084				"vfe_ahb",
1085				"vfe_axi";
1086			iommus = <&vfe_smmu 0>,
1087				 <&vfe_smmu 1>,
1088				 <&vfe_smmu 2>,
1089				 <&vfe_smmu 3>;
1090			status = "disabled";
1091			ports {
1092				#address-cells = <1>;
1093				#size-cells = <0>;
1094			};
1095		};
1096
1097		cci: cci@a0c000 {
1098			compatible = "qcom,msm8996-cci";
1099			#address-cells = <1>;
1100			#size-cells = <0>;
1101			reg = <0xa0c000 0x1000>;
1102			interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1103			power-domains = <&mmcc CAMSS_GDSC>;
1104			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1105				 <&mmcc CAMSS_CCI_AHB_CLK>,
1106				 <&mmcc CAMSS_CCI_CLK>,
1107				 <&mmcc CAMSS_AHB_CLK>;
1108			clock-names = "camss_top_ahb",
1109				      "cci_ahb",
1110				      "cci",
1111				      "camss_ahb";
1112			assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1113					  <&mmcc CAMSS_CCI_CLK>;
1114			assigned-clock-rates = <80000000>, <37500000>;
1115			pinctrl-names = "default";
1116			pinctrl-0 = <&cci0_default &cci1_default>;
1117			status = "disabled";
1118
1119			cci_i2c0: i2c-bus@0 {
1120				reg = <0>;
1121				clock-frequency = <400000>;
1122				#address-cells = <1>;
1123				#size-cells = <0>;
1124			};
1125
1126			cci_i2c1: i2c-bus@1 {
1127				reg = <1>;
1128				clock-frequency = <400000>;
1129				#address-cells = <1>;
1130				#size-cells = <0>;
1131			};
1132		};
1133
1134		adreno_smmu: iommu@b40000 {
1135			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1136			reg = <0x00b40000 0x10000>;
1137
1138			#global-interrupts = <1>;
1139			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1140				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1141				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1142			#iommu-cells = <1>;
1143
1144			clocks = <&mmcc GPU_AHB_CLK>,
1145				 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1146			clock-names = "iface", "bus";
1147
1148			power-domains = <&mmcc GPU_GDSC>;
1149		};
1150
1151		video-codec@c00000 {
1152			compatible = "qcom,msm8996-venus";
1153			reg = <0x00c00000 0xff000>;
1154			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1155			power-domains = <&mmcc VENUS_GDSC>;
1156			clocks = <&mmcc VIDEO_CORE_CLK>,
1157				 <&mmcc VIDEO_AHB_CLK>,
1158				 <&mmcc VIDEO_AXI_CLK>,
1159				 <&mmcc VIDEO_MAXI_CLK>;
1160			clock-names = "core", "iface", "bus", "mbus";
1161			iommus = <&venus_smmu 0x00>,
1162				 <&venus_smmu 0x01>,
1163				 <&venus_smmu 0x0a>,
1164				 <&venus_smmu 0x07>,
1165				 <&venus_smmu 0x0e>,
1166				 <&venus_smmu 0x0f>,
1167				 <&venus_smmu 0x08>,
1168				 <&venus_smmu 0x09>,
1169				 <&venus_smmu 0x0b>,
1170				 <&venus_smmu 0x0c>,
1171				 <&venus_smmu 0x0d>,
1172				 <&venus_smmu 0x10>,
1173				 <&venus_smmu 0x11>,
1174				 <&venus_smmu 0x21>,
1175				 <&venus_smmu 0x28>,
1176				 <&venus_smmu 0x29>,
1177				 <&venus_smmu 0x2b>,
1178				 <&venus_smmu 0x2c>,
1179				 <&venus_smmu 0x2d>,
1180				 <&venus_smmu 0x31>;
1181			memory-region = <&venus_region>;
1182			status = "okay";
1183
1184			video-decoder {
1185				compatible = "venus-decoder";
1186				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
1187				clock-names = "core";
1188				power-domains = <&mmcc VENUS_CORE0_GDSC>;
1189			};
1190
1191			video-encoder {
1192				compatible = "venus-encoder";
1193				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
1194				clock-names = "core";
1195				power-domains = <&mmcc VENUS_CORE1_GDSC>;
1196			};
1197		};
1198
1199		mdp_smmu: iommu@d00000 {
1200			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1201			reg = <0x00d00000 0x10000>;
1202
1203			#global-interrupts = <1>;
1204			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1205				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1206				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1207			#iommu-cells = <1>;
1208			clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1209				 <&mmcc SMMU_MDP_AXI_CLK>;
1210			clock-names = "iface", "bus";
1211
1212			power-domains = <&mmcc MDSS_GDSC>;
1213		};
1214
1215		venus_smmu: iommu@d40000 {
1216			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1217			reg = <0x00d40000 0x20000>;
1218			#global-interrupts = <1>;
1219			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
1220				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1221				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1222				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1223				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1224				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1225				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1226				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
1227			power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
1228			clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
1229				 <&mmcc SMMU_VIDEO_AXI_CLK>;
1230			clock-names = "iface", "bus";
1231			#iommu-cells = <1>;
1232			status = "okay";
1233		};
1234
1235		vfe_smmu: iommu@da0000 {
1236			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1237			reg = <0x00da0000 0x10000>;
1238
1239			#global-interrupts = <1>;
1240			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1241				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1242				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1243			power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1244			clocks = <&mmcc SMMU_VFE_AHB_CLK>,
1245				 <&mmcc SMMU_VFE_AXI_CLK>;
1246			clock-names = "iface",
1247				      "bus";
1248			#iommu-cells = <1>;
1249		};
1250
1251		lpass_q6_smmu: iommu@1600000 {
1252			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1253			reg = <0x01600000 0x20000>;
1254			#iommu-cells = <1>;
1255			power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
1256
1257			#global-interrupts = <1>;
1258			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1259		                <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1260		                <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1261		                <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1262		                <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1263		                <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1264		                <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1265		                <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1266		                <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1267		                <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1268		                <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1269		                <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1270		                <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
1271
1272			clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
1273				 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1274			clock-names = "iface", "bus";
1275		};
1276
1277		stm@3002000 {
1278			compatible = "arm,coresight-stm", "arm,primecell";
1279			reg = <0x3002000 0x1000>,
1280			      <0x8280000 0x180000>;
1281			reg-names = "stm-base", "stm-stimulus-base";
1282
1283			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1284			clock-names = "apb_pclk", "atclk";
1285
1286			out-ports {
1287				port {
1288					stm_out: endpoint {
1289						remote-endpoint =
1290						  <&funnel0_in>;
1291					};
1292				};
1293			};
1294		};
1295
1296		tpiu@3020000 {
1297			compatible = "arm,coresight-tpiu", "arm,primecell";
1298			reg = <0x3020000 0x1000>;
1299
1300			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1301			clock-names = "apb_pclk", "atclk";
1302
1303			in-ports {
1304				port {
1305					tpiu_in: endpoint {
1306						remote-endpoint =
1307						  <&replicator_out1>;
1308					};
1309				};
1310			};
1311		};
1312
1313		funnel@3021000 {
1314			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1315			reg = <0x3021000 0x1000>;
1316
1317			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1318			clock-names = "apb_pclk", "atclk";
1319
1320			in-ports {
1321				#address-cells = <1>;
1322				#size-cells = <0>;
1323
1324				port@7 {
1325					reg = <7>;
1326					funnel0_in: endpoint {
1327						remote-endpoint =
1328						  <&stm_out>;
1329					};
1330				};
1331			};
1332
1333			out-ports {
1334				port {
1335					funnel0_out: endpoint {
1336						remote-endpoint =
1337						  <&merge_funnel_in0>;
1338					};
1339				};
1340			};
1341		};
1342
1343		funnel@3022000 {
1344			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1345			reg = <0x3022000 0x1000>;
1346
1347			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1348			clock-names = "apb_pclk", "atclk";
1349
1350			in-ports {
1351				#address-cells = <1>;
1352				#size-cells = <0>;
1353
1354				port@6 {
1355					reg = <6>;
1356					funnel1_in: endpoint {
1357						remote-endpoint =
1358						  <&apss_merge_funnel_out>;
1359					};
1360				};
1361			};
1362
1363			out-ports {
1364				port {
1365					funnel1_out: endpoint {
1366						remote-endpoint =
1367						  <&merge_funnel_in1>;
1368					};
1369				};
1370			};
1371		};
1372
1373		funnel@3023000 {
1374			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1375			reg = <0x3023000 0x1000>;
1376
1377			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1378			clock-names = "apb_pclk", "atclk";
1379
1380
1381			out-ports {
1382				port {
1383					funnel2_out: endpoint {
1384						remote-endpoint =
1385						  <&merge_funnel_in2>;
1386					};
1387				};
1388			};
1389		};
1390
1391		funnel@3025000 {
1392			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1393			reg = <0x3025000 0x1000>;
1394
1395			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1396			clock-names = "apb_pclk", "atclk";
1397
1398			in-ports {
1399				#address-cells = <1>;
1400				#size-cells = <0>;
1401
1402				port@0 {
1403					reg = <0>;
1404					merge_funnel_in0: endpoint {
1405						remote-endpoint =
1406						  <&funnel0_out>;
1407					};
1408				};
1409
1410				port@1 {
1411					reg = <1>;
1412					merge_funnel_in1: endpoint {
1413						remote-endpoint =
1414						  <&funnel1_out>;
1415					};
1416				};
1417
1418				port@2 {
1419					reg = <2>;
1420					merge_funnel_in2: endpoint {
1421						remote-endpoint =
1422						  <&funnel2_out>;
1423					};
1424				};
1425			};
1426
1427			out-ports {
1428				port {
1429					merge_funnel_out: endpoint {
1430						remote-endpoint =
1431						  <&etf_in>;
1432					};
1433				};
1434			};
1435		};
1436
1437		replicator@3026000 {
1438			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1439			reg = <0x3026000 0x1000>;
1440
1441			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1442			clock-names = "apb_pclk", "atclk";
1443
1444			in-ports {
1445				port {
1446					replicator_in: endpoint {
1447						remote-endpoint =
1448						  <&etf_out>;
1449					};
1450				};
1451			};
1452
1453			out-ports {
1454				#address-cells = <1>;
1455				#size-cells = <0>;
1456
1457				port@0 {
1458					reg = <0>;
1459					replicator_out0: endpoint {
1460						remote-endpoint =
1461						  <&etr_in>;
1462					};
1463				};
1464
1465				port@1 {
1466					reg = <1>;
1467					replicator_out1: endpoint {
1468						remote-endpoint =
1469						  <&tpiu_in>;
1470					};
1471				};
1472			};
1473		};
1474
1475		etf@3027000 {
1476			compatible = "arm,coresight-tmc", "arm,primecell";
1477			reg = <0x3027000 0x1000>;
1478
1479			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1480			clock-names = "apb_pclk", "atclk";
1481
1482			in-ports {
1483				port {
1484					etf_in: endpoint {
1485						remote-endpoint =
1486						  <&merge_funnel_out>;
1487					};
1488				};
1489			};
1490
1491			out-ports {
1492				port {
1493					etf_out: endpoint {
1494						remote-endpoint =
1495						  <&replicator_in>;
1496					};
1497				};
1498			};
1499		};
1500
1501		etr@3028000 {
1502			compatible = "arm,coresight-tmc", "arm,primecell";
1503			reg = <0x3028000 0x1000>;
1504
1505			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1506			clock-names = "apb_pclk", "atclk";
1507			arm,scatter-gather;
1508
1509			in-ports {
1510				port {
1511					etr_in: endpoint {
1512						remote-endpoint =
1513						  <&replicator_out0>;
1514					};
1515				};
1516			};
1517		};
1518
1519		debug@3810000 {
1520			compatible = "arm,coresight-cpu-debug", "arm,primecell";
1521			reg = <0x3810000 0x1000>;
1522
1523			clocks = <&rpmcc RPM_QDSS_CLK>;
1524			clock-names = "apb_pclk";
1525
1526			cpu = <&CPU0>;
1527		};
1528
1529		etm@3840000 {
1530			compatible = "arm,coresight-etm4x", "arm,primecell";
1531			reg = <0x3840000 0x1000>;
1532
1533			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1534			clock-names = "apb_pclk", "atclk";
1535
1536			cpu = <&CPU0>;
1537
1538			out-ports {
1539				port {
1540					etm0_out: endpoint {
1541						remote-endpoint =
1542						  <&apss_funnel0_in0>;
1543					};
1544				};
1545			};
1546		};
1547
1548		debug@3910000 {
1549			compatible = "arm,coresight-cpu-debug", "arm,primecell";
1550			reg = <0x3910000 0x1000>;
1551
1552			clocks = <&rpmcc RPM_QDSS_CLK>;
1553			clock-names = "apb_pclk";
1554
1555			cpu = <&CPU1>;
1556		};
1557
1558		etm@3940000 {
1559			compatible = "arm,coresight-etm4x", "arm,primecell";
1560			reg = <0x3940000 0x1000>;
1561
1562			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1563			clock-names = "apb_pclk", "atclk";
1564
1565			cpu = <&CPU1>;
1566
1567			out-ports {
1568				port {
1569					etm1_out: endpoint {
1570						remote-endpoint =
1571						  <&apss_funnel0_in1>;
1572					};
1573				};
1574			};
1575		};
1576
1577		funnel@39b0000 { /* APSS Funnel 0 */
1578			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1579			reg = <0x39b0000 0x1000>;
1580
1581			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1582			clock-names = "apb_pclk", "atclk";
1583
1584			in-ports {
1585				#address-cells = <1>;
1586				#size-cells = <0>;
1587
1588				port@0 {
1589					reg = <0>;
1590					apss_funnel0_in0: endpoint {
1591						remote-endpoint = <&etm0_out>;
1592					};
1593				};
1594
1595				port@1 {
1596					reg = <1>;
1597					apss_funnel0_in1: endpoint {
1598						remote-endpoint = <&etm1_out>;
1599					};
1600				};
1601			};
1602
1603			out-ports {
1604				port {
1605					apss_funnel0_out: endpoint {
1606						remote-endpoint =
1607						  <&apss_merge_funnel_in0>;
1608					};
1609				};
1610			};
1611		};
1612
1613		debug@3a10000 {
1614			compatible = "arm,coresight-cpu-debug", "arm,primecell";
1615			reg = <0x3a10000 0x1000>;
1616
1617			clocks = <&rpmcc RPM_QDSS_CLK>;
1618			clock-names = "apb_pclk";
1619
1620			cpu = <&CPU2>;
1621		};
1622
1623		etm@3a40000 {
1624			compatible = "arm,coresight-etm4x", "arm,primecell";
1625			reg = <0x3a40000 0x1000>;
1626
1627			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1628			clock-names = "apb_pclk", "atclk";
1629
1630			cpu = <&CPU2>;
1631
1632			out-ports {
1633				port {
1634					etm2_out: endpoint {
1635						remote-endpoint =
1636						  <&apss_funnel1_in0>;
1637					};
1638				};
1639			};
1640		};
1641
1642		debug@3b10000 {
1643			compatible = "arm,coresight-cpu-debug", "arm,primecell";
1644			reg = <0x3b10000 0x1000>;
1645
1646			clocks = <&rpmcc RPM_QDSS_CLK>;
1647			clock-names = "apb_pclk";
1648
1649			cpu = <&CPU3>;
1650		};
1651
1652		etm@3b40000 {
1653			compatible = "arm,coresight-etm4x", "arm,primecell";
1654			reg = <0x3b40000 0x1000>;
1655
1656			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1657			clock-names = "apb_pclk", "atclk";
1658
1659			cpu = <&CPU3>;
1660
1661			out-ports {
1662				port {
1663					etm3_out: endpoint {
1664						remote-endpoint =
1665						  <&apss_funnel1_in1>;
1666					};
1667				};
1668			};
1669		};
1670
1671		funnel@3bb0000 { /* APSS Funnel 1 */
1672			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1673			reg = <0x3bb0000 0x1000>;
1674
1675			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1676			clock-names = "apb_pclk", "atclk";
1677
1678			in-ports {
1679				#address-cells = <1>;
1680				#size-cells = <0>;
1681
1682				port@0 {
1683					reg = <0>;
1684					apss_funnel1_in0: endpoint {
1685						remote-endpoint = <&etm2_out>;
1686					};
1687				};
1688
1689				port@1 {
1690					reg = <1>;
1691					apss_funnel1_in1: endpoint {
1692						remote-endpoint = <&etm3_out>;
1693					};
1694				};
1695			};
1696
1697			out-ports {
1698				port {
1699					apss_funnel1_out: endpoint {
1700						remote-endpoint =
1701						  <&apss_merge_funnel_in1>;
1702					};
1703				};
1704			};
1705		};
1706
1707		funnel@3bc0000 {
1708			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1709			reg = <0x3bc0000 0x1000>;
1710
1711			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1712			clock-names = "apb_pclk", "atclk";
1713
1714			in-ports {
1715				#address-cells = <1>;
1716				#size-cells = <0>;
1717
1718				port@0 {
1719					reg = <0>;
1720					apss_merge_funnel_in0: endpoint {
1721						remote-endpoint =
1722						  <&apss_funnel0_out>;
1723					};
1724				};
1725
1726				port@1 {
1727					reg = <1>;
1728					apss_merge_funnel_in1: endpoint {
1729						remote-endpoint =
1730						  <&apss_funnel1_out>;
1731					};
1732				};
1733			};
1734
1735			out-ports {
1736				port {
1737					apss_merge_funnel_out: endpoint {
1738						remote-endpoint =
1739						  <&funnel1_in>;
1740					};
1741				};
1742			};
1743		};
1744		kryocc: clock-controller@6400000 {
1745			compatible = "qcom,apcc-msm8996";
1746			reg = <0x06400000 0x90000>;
1747			#clock-cells = <1>;
1748		};
1749
1750		usb3: usb@6af8800 {
1751			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1752			reg = <0x06af8800 0x400>;
1753			#address-cells = <1>;
1754			#size-cells = <1>;
1755			ranges;
1756
1757			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
1758				<&gcc GCC_USB30_MASTER_CLK>,
1759				<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1760				<&gcc GCC_USB30_MOCK_UTMI_CLK>,
1761				<&gcc GCC_USB30_SLEEP_CLK>,
1762				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1763
1764			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1765					  <&gcc GCC_USB30_MASTER_CLK>;
1766			assigned-clock-rates = <19200000>, <120000000>;
1767
1768			power-domains = <&gcc USB30_GDSC>;
1769			status = "disabled";
1770
1771			dwc3@6a00000 {
1772				compatible = "snps,dwc3";
1773				reg = <0x06a00000 0xcc00>;
1774				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
1775				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
1776				phy-names = "usb2-phy", "usb3-phy";
1777				snps,dis_u2_susphy_quirk;
1778				snps,dis_enblslpm_quirk;
1779			};
1780		};
1781
1782		usb3phy: phy@7410000 {
1783			compatible = "qcom,msm8996-qmp-usb3-phy";
1784			reg = <0x07410000 0x1c4>;
1785			#clock-cells = <1>;
1786			#address-cells = <1>;
1787			#size-cells = <1>;
1788			ranges;
1789
1790			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1791				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1792				<&gcc GCC_USB3_CLKREF_CLK>;
1793			clock-names = "aux", "cfg_ahb", "ref";
1794
1795			resets = <&gcc GCC_USB3_PHY_BCR>,
1796				<&gcc GCC_USB3PHY_PHY_BCR>;
1797			reset-names = "phy", "common";
1798			status = "disabled";
1799
1800			ssusb_phy_0: lane@7410200 {
1801				reg = <0x07410200 0x200>,
1802				      <0x07410400 0x130>,
1803				      <0x07410600 0x1a8>;
1804				#phy-cells = <0>;
1805
1806				clock-output-names = "usb3_phy_pipe_clk_src";
1807				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1808				clock-names = "pipe0";
1809			};
1810		};
1811
1812		hsusb_phy1: phy@7411000 {
1813			compatible = "qcom,msm8996-qusb2-phy";
1814			reg = <0x07411000 0x180>;
1815			#phy-cells = <0>;
1816
1817			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1818				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
1819			clock-names = "cfg_ahb", "ref";
1820
1821			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1822			nvmem-cells = <&qusb2p_hstx_trim>;
1823			status = "disabled";
1824		};
1825
1826		hsusb_phy2: phy@7412000 {
1827			compatible = "qcom,msm8996-qusb2-phy";
1828			reg = <0x07412000 0x180>;
1829			#phy-cells = <0>;
1830
1831			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1832				<&gcc GCC_RX2_USB2_CLKREF_CLK>;
1833			clock-names = "cfg_ahb", "ref";
1834
1835			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1836			nvmem-cells = <&qusb2s_hstx_trim>;
1837			status = "disabled";
1838		};
1839
1840		sdhc2: sdhci@74a4900 {
1841			 status = "disabled";
1842			 compatible = "qcom,sdhci-msm-v4";
1843			 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
1844			 reg-names = "hc_mem", "core_mem";
1845
1846			 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
1847				      <0 221 IRQ_TYPE_LEVEL_HIGH>;
1848			 interrupt-names = "hc_irq", "pwr_irq";
1849
1850			 clock-names = "iface", "core", "xo";
1851			 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1852			 <&gcc GCC_SDCC2_APPS_CLK>,
1853			 <&xo_board>;
1854			 bus-width = <4>;
1855		 };
1856
1857		blsp1_uart1: serial@7570000 {
1858			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1859			reg = <0x07570000 0x1000>;
1860			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1861			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1862				 <&gcc GCC_BLSP1_AHB_CLK>;
1863			clock-names = "core", "iface";
1864			status = "disabled";
1865		};
1866
1867		blsp1_spi0: spi@7575000 {
1868			compatible = "qcom,spi-qup-v2.2.1";
1869			reg = <0x07575000 0x600>;
1870			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1871			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1872				 <&gcc GCC_BLSP1_AHB_CLK>;
1873			clock-names = "core", "iface";
1874			pinctrl-names = "default", "sleep";
1875			pinctrl-0 = <&blsp1_spi0_default>;
1876			pinctrl-1 = <&blsp1_spi0_sleep>;
1877			#address-cells = <1>;
1878			#size-cells = <0>;
1879			status = "disabled";
1880		};
1881
1882		blsp1_i2c2: i2c@7577000 {
1883			compatible = "qcom,i2c-qup-v2.2.1";
1884			reg = <0x07577000 0x1000>;
1885			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1886			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1887				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1888			clock-names = "iface", "core";
1889			pinctrl-names = "default", "sleep";
1890			pinctrl-0 = <&blsp1_i2c2_default>;
1891			pinctrl-1 = <&blsp1_i2c2_sleep>;
1892			#address-cells = <1>;
1893			#size-cells = <0>;
1894			status = "disabled";
1895		};
1896
1897		blsp2_uart1: serial@75b0000 {
1898			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1899			reg = <0x075b0000 0x1000>;
1900			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1901			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
1902				 <&gcc GCC_BLSP2_AHB_CLK>;
1903			clock-names = "core", "iface";
1904			status = "disabled";
1905		};
1906
1907		blsp2_uart2: serial@75b1000 {
1908			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1909			reg = <0x075b1000 0x1000>;
1910			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1911			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
1912				 <&gcc GCC_BLSP2_AHB_CLK>;
1913			clock-names = "core", "iface";
1914			status = "disabled";
1915		};
1916
1917		blsp2_i2c0: i2c@75b5000 {
1918			compatible = "qcom,i2c-qup-v2.2.1";
1919			reg = <0x075b5000 0x1000>;
1920			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1921			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1922				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
1923			clock-names = "iface", "core";
1924			pinctrl-names = "default", "sleep";
1925			pinctrl-0 = <&blsp2_i2c0_default>;
1926			pinctrl-1 = <&blsp2_i2c0_sleep>;
1927			#address-cells = <1>;
1928			#size-cells = <0>;
1929			status = "disabled";
1930		};
1931
1932		blsp2_i2c1: i2c@75b6000 {
1933			compatible = "qcom,i2c-qup-v2.2.1";
1934			reg = <0x075b6000 0x1000>;
1935			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1936			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1937				<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
1938			clock-names = "iface", "core";
1939			pinctrl-names = "default", "sleep";
1940			pinctrl-0 = <&blsp2_i2c1_default>;
1941			pinctrl-1 = <&blsp2_i2c1_sleep>;
1942			#address-cells = <1>;
1943			#size-cells = <0>;
1944			status = "disabled";
1945		};
1946
1947		blsp2_spi5: spi@75ba000{
1948			compatible = "qcom,spi-qup-v2.2.1";
1949			reg = <0x075ba000 0x600>;
1950			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1951			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
1952				 <&gcc GCC_BLSP2_AHB_CLK>;
1953			clock-names = "core", "iface";
1954			pinctrl-names = "default", "sleep";
1955			pinctrl-0 = <&blsp2_spi5_default>;
1956			pinctrl-1 = <&blsp2_spi5_sleep>;
1957			#address-cells = <1>;
1958			#size-cells = <0>;
1959			status = "disabled";
1960		};
1961
1962		usb2: usb@76f8800 {
1963			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1964			reg = <0x076f8800 0x400>;
1965			#address-cells = <1>;
1966			#size-cells = <1>;
1967			ranges;
1968
1969			clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
1970				<&gcc GCC_USB20_MASTER_CLK>,
1971				<&gcc GCC_USB20_MOCK_UTMI_CLK>,
1972				<&gcc GCC_USB20_SLEEP_CLK>,
1973				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1974
1975			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1976					  <&gcc GCC_USB20_MASTER_CLK>;
1977			assigned-clock-rates = <19200000>, <60000000>;
1978
1979			power-domains = <&gcc USB30_GDSC>;
1980			status = "disabled";
1981
1982			dwc3@7600000 {
1983				compatible = "snps,dwc3";
1984				reg = <0x07600000 0xcc00>;
1985				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
1986				phys = <&hsusb_phy2>;
1987				phy-names = "usb2-phy";
1988				snps,dis_u2_susphy_quirk;
1989				snps,dis_enblslpm_quirk;
1990			};
1991		};
1992
1993		slimbam: dma@9184000 {
1994			compatible = "qcom,bam-v1.7.0";
1995			qcom,controlled-remotely;
1996			reg = <0x09184000 0x32000>;
1997			num-channels  = <31>;
1998			interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
1999			#dma-cells = <1>;
2000			qcom,ee = <1>;
2001			qcom,num-ees = <2>;
2002		};
2003
2004		slim_msm: slim@91c0000 {
2005			compatible = "qcom,slim-ngd-v1.5.0";
2006			reg = <0x091c0000 0x2C000>;
2007			reg-names = "ctrl";
2008			interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2009			dmas =	<&slimbam 3>, <&slimbam 4>,
2010				<&slimbam 5>, <&slimbam 6>;
2011			dma-names = "rx", "tx", "tx2", "rx2";
2012			#address-cells = <1>;
2013			#size-cells = <0>;
2014			ngd@1 {
2015				reg = <1>;
2016				#address-cells = <1>;
2017				#size-cells = <1>;
2018
2019				tasha_ifd: tas-ifd {
2020					compatible = "slim217,1a0";
2021					reg  = <0 0>;
2022				};
2023
2024				wcd9335: codec@1{
2025					pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2026					pinctrl-names = "default";
2027
2028					compatible = "slim217,1a0";
2029					reg  = <1 0>;
2030
2031					interrupt-parent = <&msmgpio>;
2032					interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2033						     <53 IRQ_TYPE_LEVEL_HIGH>;
2034					interrupt-names  = "intr1", "intr2";
2035					interrupt-controller;
2036					#interrupt-cells = <1>;
2037					reset-gpios = <&msmgpio 64 0>;
2038
2039					slim-ifc-dev  = <&tasha_ifd>;
2040
2041					#sound-dai-cells = <1>;
2042				};
2043			};
2044		};
2045
2046		adsp_pil: remoteproc@9300000 {
2047			compatible = "qcom,msm8996-adsp-pil";
2048			reg = <0x09300000 0x80000>;
2049
2050			interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2051					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2052					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2053					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2054					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2055			interrupt-names = "wdog", "fatal", "ready",
2056					  "handover", "stop-ack";
2057
2058			clocks = <&xo_board>;
2059			clock-names = "xo";
2060
2061			memory-region = <&adsp_region>;
2062
2063			qcom,smem-states = <&smp2p_adsp_out 0>;
2064			qcom,smem-state-names = "stop";
2065
2066			smd-edge {
2067				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2068
2069				label = "lpass";
2070				mboxes = <&apcs_glb 8>;
2071				qcom,smd-edge = <1>;
2072				qcom,remote-pid = <2>;
2073				#address-cells = <1>;
2074				#size-cells = <0>;
2075				apr {
2076					power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2077					compatible = "qcom,apr-v2";
2078					qcom,smd-channels = "apr_audio_svc";
2079					qcom,apr-domain = <APR_DOMAIN_ADSP>;
2080					#address-cells = <1>;
2081					#size-cells = <0>;
2082
2083					q6core {
2084						reg = <APR_SVC_ADSP_CORE>;
2085						compatible = "qcom,q6core";
2086					};
2087
2088					q6afe: q6afe {
2089						compatible = "qcom,q6afe";
2090						reg = <APR_SVC_AFE>;
2091						q6afedai: dais {
2092							compatible = "qcom,q6afe-dais";
2093							#address-cells = <1>;
2094							#size-cells = <0>;
2095							#sound-dai-cells = <1>;
2096							hdmi@1 {
2097								reg = <1>;
2098							};
2099						};
2100					};
2101
2102					q6asm: q6asm {
2103						compatible = "qcom,q6asm";
2104						reg = <APR_SVC_ASM>;
2105						q6asmdai: dais {
2106							compatible = "qcom,q6asm-dais";
2107							#address-cells = <1>;
2108							#size-cells = <0>;
2109							#sound-dai-cells = <1>;
2110							iommus = <&lpass_q6_smmu 1>;
2111						};
2112					};
2113
2114					q6adm: q6adm {
2115						compatible = "qcom,q6adm";
2116						reg = <APR_SVC_ADM>;
2117						q6routing: routing {
2118							compatible = "qcom,q6adm-routing";
2119							#sound-dai-cells = <0>;
2120						};
2121					};
2122				};
2123
2124			};
2125		};
2126
2127		apcs_glb: mailbox@9820000 {
2128			compatible = "qcom,msm8996-apcs-hmss-global";
2129			reg = <0x09820000 0x1000>;
2130
2131			#mbox-cells = <1>;
2132		};
2133
2134		timer@9840000 {
2135			#address-cells = <1>;
2136			#size-cells = <1>;
2137			ranges;
2138			compatible = "arm,armv7-timer-mem";
2139			reg = <0x09840000 0x1000>;
2140			clock-frequency = <19200000>;
2141
2142			frame@9850000 {
2143				frame-number = <0>;
2144				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
2145					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2146				reg = <0x09850000 0x1000>,
2147				      <0x09860000 0x1000>;
2148			};
2149
2150			frame@9870000 {
2151				frame-number = <1>;
2152				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
2153				reg = <0x09870000 0x1000>;
2154				status = "disabled";
2155			};
2156
2157			frame@9880000 {
2158				frame-number = <2>;
2159				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2160				reg = <0x09880000 0x1000>;
2161				status = "disabled";
2162			};
2163
2164			frame@9890000 {
2165				frame-number = <3>;
2166				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
2167				reg = <0x09890000 0x1000>;
2168				status = "disabled";
2169			};
2170
2171			frame@98a0000 {
2172				frame-number = <4>;
2173				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
2174				reg = <0x098a0000 0x1000>;
2175				status = "disabled";
2176			};
2177
2178			frame@98b0000 {
2179				frame-number = <5>;
2180				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
2181				reg = <0x098b0000 0x1000>;
2182				status = "disabled";
2183			};
2184
2185			frame@98c0000 {
2186				frame-number = <6>;
2187				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
2188				reg = <0x098c0000 0x1000>;
2189				status = "disabled";
2190			};
2191		};
2192
2193		saw3: syscon@9a10000 {
2194			compatible = "syscon";
2195			reg = <0x09a10000 0x1000>;
2196		};
2197
2198		intc: interrupt-controller@9bc0000 {
2199			compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
2200			#interrupt-cells = <3>;
2201			interrupt-controller;
2202			#redistributor-regions = <1>;
2203			redistributor-stride = <0x0 0x40000>;
2204			reg = <0x09bc0000 0x10000>,
2205			      <0x09c00000 0x100000>;
2206			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2207		};
2208	};
2209
2210	sound: sound {
2211	};
2212
2213	thermal-zones {
2214		cpu0-thermal {
2215			polling-delay-passive = <250>;
2216			polling-delay = <1000>;
2217
2218			thermal-sensors = <&tsens0 3>;
2219
2220			trips {
2221				cpu0_alert0: trip-point0 {
2222					temperature = <75000>;
2223					hysteresis = <2000>;
2224					type = "passive";
2225				};
2226
2227				cpu0_crit: cpu_crit {
2228					temperature = <110000>;
2229					hysteresis = <2000>;
2230					type = "critical";
2231				};
2232			};
2233		};
2234
2235		cpu1-thermal {
2236			polling-delay-passive = <250>;
2237			polling-delay = <1000>;
2238
2239			thermal-sensors = <&tsens0 5>;
2240
2241			trips {
2242				cpu1_alert0: trip-point0 {
2243					temperature = <75000>;
2244					hysteresis = <2000>;
2245					type = "passive";
2246				};
2247
2248				cpu1_crit: cpu_crit {
2249					temperature = <110000>;
2250					hysteresis = <2000>;
2251					type = "critical";
2252				};
2253			};
2254		};
2255
2256		cpu2-thermal {
2257			polling-delay-passive = <250>;
2258			polling-delay = <1000>;
2259
2260			thermal-sensors = <&tsens0 8>;
2261
2262			trips {
2263				cpu2_alert0: trip-point0 {
2264					temperature = <75000>;
2265					hysteresis = <2000>;
2266					type = "passive";
2267				};
2268
2269				cpu2_crit: cpu_crit {
2270					temperature = <110000>;
2271					hysteresis = <2000>;
2272					type = "critical";
2273				};
2274			};
2275		};
2276
2277		cpu3-thermal {
2278			polling-delay-passive = <250>;
2279			polling-delay = <1000>;
2280
2281			thermal-sensors = <&tsens0 10>;
2282
2283			trips {
2284				cpu3_alert0: trip-point0 {
2285					temperature = <75000>;
2286					hysteresis = <2000>;
2287					type = "passive";
2288				};
2289
2290				cpu3_crit: cpu_crit {
2291					temperature = <110000>;
2292					hysteresis = <2000>;
2293					type = "critical";
2294				};
2295			};
2296		};
2297
2298		gpu-thermal-top {
2299			polling-delay-passive = <250>;
2300			polling-delay = <1000>;
2301
2302			thermal-sensors = <&tsens1 6>;
2303
2304			trips {
2305				gpu1_alert0: trip-point0 {
2306					temperature = <90000>;
2307					hysteresis = <2000>;
2308					type = "hot";
2309				};
2310			};
2311		};
2312
2313		gpu-thermal-bottom {
2314			polling-delay-passive = <250>;
2315			polling-delay = <1000>;
2316
2317			thermal-sensors = <&tsens1 7>;
2318
2319			trips {
2320				gpu2_alert0: trip-point0 {
2321					temperature = <90000>;
2322					hysteresis = <2000>;
2323					type = "hot";
2324				};
2325			};
2326		};
2327
2328		m4m-thermal {
2329			polling-delay-passive = <250>;
2330			polling-delay = <1000>;
2331
2332			thermal-sensors = <&tsens0 1>;
2333
2334			trips {
2335				m4m_alert0: trip-point0 {
2336					temperature = <90000>;
2337					hysteresis = <2000>;
2338					type = "hot";
2339				};
2340			};
2341		};
2342
2343		l3-or-venus-thermal {
2344			polling-delay-passive = <250>;
2345			polling-delay = <1000>;
2346
2347			thermal-sensors = <&tsens0 2>;
2348
2349			trips {
2350				l3_or_venus_alert0: trip-point0 {
2351					temperature = <90000>;
2352					hysteresis = <2000>;
2353					type = "hot";
2354				};
2355			};
2356		};
2357
2358		cluster0-l2-thermal {
2359			polling-delay-passive = <250>;
2360			polling-delay = <1000>;
2361
2362			thermal-sensors = <&tsens0 7>;
2363
2364			trips {
2365				cluster0_l2_alert0: trip-point0 {
2366					temperature = <90000>;
2367					hysteresis = <2000>;
2368					type = "hot";
2369				};
2370			};
2371		};
2372
2373		cluster1-l2-thermal {
2374			polling-delay-passive = <250>;
2375			polling-delay = <1000>;
2376
2377			thermal-sensors = <&tsens0 12>;
2378
2379			trips {
2380				cluster1_l2_alert0: trip-point0 {
2381					temperature = <90000>;
2382					hysteresis = <2000>;
2383					type = "hot";
2384				};
2385			};
2386		};
2387
2388		camera-thermal {
2389			polling-delay-passive = <250>;
2390			polling-delay = <1000>;
2391
2392			thermal-sensors = <&tsens1 1>;
2393
2394			trips {
2395				camera_alert0: trip-point0 {
2396					temperature = <90000>;
2397					hysteresis = <2000>;
2398					type = "hot";
2399				};
2400			};
2401		};
2402
2403		q6-dsp-thermal {
2404			polling-delay-passive = <250>;
2405			polling-delay = <1000>;
2406
2407			thermal-sensors = <&tsens1 2>;
2408
2409			trips {
2410				q6_dsp_alert0: trip-point0 {
2411					temperature = <90000>;
2412					hysteresis = <2000>;
2413					type = "hot";
2414				};
2415			};
2416		};
2417
2418		mem-thermal {
2419			polling-delay-passive = <250>;
2420			polling-delay = <1000>;
2421
2422			thermal-sensors = <&tsens1 3>;
2423
2424			trips {
2425				mem_alert0: trip-point0 {
2426					temperature = <90000>;
2427					hysteresis = <2000>;
2428					type = "hot";
2429				};
2430			};
2431		};
2432
2433		modemtx-thermal {
2434			polling-delay-passive = <250>;
2435			polling-delay = <1000>;
2436
2437			thermal-sensors = <&tsens1 4>;
2438
2439			trips {
2440				modemtx_alert0: trip-point0 {
2441					temperature = <90000>;
2442					hysteresis = <2000>;
2443					type = "hot";
2444				};
2445			};
2446		};
2447	};
2448
2449	timer {
2450		compatible = "arm,armv8-timer";
2451		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2452			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2453			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2454			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
2455	};
2456};
2457#include "msm8996-pins.dtsi"
2458