Lines Matching +full:0 +full:x32000
1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
22 <0x00024000 0x00024000 0x001000>, /* ap 4 */
23 <0x00025000 0x00025000 0x001000>, /* ap 5 */
24 <0x00026000 0x00026000 0x001000>, /* ap 6 */
25 <0x00027000 0x00027000 0x001000>, /* ap 7 */
26 <0x00028000 0x00028000 0x001000>, /* ap 8 */
27 <0x00029000 0x00029000 0x001000>, /* ap 9 */
28 <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
29 <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
30 <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
31 <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
32 <0x00030000 0x00030000 0x001000>, /* ap 14 */
33 <0x00031000 0x00031000 0x001000>, /* ap 15 */
34 <0x00032000 0x00032000 0x001000>, /* ap 16 */
35 <0x00033000 0x00033000 0x001000>, /* ap 17 */
36 <0x00038000 0x00038000 0x001000>, /* ap 18 */
37 <0x00039000 0x00039000 0x001000>, /* ap 19 */
38 <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
39 <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
40 <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
41 <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
42 <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
43 <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
44 <0x00080000 0x00080000 0x010000>, /* ap 26 */
45 <0x00080000 0x00080000 0x001000>, /* ap 27 */
46 <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
47 <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
48 <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
49 <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
50 <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
51 <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
54 <0x49000000 0x49000000 0x000400>, /* ap 0 */
55 <0x49000400 0x49000400 0x000400>, /* ap 1 */
56 <0x49022000 0x49022000 0x001000>, /* ap 2 */
57 <0x49023000 0x49023000 0x001000>, /* ap 3 */
58 <0x49024000 0x49024000 0x001000>, /* ap 4 */
59 <0x49025000 0x49025000 0x001000>, /* ap 5 */
60 <0x49026000 0x49026000 0x001000>, /* ap 6 */
61 <0x49027000 0x49027000 0x001000>, /* ap 7 */
62 <0x49028000 0x49028000 0x001000>, /* ap 8 */
63 <0x49029000 0x49029000 0x001000>, /* ap 9 */
64 <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
65 <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
66 <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
67 <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
68 <0x49030000 0x49030000 0x001000>, /* ap 14 */
69 <0x49031000 0x49031000 0x001000>, /* ap 15 */
70 <0x49032000 0x49032000 0x001000>, /* ap 16 */
71 <0x49033000 0x49033000 0x001000>, /* ap 17 */
72 <0x49038000 0x49038000 0x001000>, /* ap 18 */
73 <0x49039000 0x49039000 0x001000>, /* ap 19 */
74 <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
75 <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
76 <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
77 <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
78 <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
79 <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
80 <0x49080000 0x49080000 0x010000>, /* ap 26 */
81 <0x49080000 0x49080000 0x001000>, /* ap 27 */
82 <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
83 <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
84 <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
85 <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
86 <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
87 <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
89 target-module@22000 { /* 0x40122000, ap 2 02.0 */
91 reg = <0x2208c 0x4>;
100 clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
104 ranges = <0x0 0x22000 0x1000>,
105 <0x49022000 0x49022000 0x1000>;
107 mcbsp1: mcbsp@0 {
109 reg = <0x0 0xff>, /* MPU private access */
110 <0x49022000 0xff>; /* L3 Interconnect */
122 target-module@24000 { /* 0x40124000, ap 4 04.0 */
124 reg = <0x2408c 0x4>;
133 clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
137 ranges = <0x0 0x24000 0x1000>,
138 <0x49024000 0x49024000 0x1000>;
140 mcbsp2: mcbsp@0 {
142 reg = <0x0 0xff>, /* MPU private access */
143 <0x49024000 0xff>; /* L3 Interconnect */
155 target-module@26000 { /* 0x40126000, ap 6 06.0 */
157 reg = <0x2608c 0x4>;
166 clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
170 ranges = <0x0 0x26000 0x1000>,
171 <0x49026000 0x49026000 0x1000>;
173 mcbsp3: mcbsp@0 {
175 reg = <0x0 0xff>, /* MPU private access */
176 <0x49026000 0xff>; /* L3 Interconnect */
188 target-module@28000 { /* 0x40128000, ap 8 08.0 */
190 reg = <0x28000 0x4>,
191 <0x28004 0x4>;
198 clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
202 ranges = <0x0 0x28000 0x1000>,
203 <0x49028000 0x49028000 0x1000>;
213 target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
218 ranges = <0x0 0x2a000 0x1000>,
219 <0x4902a000 0x4902a000 0x1000>;
222 target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
224 reg = <0x2e000 0x4>,
225 <0x2e010 0x4>;
234 clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
238 ranges = <0x0 0x2e000 0x1000>,
239 <0x4902e000 0x4902e000 0x1000>;
241 dmic: dmic@0 {
243 reg = <0x0 0x7f>, /* MPU private access */
244 <0x4902e000 0x7f>; /* L3 Interconnect */
253 target-module@30000 { /* 0x40130000, ap 14 0e.0 */
255 reg = <0x30000 0x4>,
256 <0x30010 0x4>,
257 <0x30014 0x4>;
267 clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
271 ranges = <0x0 0x30000 0x1000>,
272 <0x49030000 0x49030000 0x1000>;
274 wdt3: wdt@0 {
276 reg = <0x0 0x80>;
281 mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
283 reg = <0x32000 0x4>,
284 <0x32010 0x4>;
293 clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
297 ranges = <0x0 0x32000 0x1000>,
298 <0x49032000 0x49032000 0x1000>;
303 mcpdm: mcpdm@0 {
305 reg = <0x0 0x7f>, /* MPU private access */
306 <0x49032000 0x7f>; /* L3 Interconnect */
315 target-module@38000 { /* 0x40138000, ap 18 12.0 */
317 reg = <0x38000 0x4>,
318 <0x38010 0x4>;
327 clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
331 ranges = <0x0 0x38000 0x1000>,
332 <0x49038000 0x49038000 0x1000>;
334 timer5: timer@0 {
336 reg = <0x00000000 0x80>,
337 <0x49038000 0x80>;
346 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
348 reg = <0x3a000 0x4>,
349 <0x3a010 0x4>;
358 clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
362 ranges = <0x0 0x3a000 0x1000>,
363 <0x4903a000 0x4903a000 0x1000>;
365 timer6: timer@0 {
367 reg = <0x00000000 0x80>,
368 <0x4903a000 0x80>;
377 target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
379 reg = <0x3c000 0x4>,
380 <0x3c010 0x4>;
389 clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
393 ranges = <0x0 0x3c000 0x1000>,
394 <0x4903c000 0x4903c000 0x1000>;
396 timer7: timer@0 {
398 reg = <0x00000000 0x80>,
399 <0x4903c000 0x80>;
408 target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
410 reg = <0x3e000 0x4>,
411 <0x3e010 0x4>;
420 clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
424 ranges = <0x0 0x3e000 0x1000>,
425 <0x4903e000 0x4903e000 0x1000>;
427 timer8: timer@0 {
429 reg = <0x00000000 0x80>,
430 <0x4903e000 0x80>;
440 target-module@80000 { /* 0x40180000, ap 26 1a.0 */
445 ranges = <0x0 0x80000 0x10000>,
446 <0x49080000 0x49080000 0x10000>;
449 target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
454 ranges = <0x0 0xa0000 0x10000>,
455 <0x490a0000 0x490a0000 0x10000>;
458 target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
463 ranges = <0x0 0xc0000 0x10000>,
464 <0x490c0000 0x490c0000 0x10000>;
467 target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
469 reg = <0xf1000 0x4>,
470 <0xf1010 0x4>;
480 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
484 ranges = <0x0 0xf1000 0x1000>,
485 <0x490f1000 0x490f1000 0x1000>;