Lines Matching +full:0 +full:x32000
22 #clock-cells = <0>;
29 #clock-cells = <0>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
42 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
66 reg = <0x0 0x100>;
80 reg = <0x0 0x101>;
112 CPU_SLEEP_0: cpu-sleep-0 {
115 arm,psci-suspend-param = <0x00000004>;
126 qcom,dload-mode = <&tcsr 0x13000>;
132 syscon = <&tcsr_mutex_regs 0 0x1000>;
139 reg = <0 0 0 0>;
153 reg = <0x0 0x91500000 0x0 0x200000>;
158 reg = <0x0 0x90b00000 0x0 0xa00000>;
163 reg = <0x0 0x90400000 0x0 0x700000>;
168 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
173 reg = <0x0 0x88800000 0x0 0x6200000>;
178 reg = <0x0 0x86000000 0x0 0x200000>;
183 reg = <0x0 0x85800000 0x0 0x800000>;
188 reg = <0x0 0x86200000 0x0 0x2600000>;
195 size = <0x0 0x200000>;
196 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
205 reg = <0x0 0x90b00000 0x0 0xa00000>;
217 mboxes = <&apcs_glb 0>;
274 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
278 qcom,local-pid = <0>;
302 qcom,local-pid = <0>;
326 qcom,local-pid = <0>;
344 ranges = <0 0 0 0xffffffff>;
349 reg = <0x00034000 0x488>;
367 reg = <0x00035000 0x130>,
368 <0x00035200 0x200>,
369 <0x00035400 0x1dc>;
370 #phy-cells = <0>;
380 reg = <0x00036000 0x130>,
381 <0x00036200 0x200>,
382 <0x00036400 0x1dc>;
383 #phy-cells = <0>;
393 reg = <0x00037000 0x130>,
394 <0x00037200 0x200>,
395 <0x00037400 0x1dc>;
396 #phy-cells = <0>;
408 reg = <0x00068000 0x6000>;
413 reg = <0x00074000 0x8ff>;
418 reg = <0x24e 0x2>;
423 reg = <0x24f 0x1>;
428 reg = <0x133 0x1>;
435 reg = <0x00083000 0x1000>;
445 reg = <0x00300000 0x90000>;
453 reg = <0x004a9000 0x1000>, /* TM */
454 <0x004a8000 0x1000>; /* SROT */
464 reg = <0x004ad000 0x1000>, /* TM */
465 <0x004ac000 0x1000>; /* SROT */
475 reg = <0x00740000 0x20000>;
480 reg = <0x007a0000 0x18000>;
488 reg = <0x008c0000 0x40000>;
504 reg = <0x00900000 0x1000>,
505 <0x009b0000 0x1040>,
506 <0x009b8000 0x1040>;
526 reg = <0x00901000 0x90000>;
530 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
543 iommus = <&mdp_smmu 0>;
547 #size-cells = <0>;
549 port@0 {
550 reg = <0>;
560 reg = <0x009a0000 0x50c>,
561 <0x00070000 0x6158>,
562 <0x009e0000 0xfff>;
588 #size-cells = <0>;
590 port@0 {
591 reg = <0>;
600 #phy-cells = <0>;
602 reg = <0x009a0600 0x1c4>,
603 <0x009a0a00 0x124>,
604 <0x009a0c00 0x124>,
605 <0x009a0e00 0x124>,
606 <0x009a1000 0x124>,
607 <0x009a1200 0x0c8>;
625 reg = <0x00b00000 0x3f000>;
628 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
643 iommus = <&adreno_smmu 0>;
658 * bin (1 << 0). All the rest are available on
663 opp-supported-hw = <0x01>;
667 opp-supported-hw = <0x01>;
671 opp-supported-hw = <0xFF>;
675 opp-supported-hw = <0xFF>;
679 opp-supported-hw = <0xFF>;
683 opp-supported-hw = <0xFF>;
687 opp-supported-hw = <0xFF>;
698 reg = <0x01010000 0x300000>;
701 gpio-ranges = <&msmgpio 0 0 150>;
709 reg = <0x0400f000 0x1000>,
710 <0x04400000 0x800000>,
711 <0x04c00000 0x800000>,
712 <0x05800000 0x200000>,
713 <0x0400a000 0x002100>;
717 qcom,ee = <0>;
718 qcom,channel = <0>;
720 #size-cells = <0>;
725 agnoc@0 {
736 bus-range = <0x00 0xff>;
739 reg = <0x00600000 0x2000>,
740 <0x0c000000 0xf1d>,
741 <0x0c000f20 0xa8>,
742 <0x0c100000 0x100000>;
750 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
751 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
756 interrupt-map-mask = <0 0 0 0x7>;
757 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
758 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
759 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
760 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
763 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
766 linux,pci-domain = <0>;
785 bus-range = <0x00 0xff>;
790 reg = <0x00608000 0x2000>,
791 <0x0d000000 0xf1d>,
792 <0x0d000f20 0xa8>,
793 <0x0d100000 0x100000>;
802 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
803 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
808 interrupt-map-mask = <0 0 0 0x7>;
809 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
810 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
811 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
812 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
815 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
836 bus-range = <0x00 0xff>;
839 reg = <0x00610000 0x2000>,
840 <0x0e000000 0xf1d>,
841 <0x0e000f20 0xa8>,
842 <0x0e100000 0x100000>;
851 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
852 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
859 interrupt-map-mask = <0 0 0 0x7>;
860 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
861 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
862 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
863 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
866 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
886 reg = <0x00624000 0x2500>;
920 <0 0>,
921 <0 0>,
922 <0 0>,
923 <0 0>,
925 <0 0>,
926 <0 0>,
927 <0 0>,
928 <0 0>,
929 <0 0>;
942 reg = <0x00627000 0x1c4>;
950 resets = <&ufshc 0>;
955 reg = <0x627400 0x12c>,
956 <0x627600 0x200>,
957 <0x627c00 0x1b4>;
958 #phy-cells = <0>;
964 reg = <0x00a34000 0x1000>,
965 <0x00a00030 0x4>,
966 <0x00a35000 0x1000>,
967 <0x00a00038 0x4>,
968 <0x00a36000 0x1000>,
969 <0x00a00040 0x4>,
970 <0x00a30000 0x100>,
971 <0x00a30400 0x100>,
972 <0x00a30800 0x100>,
973 <0x00a30c00 0x100>,
974 <0x00a31000 0x500>,
975 <0x00a00020 0x10>,
976 <0x00a10000 0x1000>,
977 <0x00a14000 0x1000>;
1086 iommus = <&vfe_smmu 0>,
1093 #size-cells = <0>;
1100 #size-cells = <0>;
1101 reg = <0xa0c000 0x1000>;
1116 pinctrl-0 = <&cci0_default &cci1_default>;
1119 cci_i2c0: i2c-bus@0 {
1120 reg = <0>;
1123 #size-cells = <0>;
1130 #size-cells = <0>;
1136 reg = <0x00b40000 0x10000>;
1153 reg = <0x00c00000 0xff000>;
1161 iommus = <&venus_smmu 0x00>,
1162 <&venus_smmu 0x01>,
1163 <&venus_smmu 0x0a>,
1164 <&venus_smmu 0x07>,
1165 <&venus_smmu 0x0e>,
1166 <&venus_smmu 0x0f>,
1167 <&venus_smmu 0x08>,
1168 <&venus_smmu 0x09>,
1169 <&venus_smmu 0x0b>,
1170 <&venus_smmu 0x0c>,
1171 <&venus_smmu 0x0d>,
1172 <&venus_smmu 0x10>,
1173 <&venus_smmu 0x11>,
1174 <&venus_smmu 0x21>,
1175 <&venus_smmu 0x28>,
1176 <&venus_smmu 0x29>,
1177 <&venus_smmu 0x2b>,
1178 <&venus_smmu 0x2c>,
1179 <&venus_smmu 0x2d>,
1180 <&venus_smmu 0x31>;
1201 reg = <0x00d00000 0x10000>;
1217 reg = <0x00d40000 0x20000>;
1237 reg = <0x00da0000 0x10000>;
1253 reg = <0x01600000 0x20000>;
1279 reg = <0x3002000 0x1000>,
1280 <0x8280000 0x180000>;
1298 reg = <0x3020000 0x1000>;
1315 reg = <0x3021000 0x1000>;
1322 #size-cells = <0>;
1345 reg = <0x3022000 0x1000>;
1352 #size-cells = <0>;
1375 reg = <0x3023000 0x1000>;
1393 reg = <0x3025000 0x1000>;
1400 #size-cells = <0>;
1402 port@0 {
1403 reg = <0>;
1439 reg = <0x3026000 0x1000>;
1455 #size-cells = <0>;
1457 port@0 {
1458 reg = <0>;
1477 reg = <0x3027000 0x1000>;
1503 reg = <0x3028000 0x1000>;
1521 reg = <0x3810000 0x1000>;
1531 reg = <0x3840000 0x1000>;
1550 reg = <0x3910000 0x1000>;
1560 reg = <0x3940000 0x1000>;
1577 funnel@39b0000 { /* APSS Funnel 0 */
1579 reg = <0x39b0000 0x1000>;
1586 #size-cells = <0>;
1588 port@0 {
1589 reg = <0>;
1615 reg = <0x3a10000 0x1000>;
1625 reg = <0x3a40000 0x1000>;
1644 reg = <0x3b10000 0x1000>;
1654 reg = <0x3b40000 0x1000>;
1673 reg = <0x3bb0000 0x1000>;
1680 #size-cells = <0>;
1682 port@0 {
1683 reg = <0>;
1709 reg = <0x3bc0000 0x1000>;
1716 #size-cells = <0>;
1718 port@0 {
1719 reg = <0>;
1746 reg = <0x06400000 0x90000>;
1752 reg = <0x06af8800 0x400>;
1773 reg = <0x06a00000 0xcc00>;
1774 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
1784 reg = <0x07410000 0x1c4>;
1801 reg = <0x07410200 0x200>,
1802 <0x07410400 0x130>,
1803 <0x07410600 0x1a8>;
1804 #phy-cells = <0>;
1814 reg = <0x07411000 0x180>;
1815 #phy-cells = <0>;
1828 reg = <0x07412000 0x180>;
1829 #phy-cells = <0>;
1843 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
1846 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
1847 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1859 reg = <0x07570000 0x1000>;
1869 reg = <0x07575000 0x600>;
1875 pinctrl-0 = <&blsp1_spi0_default>;
1878 #size-cells = <0>;
1884 reg = <0x07577000 0x1000>;
1890 pinctrl-0 = <&blsp1_i2c2_default>;
1893 #size-cells = <0>;
1899 reg = <0x075b0000 0x1000>;
1909 reg = <0x075b1000 0x1000>;
1919 reg = <0x075b5000 0x1000>;
1925 pinctrl-0 = <&blsp2_i2c0_default>;
1928 #size-cells = <0>;
1934 reg = <0x075b6000 0x1000>;
1940 pinctrl-0 = <&blsp2_i2c1_default>;
1943 #size-cells = <0>;
1949 reg = <0x075ba000 0x600>;
1955 pinctrl-0 = <&blsp2_spi5_default>;
1958 #size-cells = <0>;
1964 reg = <0x076f8800 0x400>;
1984 reg = <0x07600000 0xcc00>;
1985 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
1996 reg = <0x09184000 0x32000>;
1998 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2006 reg = <0x091c0000 0x2C000>;
2008 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2013 #size-cells = <0>;
2021 reg = <0 0>;
2025 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2029 reg = <1 0>;
2037 reset-gpios = <&msmgpio 64 0>;
2048 reg = <0x09300000 0x80000>;
2050 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2051 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2063 qcom,smem-states = <&smp2p_adsp_out 0>;
2074 #size-cells = <0>;
2081 #size-cells = <0>;
2094 #size-cells = <0>;
2108 #size-cells = <0>;
2119 #sound-dai-cells = <0>;
2129 reg = <0x09820000 0x1000>;
2139 reg = <0x09840000 0x1000>;
2143 frame-number = <0>;
2146 reg = <0x09850000 0x1000>,
2147 <0x09860000 0x1000>;
2153 reg = <0x09870000 0x1000>;
2160 reg = <0x09880000 0x1000>;
2167 reg = <0x09890000 0x1000>;
2174 reg = <0x098a0000 0x1000>;
2181 reg = <0x098b0000 0x1000>;
2188 reg = <0x098c0000 0x1000>;
2195 reg = <0x09a10000 0x1000>;
2203 redistributor-stride = <0x0 0x40000>;
2204 reg = <0x09bc0000 0x10000>,
2205 <0x09c00000 0x100000>;