Lines Matching +full:0 +full:x32000
1 &l4_wkup { /* 0x44c00000 */
3 reg = <0x44c00000 0x800>,
4 <0x44c00800 0x800>,
5 <0x44c01000 0x400>,
6 <0x44c01400 0x400>;
10 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
11 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
12 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
14 segment@0 { /* 0x44c00000 */
18 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
19 <0x00000800 0x00000800 0x000800>, /* ap 1 */
20 <0x00001000 0x00001000 0x000400>, /* ap 2 */
21 <0x00001400 0x00001400 0x000400>; /* ap 3 */
24 segment@100000 { /* 0x44d00000 */
28 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
29 <0x00004000 0x00104000 0x001000>, /* ap 5 */
30 <0x00080000 0x00180000 0x002000>, /* ap 6 */
31 <0x00082000 0x00182000 0x001000>; /* ap 7 */
33 target-module@0 { /* 0x44d00000, ap 4 28.0 */
35 reg = <0x0 0x4>;
39 ranges = <0x0 0x0 0x4000>;
43 target-module@80000 { /* 0x44d80000, ap 6 10.0 */
48 ranges = <0x0 0x80000 0x2000>;
52 segment@200000 { /* 0x44e00000 */
56 ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */
57 <0x00002000 0x00202000 0x001000>, /* ap 9 */
58 <0x00003000 0x00203000 0x001000>, /* ap 10 */
59 <0x00004000 0x00204000 0x001000>, /* ap 11 */
60 <0x00005000 0x00205000 0x001000>, /* ap 12 */
61 <0x00006000 0x00206000 0x001000>, /* ap 13 */
62 <0x00007000 0x00207000 0x001000>, /* ap 14 */
63 <0x00008000 0x00208000 0x001000>, /* ap 15 */
64 <0x00009000 0x00209000 0x001000>, /* ap 16 */
65 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */
66 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */
67 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */
68 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */
69 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */
70 <0x00010000 0x00210000 0x010000>, /* ap 22 */
71 <0x00020000 0x00220000 0x010000>, /* ap 23 */
72 <0x00030000 0x00230000 0x001000>, /* ap 24 */
73 <0x00031000 0x00231000 0x001000>, /* ap 25 */
74 <0x00032000 0x00232000 0x001000>, /* ap 26 */
75 <0x00033000 0x00233000 0x001000>, /* ap 27 */
76 <0x00034000 0x00234000 0x001000>, /* ap 28 */
77 <0x00035000 0x00235000 0x001000>, /* ap 29 */
78 <0x00036000 0x00236000 0x001000>, /* ap 30 */
79 <0x00037000 0x00237000 0x001000>, /* ap 31 */
80 <0x00038000 0x00238000 0x001000>, /* ap 32 */
81 <0x00039000 0x00239000 0x001000>, /* ap 33 */
82 <0x0003a000 0x0023a000 0x001000>, /* ap 34 */
83 <0x0003e000 0x0023e000 0x001000>, /* ap 35 */
84 <0x0003f000 0x0023f000 0x001000>, /* ap 36 */
85 <0x0000e000 0x0020e000 0x001000>, /* ap 37 */
86 <0x00040000 0x00240000 0x040000>, /* ap 38 */
87 <0x00080000 0x00280000 0x001000>; /* ap 39 */
89 target-module@0 { /* 0x44e00000, ap 8 58.0 */
91 reg = <0 0x4>;
95 ranges = <0x0 0x0 0x2000>;
97 prcm: prcm@0 {
99 reg = <0 0x2000>;
102 ranges = <0 0 0x2000>;
106 #size-cells = <0>;
114 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
119 ranges = <0x0 0x3000 0x1000>;
122 target-module@5000 { /* 0x44e05000, ap 12 30.0 */
127 ranges = <0x0 0x5000 0x1000>;
130 gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
132 reg = <0x7000 0x4>,
133 <0x7010 0x4>,
134 <0x7114 0x4>;
145 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
150 ranges = <0x0 0x7000 0x1000>;
152 gpio0: gpio@0 {
154 gpio-ranges = <&am33xx_pinmux 0 82 8>,
170 reg = <0x0 0x1000>;
175 target-module@9000 { /* 0x44e09000, ap 16 04.0 */
177 reg = <0x9050 0x4>,
178 <0x9054 0x4>,
179 <0x9058 0x4>;
189 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>;
193 ranges = <0x0 0x9000 0x1000>;
195 uart0: serial@0 {
198 reg = <0x0 0x1000>;
201 dmas = <&edma 26 0>, <&edma 27 0>;
206 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
208 reg = <0xb000 0x8>,
209 <0xb010 0x8>,
210 <0xb090 0x8>;
222 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>;
226 ranges = <0x0 0xb000 0x1000>;
228 i2c0: i2c@0 {
231 #size-cells = <0>;
232 reg = <0x0 0x1000>;
238 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
240 reg = <0xd000 0x4>,
241 <0xd010 0x4>;
248 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>;
252 ranges = <0x00000000 0x0000d000 0x00001000>,
253 <0x00001000 0x0000e000 0x00001000>;
255 tscadc: tscadc@0 {
257 reg = <0x0 0x1000>;
260 dmas = <&edma 53 0>, <&edma 57 0>;
273 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
275 reg = <0x10000 0x4>;
279 ranges = <0x00000000 0x00010000 0x00010000>,
280 <0x00010000 0x00020000 0x00010000>;
282 scm: scm@0 {
284 reg = <0x0 0x2000>;
288 ranges = <0 0 0x2000>;
292 reg = <0x800 0x238>;
295 pinctrl-single,function-mask = <0x7f>;
298 scm_conf: scm_conf@0 {
300 reg = <0x0 0x800>;
303 ranges = <0 0 0x800>;
307 reg = <0x650 0x4>;
313 #size-cells = <0>;
319 reg = <0x620 0x10>,
320 <0x648 0x4>;
326 reg = <0x1324 0x24>;
334 reg = <0xf90 0x40>;
345 timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */
347 reg = <0x31000 0x4>,
348 <0x31010 0x4>,
349 <0x31014 0x4>;
359 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>;
363 ranges = <0x0 0x31000 0x1000>;
365 timer1: timer@0 {
367 reg = <0x0 0x400>;
375 target-module@33000 { /* 0x44e33000, ap 27 18.0 */
380 ranges = <0x0 0x33000 0x1000>;
383 target-module@35000 { /* 0x44e35000, ap 29 50.0 */
385 reg = <0x35000 0x4>,
386 <0x35010 0x4>,
387 <0x35014 0x4>;
397 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
401 ranges = <0x0 0x35000 0x1000>;
403 wdt2: wdt@0 {
405 reg = <0x0 0x1000>;
410 target-module@37000 { /* 0x44e37000, ap 31 08.0 */
415 ranges = <0x0 0x37000 0x1000>;
418 target-module@39000 { /* 0x44e39000, ap 33 02.0 */
423 ranges = <0x0 0x39000 0x1000>;
426 target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */
428 reg = <0x3e074 0x4>,
429 <0x3e078 0x4>;
436 clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;
440 ranges = <0x0 0x3e000 0x1000>;
442 rtc: rtc@0 {
444 reg = <0x0 0x1000>;
450 target-module@40000 { /* 0x44e40000, ap 38 68.0 */
455 ranges = <0x0 0x40000 0x40000>;
460 &l4_fw { /* 0x47c00000 */
462 reg = <0x47c00000 0x800>,
463 <0x47c00800 0x800>,
464 <0x47c01000 0x400>;
468 ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */
470 segment@0 { /* 0x47c00000 */
474 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
475 <0x00000800 0x00000800 0x000800>, /* ap 1 */
476 <0x00001000 0x00001000 0x000400>, /* ap 2 */
477 <0x0000c000 0x0000c000 0x001000>, /* ap 3 */
478 <0x0000d000 0x0000d000 0x001000>, /* ap 4 */
479 <0x0000e000 0x0000e000 0x001000>, /* ap 5 */
480 <0x0000f000 0x0000f000 0x001000>, /* ap 6 */
481 <0x00010000 0x00010000 0x001000>, /* ap 7 */
482 <0x00011000 0x00011000 0x001000>, /* ap 8 */
483 <0x0001a000 0x0001a000 0x001000>, /* ap 9 */
484 <0x0001b000 0x0001b000 0x001000>, /* ap 10 */
485 <0x00024000 0x00024000 0x001000>, /* ap 11 */
486 <0x00025000 0x00025000 0x001000>, /* ap 12 */
487 <0x00026000 0x00026000 0x001000>, /* ap 13 */
488 <0x00027000 0x00027000 0x001000>, /* ap 14 */
489 <0x00030000 0x00030000 0x001000>, /* ap 15 */
490 <0x00031000 0x00031000 0x001000>, /* ap 16 */
491 <0x00038000 0x00038000 0x001000>, /* ap 17 */
492 <0x00039000 0x00039000 0x001000>, /* ap 18 */
493 <0x0003a000 0x0003a000 0x001000>, /* ap 19 */
494 <0x0003b000 0x0003b000 0x001000>, /* ap 20 */
495 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
496 <0x0003f000 0x0003f000 0x001000>, /* ap 22 */
497 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
498 <0x00040000 0x00040000 0x001000>, /* ap 24 */
499 <0x00046000 0x00046000 0x001000>, /* ap 25 */
500 <0x00047000 0x00047000 0x001000>, /* ap 26 */
501 <0x00044000 0x00044000 0x001000>, /* ap 27 */
502 <0x00045000 0x00045000 0x001000>, /* ap 28 */
503 <0x00028000 0x00028000 0x001000>, /* ap 29 */
504 <0x00029000 0x00029000 0x001000>, /* ap 30 */
505 <0x00032000 0x00032000 0x001000>, /* ap 31 */
506 <0x00033000 0x00033000 0x001000>, /* ap 32 */
507 <0x0003d000 0x0003d000 0x001000>, /* ap 33 */
508 <0x00041000 0x00041000 0x001000>, /* ap 34 */
509 <0x00042000 0x00042000 0x001000>, /* ap 35 */
510 <0x00043000 0x00043000 0x001000>, /* ap 36 */
511 <0x00014000 0x00014000 0x001000>, /* ap 37 */
512 <0x00015000 0x00015000 0x001000>; /* ap 38 */
514 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */
519 ranges = <0x0 0xc000 0x1000>;
522 target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */
527 ranges = <0x0 0xe000 0x1000>;
530 target-module@10000 { /* 0x47c10000, ap 7 20.0 */
535 ranges = <0x0 0x10000 0x1000>;
538 target-module@14000 { /* 0x47c14000, ap 37 3c.0 */
543 ranges = <0x0 0x14000 0x1000>;
546 target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */
551 ranges = <0x0 0x1a000 0x1000>;
554 target-module@24000 { /* 0x47c24000, ap 11 28.0 */
559 ranges = <0x0 0x24000 0x1000>;
562 target-module@26000 { /* 0x47c26000, ap 13 30.0 */
567 ranges = <0x0 0x26000 0x1000>;
570 target-module@28000 { /* 0x47c28000, ap 29 40.0 */
575 ranges = <0x0 0x28000 0x1000>;
578 target-module@30000 { /* 0x47c30000, ap 15 14.0 */
583 ranges = <0x0 0x30000 0x1000>;
586 target-module@32000 { /* 0x47c32000, ap 31 06.0 */
591 ranges = <0x0 0x32000 0x1000>;
594 target-module@38000 { /* 0x47c38000, ap 17 18.0 */
599 ranges = <0x0 0x38000 0x1000>;
602 target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */
607 ranges = <0x0 0x3a000 0x1000>;
610 target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */
615 ranges = <0x0 0x3c000 0x1000>;
618 target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */
623 ranges = <0x0 0x3e000 0x1000>;
626 target-module@40000 { /* 0x47c40000, ap 24 02.0 */
631 ranges = <0x0 0x40000 0x1000>;
634 target-module@42000 { /* 0x47c42000, ap 35 34.0 */
639 ranges = <0x0 0x42000 0x1000>;
642 target-module@44000 { /* 0x47c44000, ap 27 24.0 */
647 ranges = <0x0 0x44000 0x1000>;
650 target-module@46000 { /* 0x47c46000, ap 25 2c.0 */
655 ranges = <0x0 0x46000 0x1000>;
660 &l4_fast { /* 0x4a000000 */
662 reg = <0x4a000000 0x800>,
663 <0x4a000800 0x800>,
664 <0x4a001000 0x400>;
668 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
670 segment@0 { /* 0x4a000000 */
674 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
675 <0x00000800 0x00000800 0x000800>, /* ap 1 */
676 <0x00001000 0x00001000 0x000400>, /* ap 2 */
677 <0x00100000 0x00100000 0x008000>, /* ap 3 */
678 <0x00108000 0x00108000 0x001000>, /* ap 4 */
679 <0x00180000 0x00180000 0x020000>, /* ap 5 */
680 <0x001a0000 0x001a0000 0x001000>, /* ap 6 */
681 <0x00200000 0x00200000 0x080000>, /* ap 7 */
682 <0x00280000 0x00280000 0x001000>, /* ap 8 */
683 <0x00300000 0x00300000 0x080000>, /* ap 9 */
684 <0x00380000 0x00380000 0x001000>; /* ap 10 */
686 target-module@100000 { /* 0x4a100000, ap 3 08.0 */
688 reg = <0x101200 0x4>,
689 <0x101208 0x4>,
690 <0x101204 0x4>;
692 ti,sysc-mask = <0>;
698 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
702 ranges = <0x0 0x100000 0x8000>;
704 mac: ethernet@0 {
710 bd_ram_size = <0x2000>;
711 mac_control = <0x20>;
713 active_slave = <0>;
714 cpts_clock_mult = <0x80000000>;
716 reg = <0x0 0x800
717 0x1200 0x100>;
727 ranges = <0 0 0x8000>;
733 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
736 #size-cells = <0>;
738 reg = <0x1000 0x100>;
756 target-module@180000 { /* 0x4a180000, ap 5 10.0 */
761 ranges = <0x0 0x180000 0x20000>;
764 target-module@200000 { /* 0x4a200000, ap 7 02.0 */
769 ranges = <0x0 0x200000 0x80000>;
772 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
774 reg = <0x326000 0x4>,
775 <0x326004 0x4>;
785 clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
791 ranges = <0x0 0x300000 0x80000>;
797 &l4_mpuss { /* 0x4b140000 */
799 reg = <0x4b144400 0x100>,
800 <0x4b144800 0x400>;
804 ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */
806 segment@0 { /* 0x4b140000 */
810 ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */
811 <0x00001000 0x00001000 0x001000>, /* ap 1 */
812 <0x00002000 0x00002000 0x001000>, /* ap 2 */
813 <0x00004000 0x00004000 0x000400>, /* ap 3 */
814 <0x00005000 0x00005000 0x000400>, /* ap 4 */
815 <0x00000000 0x00000000 0x001000>, /* ap 5 */
816 <0x00003000 0x00003000 0x001000>, /* ap 6 */
817 <0x00000800 0x00000800 0x000800>; /* ap 7 */
819 target-module@0 { /* 0x4b140000, ap 5 02.2 */
824 ranges = <0x00000000 0x00000000 0x00001000>,
825 <0x00001000 0x00001000 0x00001000>,
826 <0x00002000 0x00002000 0x00001000>;
829 target-module@3000 { /* 0x4b143000, ap 6 04.0 */
834 ranges = <0x0 0x3000 0x1000>;
839 &l4_per { /* 0x48000000 */
841 reg = <0x48000000 0x800>,
842 <0x48000800 0x800>,
843 <0x48001000 0x400>,
844 <0x48001400 0x400>,
845 <0x48001800 0x400>,
846 <0x48001c00 0x400>;
850 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
851 <0x00100000 0x48100000 0x100000>, /* segment 1 */
852 <0x00200000 0x48200000 0x100000>, /* segment 2 */
853 <0x00300000 0x48300000 0x100000>, /* segment 3 */
854 <0x46000000 0x46000000 0x400000>, /* l3 data port */
855 <0x46400000 0x46400000 0x400000>; /* l3 data port */
857 segment@0 { /* 0x48000000 */
861 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
862 <0x00000800 0x00000800 0x000800>, /* ap 1 */
863 <0x00001000 0x00001000 0x000400>, /* ap 2 */
864 <0x00001400 0x00001400 0x000400>, /* ap 3 */
865 <0x00001800 0x00001800 0x000400>, /* ap 4 */
866 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */
867 <0x00008000 0x00008000 0x001000>, /* ap 6 */
868 <0x00009000 0x00009000 0x001000>, /* ap 7 */
869 <0x00016000 0x00016000 0x001000>, /* ap 8 */
870 <0x00017000 0x00017000 0x001000>, /* ap 9 */
871 <0x00022000 0x00022000 0x001000>, /* ap 10 */
872 <0x00023000 0x00023000 0x001000>, /* ap 11 */
873 <0x00024000 0x00024000 0x001000>, /* ap 12 */
874 <0x00025000 0x00025000 0x001000>, /* ap 13 */
875 <0x0002a000 0x0002a000 0x001000>, /* ap 14 */
876 <0x0002b000 0x0002b000 0x001000>, /* ap 15 */
877 <0x00038000 0x00038000 0x002000>, /* ap 16 */
878 <0x0003a000 0x0003a000 0x001000>, /* ap 17 */
879 <0x00014000 0x00014000 0x001000>, /* ap 18 */
880 <0x00015000 0x00015000 0x001000>, /* ap 19 */
881 <0x0003c000 0x0003c000 0x002000>, /* ap 20 */
882 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
883 <0x00040000 0x00040000 0x001000>, /* ap 22 */
884 <0x00041000 0x00041000 0x001000>, /* ap 23 */
885 <0x00042000 0x00042000 0x001000>, /* ap 24 */
886 <0x00043000 0x00043000 0x001000>, /* ap 25 */
887 <0x00044000 0x00044000 0x001000>, /* ap 26 */
888 <0x00045000 0x00045000 0x001000>, /* ap 27 */
889 <0x00046000 0x00046000 0x001000>, /* ap 28 */
890 <0x00047000 0x00047000 0x001000>, /* ap 29 */
891 <0x00048000 0x00048000 0x001000>, /* ap 30 */
892 <0x00049000 0x00049000 0x001000>, /* ap 31 */
893 <0x0004c000 0x0004c000 0x001000>, /* ap 32 */
894 <0x0004d000 0x0004d000 0x001000>, /* ap 33 */
895 <0x00050000 0x00050000 0x002000>, /* ap 34 */
896 <0x00052000 0x00052000 0x001000>, /* ap 35 */
897 <0x00060000 0x00060000 0x001000>, /* ap 36 */
898 <0x00061000 0x00061000 0x001000>, /* ap 37 */
899 <0x00080000 0x00080000 0x010000>, /* ap 38 */
900 <0x00090000 0x00090000 0x001000>, /* ap 39 */
901 <0x000a0000 0x000a0000 0x010000>, /* ap 40 */
902 <0x000b0000 0x000b0000 0x001000>, /* ap 41 */
903 <0x00030000 0x00030000 0x001000>, /* ap 77 */
904 <0x00031000 0x00031000 0x001000>, /* ap 78 */
905 <0x0004a000 0x0004a000 0x001000>, /* ap 85 */
906 <0x0004b000 0x0004b000 0x001000>, /* ap 86 */
907 <0x000c8000 0x000c8000 0x001000>, /* ap 87 */
908 <0x000c9000 0x000c9000 0x001000>, /* ap 88 */
909 <0x000cc000 0x000cc000 0x001000>, /* ap 89 */
910 <0x000cd000 0x000cd000 0x001000>, /* ap 90 */
911 <0x000ca000 0x000ca000 0x001000>, /* ap 91 */
912 <0x000cb000 0x000cb000 0x001000>, /* ap 92 */
913 <0x46000000 0x46000000 0x400000>, /* l3 data port */
914 <0x46400000 0x46400000 0x400000>; /* l3 data port */
916 target-module@8000 { /* 0x48008000, ap 6 10.0 */
921 ranges = <0x0 0x8000 0x1000>;
924 target-module@14000 { /* 0x48014000, ap 18 58.0 */
929 ranges = <0x0 0x14000 0x1000>;
932 target-module@16000 { /* 0x48016000, ap 8 3c.0 */
937 ranges = <0x0 0x16000 0x1000>;
940 target-module@22000 { /* 0x48022000, ap 10 12.0 */
942 reg = <0x22050 0x4>,
943 <0x22054 0x4>,
944 <0x22058 0x4>;
954 clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;
958 ranges = <0x0 0x22000 0x1000>;
960 uart1: serial@0 {
963 reg = <0x0 0x1000>;
966 dmas = <&edma 28 0>, <&edma 29 0>;
971 target-module@24000 { /* 0x48024000, ap 12 14.0 */
973 reg = <0x24050 0x4>,
974 <0x24054 0x4>,
975 <0x24058 0x4>;
985 clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>;
989 ranges = <0x0 0x24000 0x1000>;
991 uart2: serial@0 {
994 reg = <0x0 0x1000>;
997 dmas = <&edma 30 0>, <&edma 31 0>;
1002 target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */
1004 reg = <0x2a000 0x8>,
1005 <0x2a010 0x8>,
1006 <0x2a090 0x8>;
1018 clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>;
1022 ranges = <0x0 0x2a000 0x1000>;
1024 i2c1: i2c@0 {
1027 #size-cells = <0>;
1028 reg = <0x0 0x1000>;
1034 target-module@30000 { /* 0x48030000, ap 77 08.0 */
1036 reg = <0x30000 0x4>,
1037 <0x30110 0x4>,
1038 <0x30114 0x4>;
1048 clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>;
1052 ranges = <0x0 0x30000 0x1000>;
1054 spi0: spi@0 {
1057 #size-cells = <0>;
1058 reg = <0x0 0x400>;
1061 dmas = <&edma 16 0
1062 &edma 17 0
1063 &edma 18 0
1064 &edma 19 0>;
1070 target-module@38000 { /* 0x48038000, ap 16 02.0 */
1072 reg = <0x38000 0x4>,
1073 <0x38004 0x4>;
1079 clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>;
1083 ranges = <0x0 0x38000 0x2000>,
1084 <0x46000000 0x46000000 0x400000>;
1086 mcasp0: mcasp@0 {
1088 reg = <0x0 0x2000>,
1089 <0x46000000 0x400000>;
1100 target-module@3c000 { /* 0x4803c000, ap 20 32.0 */
1102 reg = <0x3c000 0x4>,
1103 <0x3c004 0x4>;
1109 clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>;
1113 ranges = <0x0 0x3c000 0x2000>,
1114 <0x46400000 0x46400000 0x400000>;
1116 mcasp1: mcasp@0 {
1118 reg = <0x0 0x2000>,
1119 <0x46400000 0x400000>;
1130 timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */
1132 reg = <0x40000 0x4>,
1133 <0x40010 0x4>,
1134 <0x40014 0x4>;
1142 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>;
1146 ranges = <0x0 0x40000 0x1000>;
1148 timer2: timer@0 {
1150 reg = <0x0 0x400>;
1157 target-module@42000 { /* 0x48042000, ap 24 1c.0 */
1159 reg = <0x42000 0x4>,
1160 <0x42010 0x4>,
1161 <0x42014 0x4>;
1169 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>;
1173 ranges = <0x0 0x42000 0x1000>;
1175 timer3: timer@0 {
1177 reg = <0x0 0x400>;
1182 target-module@44000 { /* 0x48044000, ap 26 26.0 */
1184 reg = <0x44000 0x4>,
1185 <0x44010 0x4>,
1186 <0x44014 0x4>;
1194 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>;
1198 ranges = <0x0 0x44000 0x1000>;
1200 timer4: timer@0 {
1202 reg = <0x0 0x400>;
1208 target-module@46000 { /* 0x48046000, ap 28 28.0 */
1210 reg = <0x46000 0x4>,
1211 <0x46010 0x4>,
1212 <0x46014 0x4>;
1220 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>;
1224 ranges = <0x0 0x46000 0x1000>;
1226 timer5: timer@0 {
1228 reg = <0x0 0x400>;
1234 target-module@48000 { /* 0x48048000, ap 30 22.0 */
1236 reg = <0x48000 0x4>,
1237 <0x48010 0x4>,
1238 <0x48014 0x4>;
1246 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>;
1250 ranges = <0x0 0x48000 0x1000>;
1252 timer6: timer@0 {
1254 reg = <0x0 0x400>;
1260 target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
1262 reg = <0x4a000 0x4>,
1263 <0x4a010 0x4>,
1264 <0x4a014 0x4>;
1272 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>;
1276 ranges = <0x0 0x4a000 0x1000>;
1278 timer7: timer@0 {
1280 reg = <0x0 0x400>;
1286 target-module@4c000 { /* 0x4804c000, ap 32 36.0 */
1288 reg = <0x4c000 0x4>,
1289 <0x4c010 0x4>,
1290 <0x4c114 0x4>;
1301 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>,
1306 ranges = <0x0 0x4c000 0x1000>;
1308 gpio1: gpio@0 {
1310 gpio-ranges = <&am33xx_pinmux 0 0 8>,
1318 reg = <0x0 0x1000>;
1323 target-module@50000 { /* 0x48050000, ap 34 2c.0 */
1328 ranges = <0x0 0x50000 0x2000>;
1331 target-module@60000 { /* 0x48060000, ap 36 0c.0 */
1333 reg = <0x602fc 0x4>,
1334 <0x60110 0x4>,
1335 <0x60114 0x4>;
1346 clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>;
1350 ranges = <0x0 0x60000 0x1000>;
1352 mmc1: mmc@0 {
1355 dmas = <&edma_xbar 24 0 0
1356 &edma_xbar 25 0 0>;
1359 reg = <0x0 0x1000>;
1364 target-module@80000 { /* 0x48080000, ap 38 18.0 */
1366 reg = <0x80000 0x4>,
1367 <0x80010 0x4>,
1368 <0x80014 0x4>;
1378 clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>;
1382 ranges = <0x0 0x80000 0x10000>;
1384 elm: elm@0 {
1386 reg = <0x0 0x2000>;
1392 target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */
1397 ranges = <0x0 0xa0000 0x10000>;
1400 target-module@c8000 { /* 0x480c8000, ap 87 06.0 */
1402 reg = <0xc8000 0x4>,
1403 <0xc8010 0x4>;
1410 clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>;
1414 ranges = <0x0 0xc8000 0x1000>;
1416 mailbox: mailbox@0 {
1418 reg = <0x0 0x200>;
1425 ti,mbox-tx = <0 0 0>;
1426 ti,mbox-rx = <0 0 3>;
1431 target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
1433 reg = <0xca000 0x4>,
1434 <0xca010 0x4>,
1435 <0xca014 0x4>;
1446 clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>;
1450 ranges = <0x0 0xca000 0x1000>;
1452 hwspinlock: spinlock@0 {
1454 reg = <0x0 0x1000>;
1459 target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */
1464 ranges = <0x0 0xcc000 0x1000>;
1468 segment@100000 { /* 0x48100000 */
1472 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */
1473 <0x0008d000 0x0018d000 0x001000>, /* ap 43 */
1474 <0x0008e000 0x0018e000 0x001000>, /* ap 44 */
1475 <0x0008f000 0x0018f000 0x001000>, /* ap 45 */
1476 <0x0009c000 0x0019c000 0x001000>, /* ap 46 */
1477 <0x0009d000 0x0019d000 0x001000>, /* ap 47 */
1478 <0x000a6000 0x001a6000 0x001000>, /* ap 48 */
1479 <0x000a7000 0x001a7000 0x001000>, /* ap 49 */
1480 <0x000a8000 0x001a8000 0x001000>, /* ap 50 */
1481 <0x000a9000 0x001a9000 0x001000>, /* ap 51 */
1482 <0x000aa000 0x001aa000 0x001000>, /* ap 52 */
1483 <0x000ab000 0x001ab000 0x001000>, /* ap 53 */
1484 <0x000ac000 0x001ac000 0x001000>, /* ap 54 */
1485 <0x000ad000 0x001ad000 0x001000>, /* ap 55 */
1486 <0x000ae000 0x001ae000 0x001000>, /* ap 56 */
1487 <0x000af000 0x001af000 0x001000>, /* ap 57 */
1488 <0x000b0000 0x001b0000 0x010000>, /* ap 58 */
1489 <0x000c0000 0x001c0000 0x001000>, /* ap 59 */
1490 <0x000cc000 0x001cc000 0x002000>, /* ap 60 */
1491 <0x000ce000 0x001ce000 0x002000>, /* ap 61 */
1492 <0x000d0000 0x001d0000 0x002000>, /* ap 62 */
1493 <0x000d2000 0x001d2000 0x002000>, /* ap 63 */
1494 <0x000d8000 0x001d8000 0x001000>, /* ap 64 */
1495 <0x000d9000 0x001d9000 0x001000>, /* ap 65 */
1496 <0x000a0000 0x001a0000 0x001000>, /* ap 79 */
1497 <0x000a1000 0x001a1000 0x001000>, /* ap 80 */
1498 <0x000a2000 0x001a2000 0x001000>, /* ap 81 */
1499 <0x000a3000 0x001a3000 0x001000>, /* ap 82 */
1500 <0x000a4000 0x001a4000 0x001000>, /* ap 83 */
1501 <0x000a5000 0x001a5000 0x001000>; /* ap 84 */
1503 target-module@8c000 { /* 0x4818c000, ap 42 04.0 */
1508 ranges = <0x0 0x8c000 0x1000>;
1511 target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */
1516 ranges = <0x0 0x8e000 0x1000>;
1519 target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */
1521 reg = <0x9c000 0x8>,
1522 <0x9c010 0x8>,
1523 <0x9c090 0x8>;
1535 clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>;
1539 ranges = <0x0 0x9c000 0x1000>;
1541 i2c2: i2c@0 {
1544 #size-cells = <0>;
1545 reg = <0x0 0x1000>;
1551 target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
1553 reg = <0xa0000 0x4>,
1554 <0xa0110 0x4>,
1555 <0xa0114 0x4>;
1565 clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>;
1569 ranges = <0x0 0xa0000 0x1000>;
1571 spi1: spi@0 {
1574 #size-cells = <0>;
1575 reg = <0x0 0x400>;
1578 dmas = <&edma 42 0
1579 &edma 43 0
1580 &edma 44 0
1581 &edma 45 0>;
1587 target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */
1592 ranges = <0x0 0xa2000 0x1000>;
1595 target-module@a4000 { /* 0x481a4000, ap 83 30.0 */
1600 ranges = <0x0 0xa4000 0x1000>;
1603 target-module@a6000 { /* 0x481a6000, ap 48 16.0 */
1605 reg = <0xa6050 0x4>,
1606 <0xa6054 0x4>,
1607 <0xa6058 0x4>;
1617 clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>;
1621 ranges = <0x0 0xa6000 0x1000>;
1623 uart3: serial@0 {
1626 reg = <0x0 0x1000>;
1632 target-module@a8000 { /* 0x481a8000, ap 50 20.0 */
1634 reg = <0xa8050 0x4>,
1635 <0xa8054 0x4>,
1636 <0xa8058 0x4>;
1646 clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>;
1650 ranges = <0x0 0xa8000 0x1000>;
1652 uart4: serial@0 {
1655 reg = <0x0 0x1000>;
1661 target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */
1663 reg = <0xaa050 0x4>,
1664 <0xaa054 0x4>,
1665 <0xaa058 0x4>;
1675 clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>;
1679 ranges = <0x0 0xaa000 0x1000>;
1681 uart5: serial@0 {
1684 reg = <0x0 0x1000>;
1690 target-module@ac000 { /* 0x481ac000, ap 54 38.0 */
1692 reg = <0xac000 0x4>,
1693 <0xac010 0x4>,
1694 <0xac114 0x4>;
1705 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>,
1710 ranges = <0x0 0xac000 0x1000>;
1712 gpio2: gpio@0 {
1714 gpio-ranges = <&am33xx_pinmux 0 34 18>,
1721 reg = <0x0 0x1000>;
1726 target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
1728 reg = <0xae000 0x4>,
1729 <0xae010 0x4>,
1730 <0xae114 0x4>;
1741 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>,
1746 ranges = <0x0 0xae000 0x1000>;
1748 gpio3: gpio@0 {
1750 gpio-ranges = <&am33xx_pinmux 0 66 5>,
1759 reg = <0x0 0x1000>;
1764 target-module@b0000 { /* 0x481b0000, ap 58 50.0 */
1769 ranges = <0x0 0xb0000 0x10000>;
1772 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
1774 reg = <0xcc020 0x4>;
1777 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
1782 ranges = <0x0 0xcc000 0x2000>;
1784 dcan0: can@0 {
1786 reg = <0x0 0x2000>;
1789 syscon-raminit = <&scm_conf 0x644 0>;
1795 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
1797 reg = <0xd0020 0x4>;
1800 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
1805 ranges = <0x0 0xd0000 0x2000>;
1807 dcan1: can@0 {
1809 reg = <0x0 0x2000>;
1812 syscon-raminit = <&scm_conf 0x644 1>;
1818 target-module@d8000 { /* 0x481d8000, ap 64 66.0 */
1820 reg = <0xd82fc 0x4>,
1821 <0xd8110 0x4>,
1822 <0xd8114 0x4>;
1833 clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>;
1837 ranges = <0x0 0xd8000 0x1000>;
1839 mmc2: mmc@0 {
1842 dmas = <&edma 2 0
1843 &edma 3 0>;
1846 reg = <0x0 0x1000>;
1852 segment@200000 { /* 0x48200000 */
1858 segment@300000 { /* 0x48300000 */
1862 ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */
1863 <0x00001000 0x00301000 0x001000>, /* ap 67 */
1864 <0x00002000 0x00302000 0x001000>, /* ap 68 */
1865 <0x00003000 0x00303000 0x001000>, /* ap 69 */
1866 <0x00004000 0x00304000 0x001000>, /* ap 70 */
1867 <0x00005000 0x00305000 0x001000>, /* ap 71 */
1868 <0x0000e000 0x0030e000 0x001000>, /* ap 72 */
1869 <0x0000f000 0x0030f000 0x001000>, /* ap 73 */
1870 <0x00018000 0x00318000 0x004000>, /* ap 74 */
1871 <0x0001c000 0x0031c000 0x001000>, /* ap 75 */
1872 <0x00010000 0x00310000 0x002000>, /* ap 76 */
1873 <0x00012000 0x00312000 0x001000>, /* ap 93 */
1874 <0x00015000 0x00315000 0x001000>, /* ap 94 */
1875 <0x00016000 0x00316000 0x001000>, /* ap 95 */
1876 <0x00017000 0x00317000 0x001000>, /* ap 96 */
1877 <0x00013000 0x00313000 0x001000>, /* ap 97 */
1878 <0x00014000 0x00314000 0x001000>, /* ap 98 */
1879 <0x00020000 0x00320000 0x001000>, /* ap 99 */
1880 <0x00021000 0x00321000 0x001000>, /* ap 100 */
1881 <0x00022000 0x00322000 0x001000>, /* ap 101 */
1882 <0x00023000 0x00323000 0x001000>, /* ap 102 */
1883 <0x00024000 0x00324000 0x001000>, /* ap 103 */
1884 <0x00025000 0x00325000 0x001000>; /* ap 104 */
1886 target-module@0 { /* 0x48300000, ap 66 48.0 */
1888 reg = <0x0 0x4>,
1889 <0x4 0x4>;
1900 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>;
1904 ranges = <0x0 0x0 0x1000>;
1906 epwmss0: epwmss@0 {
1908 reg = <0x0 0x10>;
1912 ranges = <0 0 0x1000>;
1918 reg = <0x100 0x80>;
1930 reg = <0x200 0x80>;
1938 target-module@2000 { /* 0x48302000, ap 68 52.0 */
1940 reg = <0x2000 0x4>,
1941 <0x2004 0x4>;
1952 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>;
1956 ranges = <0x0 0x2000 0x1000>;
1958 epwmss1: epwmss@0 {
1960 reg = <0x0 0x10>;
1964 ranges = <0 0 0x1000>;
1970 reg = <0x100 0x80>;
1982 reg = <0x200 0x80>;
1990 target-module@4000 { /* 0x48304000, ap 70 44.0 */
1992 reg = <0x4000 0x4>,
1993 <0x4004 0x4>;
2004 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>;
2008 ranges = <0x0 0x4000 0x1000>;
2010 epwmss2: epwmss@0 {
2012 reg = <0x0 0x10>;
2016 ranges = <0 0 0x1000>;
2022 reg = <0x100 0x80>;
2034 reg = <0x200 0x80>;
2042 target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
2044 reg = <0xe000 0x4>,
2045 <0xe054 0x4>;
2054 clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>;
2058 ranges = <0x0 0xe000 0x1000>;
2060 lcdc: lcdc@0 {
2062 reg = <0x0 0x1000>;
2068 target-module@10000 { /* 0x48310000, ap 76 4e.1 */
2070 reg = <0x11fe0 0x4>,
2071 <0x11fe4 0x4>;
2077 clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>;
2081 ranges = <0x0 0x10000 0x2000>;
2083 rng: rng@0 {
2085 reg = <0x0 0x2000>;
2090 target-module@13000 { /* 0x48313000, ap 97 62.0 */
2095 ranges = <0x0 0x13000 0x1000>;
2098 target-module@15000 { /* 0x48315000, ap 94 56.0 */
2103 ranges = <0x00000000 0x00015000 0x00001000>,
2104 <0x00001000 0x00016000 0x00001000>;
2107 target-module@18000 { /* 0x48318000, ap 74 4c.0 */
2112 ranges = <0x0 0x18000 0x4000>;
2115 target-module@20000 { /* 0x48320000, ap 99 34.0 */
2120 ranges = <0x0 0x20000 0x1000>;
2123 target-module@22000 { /* 0x48322000, ap 101 3e.0 */
2128 ranges = <0x0 0x22000 0x1000>;
2131 target-module@24000 { /* 0x48324000, ap 103 68.0 */
2136 ranges = <0x0 0x24000 0x1000>;