Lines Matching +full:0 +full:x32000
35 #size-cells = <0>;
36 cpu@0 {
39 reg = <0>;
69 reg = <0x47400000 0x1000>;
77 reg = <0x47401300 0x100>;
80 #phy-cells = <0>;
85 reg = <0x47401400 0x400
86 0x47401000 0x200>;
98 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
99 &cppi41dma 2 0 &cppi41dma 3 0
100 &cppi41dma 4 0 &cppi41dma 5 0
101 &cppi41dma 6 0 &cppi41dma 7 0
102 &cppi41dma 8 0 &cppi41dma 9 0
103 &cppi41dma 10 0 &cppi41dma 11 0
104 &cppi41dma 12 0 &cppi41dma 13 0
105 &cppi41dma 14 0 &cppi41dma 0 1
124 reg = <0x47401c00 0x400
125 0x47401800 0x200>;
136 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
137 &cppi41dma 17 0 &cppi41dma 18 0
138 &cppi41dma 19 0 &cppi41dma 20 0
139 &cppi41dma 21 0 &cppi41dma 22 0
140 &cppi41dma 23 0 &cppi41dma 24 0
141 &cppi41dma 25 0 &cppi41dma 26 0
142 &cppi41dma 27 0 &cppi41dma 28 0
143 &cppi41dma 29 0 &cppi41dma 15 1
162 reg = <0x47400000 0x1000
163 0x47402000 0x1000
164 0x47403000 0x1000
165 0x47404000 0x4000>;
178 * actual device is typically 0x1000 before the target agent
179 * except in cases where the module is larger than 0x1000.
185 ranges = <0 0x48000000 0x2000000>;
190 #size-cells = <0>;
192 reg = <0x28000 0x1000>;
199 reg = <0x80000 0x2000>;
207 reg = <0x32000 0x2000>;
219 reg = <0x4c000 0x2000>;
231 reg = <0x1ac000 0x2000>;
243 reg = <0x1ae000 0x2000>;
254 #size-cells = <0>;
256 reg = <0x2a000 0x1000>;
262 reg = <0x30000 0x1000>;
264 #size-cells = <0>;
268 dmas = <&edma 16 0 &edma 17 0
269 &edma 18 0 &edma 19 0
270 &edma 20 0 &edma 21 0
271 &edma 22 0 &edma 23 0>;
279 reg = <0x1a0000 0x1000>;
281 #size-cells = <0>;
285 dmas = <&edma 42 0 &edma 43 0
286 &edma 44 0 &edma 45 0>;
293 reg = <0x1a2000 0x1000>;
295 #size-cells = <0>;
303 reg = <0x1a4000 0x1000>;
305 #size-cells = <0>;
313 reg = <0x2e000 0x4>,
314 <0x2e010 0x4>;
325 ranges = <0x0 0x2e000 0x1000>;
327 timer1: timer@0 {
329 reg = <0x0 0x400>;
340 reg = <0x20000 0x2000>;
343 dmas = <&edma 26 0 &edma 27 0>;
350 reg = <0x22000 0x2000>;
353 dmas = <&edma 28 0 &edma 29 0>;
360 reg = <0x24000 0x2000>;
363 dmas = <&edma 30 0 &edma 31 0>;
369 reg = <0x40000 0x4>,
370 <0x40010 0x4>;
381 ranges = <0x0 0x40000 0x1000>;
383 timer2: timer@0 {
385 reg = <0 0x1000>;
394 reg = <0x42000 0x2000>;
402 dmas = <&edma 24 0
403 &edma 25 0>;
407 reg = <0x60000 0x1000>;
412 reg = <0xc0000 0x1000>;
420 dmas = <&edma 2 0
421 &edma 3 0>;
425 reg = <0x1d8000 0x1000>;
430 reg = <0x140000 0x20000>;
433 ranges = <0 0x140000 0x20000>;
435 scm_conf: scm_conf@0 {
437 reg = <0x0 0x800>;
440 ranges = <0 0 0x800>;
444 reg = <0x650 0x4>;
450 #size-cells = <0>;
459 reg = <0x620 0x10
460 0x648 0x4>;
466 reg = <0xf90 0x40>;
482 reg = <0x800 0x438>;
484 #size-cells = <0>;
487 pinctrl-single,function-mask = <0x307ff>;
492 reg = <0x1b00 0x100>;
495 #phy-cells = <0>;
501 reg = <0x180000 0x2000>;
504 ranges = <0 0x180000 0x2000>;
508 #size-cells = <0>;
518 reg = <0x1c5000 0x1000>;
521 ranges = <0 0x1c5000 0x1000>;
525 #size-cells = <0>;
535 reg = <0x1c7000 0x1000>;
544 reg = <0x48200000 0x1000>;
553 reg = <0x47810000 0x1000>;
558 reg = <0x49000000 0x4>;
560 clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>;
564 ranges = <0x0 0x49000000 0x10000>;
566 edma: dma@0 {
568 reg = <0 0x10000>;
577 <&edma_tptc2 3>, <&edma_tptc3 0>;
585 reg = <0x49800000 0x4>,
586 <0x49800010 0x4>;
592 clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>;
596 ranges = <0x0 0x49800000 0x100000>;
598 edma_tptc0: dma@0 {
600 reg = <0 0x100000>;
608 reg = <0x49900000 0x4>,
609 <0x49900010 0x4>;
615 clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>;
619 ranges = <0x0 0x49900000 0x100000>;
621 edma_tptc1: dma@0 {
623 reg = <0 0x100000>;
631 reg = <0x49a00000 0x4>,
632 <0x49a00010 0x4>;
638 clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>;
642 ranges = <0x0 0x49a00000 0x100000>;
644 edma_tptc2: dma@0 {
646 reg = <0 0x100000>;
654 reg = <0x49b00000 0x4>,
655 <0x49b00010 0x4>;
661 clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>;
665 ranges = <0x0 0x49b00000 0x100000>;
667 edma_tptc3: dma@0 {
669 reg = <0 0x100000>;
680 ranges = <0 0x4a000000 0x1b4040>;
684 reg = <0x100900 0x4>,
685 <0x100908 0x4>,
686 <0x100904 0x4>;
688 ti,sysc-mask = <0>;
694 clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
698 ranges = <0 0x100000 0x8000>;
700 mac: ethernet@0 {
706 bd_ram_size = <0x2000>;
707 mac_control = <0x20>;
709 active_slave = <0>;
710 cpts_clock_mult = <0x80000000>;
712 reg = <0 0x800>,
713 <0x900 0x100>;
723 ranges = <0 0 0x8000>;
731 #size-cells = <0>;
733 reg = <0x800 0x100>;
755 reg = <0x50000000 0x2000>;
775 timer@0 {
785 timer@0 {