1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges; 24 25 simplefb_cvbs: framebuffer-cvbs { 26 compatible = "amlogic,simple-framebuffer", 27 "simple-framebuffer"; 28 amlogic,pipeline = "vpu-cvbs"; 29 clocks = <&clkc CLKID_HDMI>, 30 <&clkc CLKID_HTX_PCLK>, 31 <&clkc CLKID_VPU_INTR>; 32 status = "disabled"; 33 }; 34 35 simplefb_hdmi: framebuffer-hdmi { 36 compatible = "amlogic,simple-framebuffer", 37 "simple-framebuffer"; 38 amlogic,pipeline = "vpu-hdmi"; 39 clocks = <&clkc CLKID_HDMI>, 40 <&clkc CLKID_HTX_PCLK>, 41 <&clkc CLKID_VPU_INTR>; 42 status = "disabled"; 43 }; 44 }; 45 46 efuse: efuse { 47 compatible = "amlogic,meson-gxbb-efuse"; 48 clocks = <&clkc CLKID_EFUSE>; 49 #address-cells = <1>; 50 #size-cells = <1>; 51 read-only; 52 secure-monitor = <&sm>; 53 }; 54 55 gpu_opp_table: gpu-opp-table { 56 compatible = "operating-points-v2"; 57 58 opp-124999998 { 59 opp-hz = /bits/ 64 <124999998>; 60 opp-microvolt = <800000>; 61 }; 62 opp-249999996 { 63 opp-hz = /bits/ 64 <249999996>; 64 opp-microvolt = <800000>; 65 }; 66 opp-285714281 { 67 opp-hz = /bits/ 64 <285714281>; 68 opp-microvolt = <800000>; 69 }; 70 opp-399999994 { 71 opp-hz = /bits/ 64 <399999994>; 72 opp-microvolt = <800000>; 73 }; 74 opp-499999992 { 75 opp-hz = /bits/ 64 <499999992>; 76 opp-microvolt = <800000>; 77 }; 78 opp-666666656 { 79 opp-hz = /bits/ 64 <666666656>; 80 opp-microvolt = <800000>; 81 }; 82 opp-799999987 { 83 opp-hz = /bits/ 64 <799999987>; 84 opp-microvolt = <800000>; 85 }; 86 }; 87 88 psci { 89 compatible = "arm,psci-1.0"; 90 method = "smc"; 91 }; 92 93 reserved-memory { 94 #address-cells = <2>; 95 #size-cells = <2>; 96 ranges; 97 98 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 99 secmon_reserved: secmon@5000000 { 100 reg = <0x0 0x05000000 0x0 0x300000>; 101 no-map; 102 }; 103 104 linux,cma { 105 compatible = "shared-dma-pool"; 106 reusable; 107 size = <0x0 0x10000000>; 108 alignment = <0x0 0x400000>; 109 linux,cma-default; 110 }; 111 }; 112 113 sm: secure-monitor { 114 compatible = "amlogic,meson-gxbb-sm"; 115 }; 116 117 soc { 118 compatible = "simple-bus"; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges; 122 123 pcie: pcie@fc000000 { 124 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 125 reg = <0x0 0xfc000000 0x0 0x400000 126 0x0 0xff648000 0x0 0x2000 127 0x0 0xfc400000 0x0 0x200000>; 128 reg-names = "elbi", "cfg", "config"; 129 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 130 #interrupt-cells = <1>; 131 interrupt-map-mask = <0 0 0 0>; 132 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 133 bus-range = <0x0 0xff>; 134 #address-cells = <3>; 135 #size-cells = <2>; 136 device_type = "pci"; 137 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000 138 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 139 140 clocks = <&clkc CLKID_PCIE_PHY 141 &clkc CLKID_PCIE_COMB 142 &clkc CLKID_PCIE_PLL>; 143 clock-names = "general", 144 "pclk", 145 "port"; 146 resets = <&reset RESET_PCIE_CTRL_A>, 147 <&reset RESET_PCIE_APB>; 148 reset-names = "port", 149 "apb"; 150 num-lanes = <1>; 151 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 152 phy-names = "pcie"; 153 status = "disabled"; 154 }; 155 156 thermal-zones { 157 cpu_thermal: cpu-thermal { 158 polling-delay = <1000>; 159 polling-delay-passive = <100>; 160 thermal-sensors = <&cpu_temp>; 161 162 trips { 163 cpu_passive: cpu-passive { 164 temperature = <85000>; /* millicelsius */ 165 hysteresis = <2000>; /* millicelsius */ 166 type = "passive"; 167 }; 168 169 cpu_hot: cpu-hot { 170 temperature = <95000>; /* millicelsius */ 171 hysteresis = <2000>; /* millicelsius */ 172 type = "hot"; 173 }; 174 175 cpu_critical: cpu-critical { 176 temperature = <110000>; /* millicelsius */ 177 hysteresis = <2000>; /* millicelsius */ 178 type = "critical"; 179 }; 180 }; 181 }; 182 183 ddr_thermal: ddr-thermal { 184 polling-delay = <1000>; 185 polling-delay-passive = <100>; 186 thermal-sensors = <&ddr_temp>; 187 188 trips { 189 ddr_passive: ddr-passive { 190 temperature = <85000>; /* millicelsius */ 191 hysteresis = <2000>; /* millicelsius */ 192 type = "passive"; 193 }; 194 195 ddr_critical: ddr-critical { 196 temperature = <110000>; /* millicelsius */ 197 hysteresis = <2000>; /* millicelsius */ 198 type = "critical"; 199 }; 200 }; 201 202 cooling-maps { 203 map { 204 trip = <&ddr_passive>; 205 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 206 }; 207 }; 208 }; 209 }; 210 211 ethmac: ethernet@ff3f0000 { 212 compatible = "amlogic,meson-g12a-dwmac", 213 "snps,dwmac-3.70a", 214 "snps,dwmac"; 215 reg = <0x0 0xff3f0000 0x0 0x10000>, 216 <0x0 0xff634540 0x0 0x8>; 217 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 218 interrupt-names = "macirq"; 219 clocks = <&clkc CLKID_ETH>, 220 <&clkc CLKID_FCLK_DIV2>, 221 <&clkc CLKID_MPLL2>, 222 <&clkc CLKID_FCLK_DIV2>; 223 clock-names = "stmmaceth", "clkin0", "clkin1", 224 "timing-adjustment"; 225 rx-fifo-depth = <4096>; 226 tx-fifo-depth = <2048>; 227 resets = <&reset RESET_ETHERNET>; 228 reset-names = "stmmaceth"; 229 status = "disabled"; 230 231 mdio0: mdio { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 compatible = "snps,dwmac-mdio"; 235 }; 236 }; 237 238 apb: bus@ff600000 { 239 compatible = "simple-bus"; 240 reg = <0x0 0xff600000 0x0 0x200000>; 241 #address-cells = <2>; 242 #size-cells = <2>; 243 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 244 245 hdmi_tx: hdmi-tx@0 { 246 compatible = "amlogic,meson-g12a-dw-hdmi"; 247 reg = <0x0 0x0 0x0 0x10000>; 248 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 249 resets = <&reset RESET_HDMITX_CAPB3>, 250 <&reset RESET_HDMITX_PHY>, 251 <&reset RESET_HDMITX>; 252 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 253 clocks = <&clkc CLKID_HDMI>, 254 <&clkc CLKID_HTX_PCLK>, 255 <&clkc CLKID_VPU_INTR>; 256 clock-names = "isfr", "iahb", "venci"; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 #sound-dai-cells = <0>; 260 status = "disabled"; 261 262 /* VPU VENC Input */ 263 hdmi_tx_venc_port: port@0 { 264 reg = <0>; 265 266 hdmi_tx_in: endpoint { 267 remote-endpoint = <&hdmi_tx_out>; 268 }; 269 }; 270 271 /* TMDS Output */ 272 hdmi_tx_tmds_port: port@1 { 273 reg = <1>; 274 }; 275 }; 276 277 apb_efuse: bus@30000 { 278 compatible = "simple-bus"; 279 reg = <0x0 0x30000 0x0 0x2000>; 280 #address-cells = <2>; 281 #size-cells = <2>; 282 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 283 284 hwrng: rng@218 { 285 compatible = "amlogic,meson-rng"; 286 reg = <0x0 0x218 0x0 0x4>; 287 clocks = <&clkc CLKID_RNG0>; 288 clock-names = "core"; 289 }; 290 }; 291 292 acodec: audio-controller@32000 { 293 compatible = "amlogic,t9015"; 294 reg = <0x0 0x32000 0x0 0x14>; 295 #sound-dai-cells = <0>; 296 sound-name-prefix = "ACODEC"; 297 clocks = <&clkc CLKID_AUDIO_CODEC>; 298 clock-names = "pclk"; 299 resets = <&reset RESET_AUDIO_CODEC>; 300 status = "disabled"; 301 }; 302 303 periphs: bus@34400 { 304 compatible = "simple-bus"; 305 reg = <0x0 0x34400 0x0 0x400>; 306 #address-cells = <2>; 307 #size-cells = <2>; 308 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 309 310 periphs_pinctrl: pinctrl@40 { 311 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 312 #address-cells = <2>; 313 #size-cells = <2>; 314 ranges; 315 316 gpio: bank@40 { 317 reg = <0x0 0x40 0x0 0x4c>, 318 <0x0 0xe8 0x0 0x18>, 319 <0x0 0x120 0x0 0x18>, 320 <0x0 0x2c0 0x0 0x40>, 321 <0x0 0x340 0x0 0x1c>; 322 reg-names = "gpio", 323 "pull", 324 "pull-enable", 325 "mux", 326 "ds"; 327 gpio-controller; 328 #gpio-cells = <2>; 329 gpio-ranges = <&periphs_pinctrl 0 0 86>; 330 }; 331 332 cec_ao_a_h_pins: cec_ao_a_h { 333 mux { 334 groups = "cec_ao_a_h"; 335 function = "cec_ao_a_h"; 336 bias-disable; 337 }; 338 }; 339 340 cec_ao_b_h_pins: cec_ao_b_h { 341 mux { 342 groups = "cec_ao_b_h"; 343 function = "cec_ao_b_h"; 344 bias-disable; 345 }; 346 }; 347 348 emmc_ctrl_pins: emmc-ctrl { 349 mux-0 { 350 groups = "emmc_cmd"; 351 function = "emmc"; 352 bias-pull-up; 353 drive-strength-microamp = <4000>; 354 }; 355 356 mux-1 { 357 groups = "emmc_clk"; 358 function = "emmc"; 359 bias-disable; 360 drive-strength-microamp = <4000>; 361 }; 362 }; 363 364 emmc_data_4b_pins: emmc-data-4b { 365 mux-0 { 366 groups = "emmc_nand_d0", 367 "emmc_nand_d1", 368 "emmc_nand_d2", 369 "emmc_nand_d3"; 370 function = "emmc"; 371 bias-pull-up; 372 drive-strength-microamp = <4000>; 373 }; 374 }; 375 376 emmc_data_8b_pins: emmc-data-8b { 377 mux-0 { 378 groups = "emmc_nand_d0", 379 "emmc_nand_d1", 380 "emmc_nand_d2", 381 "emmc_nand_d3", 382 "emmc_nand_d4", 383 "emmc_nand_d5", 384 "emmc_nand_d6", 385 "emmc_nand_d7"; 386 function = "emmc"; 387 bias-pull-up; 388 drive-strength-microamp = <4000>; 389 }; 390 }; 391 392 emmc_ds_pins: emmc-ds { 393 mux { 394 groups = "emmc_nand_ds"; 395 function = "emmc"; 396 bias-pull-down; 397 drive-strength-microamp = <4000>; 398 }; 399 }; 400 401 emmc_clk_gate_pins: emmc_clk_gate { 402 mux { 403 groups = "BOOT_8"; 404 function = "gpio_periphs"; 405 bias-pull-down; 406 drive-strength-microamp = <4000>; 407 }; 408 }; 409 410 hdmitx_ddc_pins: hdmitx_ddc { 411 mux { 412 groups = "hdmitx_sda", 413 "hdmitx_sck"; 414 function = "hdmitx"; 415 bias-disable; 416 drive-strength-microamp = <4000>; 417 }; 418 }; 419 420 hdmitx_hpd_pins: hdmitx_hpd { 421 mux { 422 groups = "hdmitx_hpd_in"; 423 function = "hdmitx"; 424 bias-disable; 425 }; 426 }; 427 428 429 i2c0_sda_c_pins: i2c0-sda-c { 430 mux { 431 groups = "i2c0_sda_c"; 432 function = "i2c0"; 433 bias-disable; 434 drive-strength-microamp = <3000>; 435 436 }; 437 }; 438 439 i2c0_sck_c_pins: i2c0-sck-c { 440 mux { 441 groups = "i2c0_sck_c"; 442 function = "i2c0"; 443 bias-disable; 444 drive-strength-microamp = <3000>; 445 }; 446 }; 447 448 i2c0_sda_z0_pins: i2c0-sda-z0 { 449 mux { 450 groups = "i2c0_sda_z0"; 451 function = "i2c0"; 452 bias-disable; 453 drive-strength-microamp = <3000>; 454 }; 455 }; 456 457 i2c0_sck_z1_pins: i2c0-sck-z1 { 458 mux { 459 groups = "i2c0_sck_z1"; 460 function = "i2c0"; 461 bias-disable; 462 drive-strength-microamp = <3000>; 463 }; 464 }; 465 466 i2c0_sda_z7_pins: i2c0-sda-z7 { 467 mux { 468 groups = "i2c0_sda_z7"; 469 function = "i2c0"; 470 bias-disable; 471 drive-strength-microamp = <3000>; 472 }; 473 }; 474 475 i2c0_sda_z8_pins: i2c0-sda-z8 { 476 mux { 477 groups = "i2c0_sda_z8"; 478 function = "i2c0"; 479 bias-disable; 480 drive-strength-microamp = <3000>; 481 }; 482 }; 483 484 i2c1_sda_x_pins: i2c1-sda-x { 485 mux { 486 groups = "i2c1_sda_x"; 487 function = "i2c1"; 488 bias-disable; 489 drive-strength-microamp = <3000>; 490 }; 491 }; 492 493 i2c1_sck_x_pins: i2c1-sck-x { 494 mux { 495 groups = "i2c1_sck_x"; 496 function = "i2c1"; 497 bias-disable; 498 drive-strength-microamp = <3000>; 499 }; 500 }; 501 502 i2c1_sda_h2_pins: i2c1-sda-h2 { 503 mux { 504 groups = "i2c1_sda_h2"; 505 function = "i2c1"; 506 bias-disable; 507 drive-strength-microamp = <3000>; 508 }; 509 }; 510 511 i2c1_sck_h3_pins: i2c1-sck-h3 { 512 mux { 513 groups = "i2c1_sck_h3"; 514 function = "i2c1"; 515 bias-disable; 516 drive-strength-microamp = <3000>; 517 }; 518 }; 519 520 i2c1_sda_h6_pins: i2c1-sda-h6 { 521 mux { 522 groups = "i2c1_sda_h6"; 523 function = "i2c1"; 524 bias-disable; 525 drive-strength-microamp = <3000>; 526 }; 527 }; 528 529 i2c1_sck_h7_pins: i2c1-sck-h7 { 530 mux { 531 groups = "i2c1_sck_h7"; 532 function = "i2c1"; 533 bias-disable; 534 drive-strength-microamp = <3000>; 535 }; 536 }; 537 538 i2c2_sda_x_pins: i2c2-sda-x { 539 mux { 540 groups = "i2c2_sda_x"; 541 function = "i2c2"; 542 bias-disable; 543 drive-strength-microamp = <3000>; 544 }; 545 }; 546 547 i2c2_sck_x_pins: i2c2-sck-x { 548 mux { 549 groups = "i2c2_sck_x"; 550 function = "i2c2"; 551 bias-disable; 552 drive-strength-microamp = <3000>; 553 }; 554 }; 555 556 i2c2_sda_z_pins: i2c2-sda-z { 557 mux { 558 groups = "i2c2_sda_z"; 559 function = "i2c2"; 560 bias-disable; 561 drive-strength-microamp = <3000>; 562 }; 563 }; 564 565 i2c2_sck_z_pins: i2c2-sck-z { 566 mux { 567 groups = "i2c2_sck_z"; 568 function = "i2c2"; 569 bias-disable; 570 drive-strength-microamp = <3000>; 571 }; 572 }; 573 574 i2c3_sda_h_pins: i2c3-sda-h { 575 mux { 576 groups = "i2c3_sda_h"; 577 function = "i2c3"; 578 bias-disable; 579 drive-strength-microamp = <3000>; 580 }; 581 }; 582 583 i2c3_sck_h_pins: i2c3-sck-h { 584 mux { 585 groups = "i2c3_sck_h"; 586 function = "i2c3"; 587 bias-disable; 588 drive-strength-microamp = <3000>; 589 }; 590 }; 591 592 i2c3_sda_a_pins: i2c3-sda-a { 593 mux { 594 groups = "i2c3_sda_a"; 595 function = "i2c3"; 596 bias-disable; 597 drive-strength-microamp = <3000>; 598 }; 599 }; 600 601 i2c3_sck_a_pins: i2c3-sck-a { 602 mux { 603 groups = "i2c3_sck_a"; 604 function = "i2c3"; 605 bias-disable; 606 drive-strength-microamp = <3000>; 607 }; 608 }; 609 610 mclk0_a_pins: mclk0-a { 611 mux { 612 groups = "mclk0_a"; 613 function = "mclk0"; 614 bias-disable; 615 drive-strength-microamp = <3000>; 616 }; 617 }; 618 619 mclk1_a_pins: mclk1-a { 620 mux { 621 groups = "mclk1_a"; 622 function = "mclk1"; 623 bias-disable; 624 drive-strength-microamp = <3000>; 625 }; 626 }; 627 628 mclk1_x_pins: mclk1-x { 629 mux { 630 groups = "mclk1_x"; 631 function = "mclk1"; 632 bias-disable; 633 drive-strength-microamp = <3000>; 634 }; 635 }; 636 637 mclk1_z_pins: mclk1-z { 638 mux { 639 groups = "mclk1_z"; 640 function = "mclk1"; 641 bias-disable; 642 drive-strength-microamp = <3000>; 643 }; 644 }; 645 646 nor_pins: nor { 647 mux { 648 groups = "nor_d", 649 "nor_q", 650 "nor_c", 651 "nor_cs"; 652 function = "nor"; 653 bias-disable; 654 }; 655 }; 656 657 pdm_din0_a_pins: pdm-din0-a { 658 mux { 659 groups = "pdm_din0_a"; 660 function = "pdm"; 661 bias-disable; 662 }; 663 }; 664 665 pdm_din0_c_pins: pdm-din0-c { 666 mux { 667 groups = "pdm_din0_c"; 668 function = "pdm"; 669 bias-disable; 670 }; 671 }; 672 673 pdm_din0_x_pins: pdm-din0-x { 674 mux { 675 groups = "pdm_din0_x"; 676 function = "pdm"; 677 bias-disable; 678 }; 679 }; 680 681 pdm_din0_z_pins: pdm-din0-z { 682 mux { 683 groups = "pdm_din0_z"; 684 function = "pdm"; 685 bias-disable; 686 }; 687 }; 688 689 pdm_din1_a_pins: pdm-din1-a { 690 mux { 691 groups = "pdm_din1_a"; 692 function = "pdm"; 693 bias-disable; 694 }; 695 }; 696 697 pdm_din1_c_pins: pdm-din1-c { 698 mux { 699 groups = "pdm_din1_c"; 700 function = "pdm"; 701 bias-disable; 702 }; 703 }; 704 705 pdm_din1_x_pins: pdm-din1-x { 706 mux { 707 groups = "pdm_din1_x"; 708 function = "pdm"; 709 bias-disable; 710 }; 711 }; 712 713 pdm_din1_z_pins: pdm-din1-z { 714 mux { 715 groups = "pdm_din1_z"; 716 function = "pdm"; 717 bias-disable; 718 }; 719 }; 720 721 pdm_din2_a_pins: pdm-din2-a { 722 mux { 723 groups = "pdm_din2_a"; 724 function = "pdm"; 725 bias-disable; 726 }; 727 }; 728 729 pdm_din2_c_pins: pdm-din2-c { 730 mux { 731 groups = "pdm_din2_c"; 732 function = "pdm"; 733 bias-disable; 734 }; 735 }; 736 737 pdm_din2_x_pins: pdm-din2-x { 738 mux { 739 groups = "pdm_din2_x"; 740 function = "pdm"; 741 bias-disable; 742 }; 743 }; 744 745 pdm_din2_z_pins: pdm-din2-z { 746 mux { 747 groups = "pdm_din2_z"; 748 function = "pdm"; 749 bias-disable; 750 }; 751 }; 752 753 pdm_din3_a_pins: pdm-din3-a { 754 mux { 755 groups = "pdm_din3_a"; 756 function = "pdm"; 757 bias-disable; 758 }; 759 }; 760 761 pdm_din3_c_pins: pdm-din3-c { 762 mux { 763 groups = "pdm_din3_c"; 764 function = "pdm"; 765 bias-disable; 766 }; 767 }; 768 769 pdm_din3_x_pins: pdm-din3-x { 770 mux { 771 groups = "pdm_din3_x"; 772 function = "pdm"; 773 bias-disable; 774 }; 775 }; 776 777 pdm_din3_z_pins: pdm-din3-z { 778 mux { 779 groups = "pdm_din3_z"; 780 function = "pdm"; 781 bias-disable; 782 }; 783 }; 784 785 pdm_dclk_a_pins: pdm-dclk-a { 786 mux { 787 groups = "pdm_dclk_a"; 788 function = "pdm"; 789 bias-disable; 790 drive-strength-microamp = <500>; 791 }; 792 }; 793 794 pdm_dclk_c_pins: pdm-dclk-c { 795 mux { 796 groups = "pdm_dclk_c"; 797 function = "pdm"; 798 bias-disable; 799 drive-strength-microamp = <500>; 800 }; 801 }; 802 803 pdm_dclk_x_pins: pdm-dclk-x { 804 mux { 805 groups = "pdm_dclk_x"; 806 function = "pdm"; 807 bias-disable; 808 drive-strength-microamp = <500>; 809 }; 810 }; 811 812 pdm_dclk_z_pins: pdm-dclk-z { 813 mux { 814 groups = "pdm_dclk_z"; 815 function = "pdm"; 816 bias-disable; 817 drive-strength-microamp = <500>; 818 }; 819 }; 820 821 pwm_a_pins: pwm-a { 822 mux { 823 groups = "pwm_a"; 824 function = "pwm_a"; 825 bias-disable; 826 }; 827 }; 828 829 pwm_b_x7_pins: pwm-b-x7 { 830 mux { 831 groups = "pwm_b_x7"; 832 function = "pwm_b"; 833 bias-disable; 834 }; 835 }; 836 837 pwm_b_x19_pins: pwm-b-x19 { 838 mux { 839 groups = "pwm_b_x19"; 840 function = "pwm_b"; 841 bias-disable; 842 }; 843 }; 844 845 pwm_c_c_pins: pwm-c-c { 846 mux { 847 groups = "pwm_c_c"; 848 function = "pwm_c"; 849 bias-disable; 850 }; 851 }; 852 853 pwm_c_x5_pins: pwm-c-x5 { 854 mux { 855 groups = "pwm_c_x5"; 856 function = "pwm_c"; 857 bias-disable; 858 }; 859 }; 860 861 pwm_c_x8_pins: pwm-c-x8 { 862 mux { 863 groups = "pwm_c_x8"; 864 function = "pwm_c"; 865 bias-disable; 866 }; 867 }; 868 869 pwm_d_x3_pins: pwm-d-x3 { 870 mux { 871 groups = "pwm_d_x3"; 872 function = "pwm_d"; 873 bias-disable; 874 }; 875 }; 876 877 pwm_d_x6_pins: pwm-d-x6 { 878 mux { 879 groups = "pwm_d_x6"; 880 function = "pwm_d"; 881 bias-disable; 882 }; 883 }; 884 885 pwm_e_pins: pwm-e { 886 mux { 887 groups = "pwm_e"; 888 function = "pwm_e"; 889 bias-disable; 890 }; 891 }; 892 893 pwm_f_x_pins: pwm-f-x { 894 mux { 895 groups = "pwm_f_x"; 896 function = "pwm_f"; 897 bias-disable; 898 }; 899 }; 900 901 pwm_f_h_pins: pwm-f-h { 902 mux { 903 groups = "pwm_f_h"; 904 function = "pwm_f"; 905 bias-disable; 906 }; 907 }; 908 909 sdcard_c_pins: sdcard_c { 910 mux-0 { 911 groups = "sdcard_d0_c", 912 "sdcard_d1_c", 913 "sdcard_d2_c", 914 "sdcard_d3_c", 915 "sdcard_cmd_c"; 916 function = "sdcard"; 917 bias-pull-up; 918 drive-strength-microamp = <4000>; 919 }; 920 921 mux-1 { 922 groups = "sdcard_clk_c"; 923 function = "sdcard"; 924 bias-disable; 925 drive-strength-microamp = <4000>; 926 }; 927 }; 928 929 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 930 mux { 931 groups = "GPIOC_4"; 932 function = "gpio_periphs"; 933 bias-pull-down; 934 drive-strength-microamp = <4000>; 935 }; 936 }; 937 938 sdcard_z_pins: sdcard_z { 939 mux-0 { 940 groups = "sdcard_d0_z", 941 "sdcard_d1_z", 942 "sdcard_d2_z", 943 "sdcard_d3_z", 944 "sdcard_cmd_z"; 945 function = "sdcard"; 946 bias-pull-up; 947 drive-strength-microamp = <4000>; 948 }; 949 950 mux-1 { 951 groups = "sdcard_clk_z"; 952 function = "sdcard"; 953 bias-disable; 954 drive-strength-microamp = <4000>; 955 }; 956 }; 957 958 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 959 mux { 960 groups = "GPIOZ_6"; 961 function = "gpio_periphs"; 962 bias-pull-down; 963 drive-strength-microamp = <4000>; 964 }; 965 }; 966 967 sdio_pins: sdio { 968 mux { 969 groups = "sdio_d0", 970 "sdio_d1", 971 "sdio_d2", 972 "sdio_d3", 973 "sdio_clk", 974 "sdio_cmd"; 975 function = "sdio"; 976 bias-disable; 977 drive-strength-microamp = <4000>; 978 }; 979 }; 980 981 sdio_clk_gate_pins: sdio_clk_gate { 982 mux { 983 groups = "GPIOX_4"; 984 function = "gpio_periphs"; 985 bias-pull-down; 986 drive-strength-microamp = <4000>; 987 }; 988 }; 989 990 spdif_in_a10_pins: spdif-in-a10 { 991 mux { 992 groups = "spdif_in_a10"; 993 function = "spdif_in"; 994 bias-disable; 995 }; 996 }; 997 998 spdif_in_a12_pins: spdif-in-a12 { 999 mux { 1000 groups = "spdif_in_a12"; 1001 function = "spdif_in"; 1002 bias-disable; 1003 }; 1004 }; 1005 1006 spdif_in_h_pins: spdif-in-h { 1007 mux { 1008 groups = "spdif_in_h"; 1009 function = "spdif_in"; 1010 bias-disable; 1011 }; 1012 }; 1013 1014 spdif_out_h_pins: spdif-out-h { 1015 mux { 1016 groups = "spdif_out_h"; 1017 function = "spdif_out"; 1018 drive-strength-microamp = <500>; 1019 bias-disable; 1020 }; 1021 }; 1022 1023 spdif_out_a11_pins: spdif-out-a11 { 1024 mux { 1025 groups = "spdif_out_a11"; 1026 function = "spdif_out"; 1027 drive-strength-microamp = <500>; 1028 bias-disable; 1029 }; 1030 }; 1031 1032 spdif_out_a13_pins: spdif-out-a13 { 1033 mux { 1034 groups = "spdif_out_a13"; 1035 function = "spdif_out"; 1036 drive-strength-microamp = <500>; 1037 bias-disable; 1038 }; 1039 }; 1040 1041 spicc0_x_pins: spicc0-x { 1042 mux { 1043 groups = "spi0_mosi_x", 1044 "spi0_miso_x", 1045 "spi0_clk_x"; 1046 function = "spi0"; 1047 drive-strength-microamp = <4000>; 1048 bias-disable; 1049 }; 1050 }; 1051 1052 spicc0_ss0_x_pins: spicc0-ss0-x { 1053 mux { 1054 groups = "spi0_ss0_x"; 1055 function = "spi0"; 1056 drive-strength-microamp = <4000>; 1057 bias-disable; 1058 }; 1059 }; 1060 1061 spicc0_c_pins: spicc0-c { 1062 mux { 1063 groups = "spi0_mosi_c", 1064 "spi0_miso_c", 1065 "spi0_ss0_c", 1066 "spi0_clk_c"; 1067 function = "spi0"; 1068 drive-strength-microamp = <4000>; 1069 bias-disable; 1070 }; 1071 }; 1072 1073 spicc1_pins: spicc1 { 1074 mux { 1075 groups = "spi1_mosi", 1076 "spi1_miso", 1077 "spi1_clk"; 1078 function = "spi1"; 1079 drive-strength-microamp = <4000>; 1080 }; 1081 }; 1082 1083 spicc1_ss0_pins: spicc1-ss0 { 1084 mux { 1085 groups = "spi1_ss0"; 1086 function = "spi1"; 1087 drive-strength-microamp = <4000>; 1088 bias-disable; 1089 }; 1090 }; 1091 1092 tdm_a_din0_pins: tdm-a-din0 { 1093 mux { 1094 groups = "tdm_a_din0"; 1095 function = "tdm_a"; 1096 bias-disable; 1097 }; 1098 }; 1099 1100 1101 tdm_a_din1_pins: tdm-a-din1 { 1102 mux { 1103 groups = "tdm_a_din1"; 1104 function = "tdm_a"; 1105 bias-disable; 1106 }; 1107 }; 1108 1109 tdm_a_dout0_pins: tdm-a-dout0 { 1110 mux { 1111 groups = "tdm_a_dout0"; 1112 function = "tdm_a"; 1113 bias-disable; 1114 drive-strength-microamp = <3000>; 1115 }; 1116 }; 1117 1118 tdm_a_dout1_pins: tdm-a-dout1 { 1119 mux { 1120 groups = "tdm_a_dout1"; 1121 function = "tdm_a"; 1122 bias-disable; 1123 drive-strength-microamp = <3000>; 1124 }; 1125 }; 1126 1127 tdm_a_fs_pins: tdm-a-fs { 1128 mux { 1129 groups = "tdm_a_fs"; 1130 function = "tdm_a"; 1131 bias-disable; 1132 drive-strength-microamp = <3000>; 1133 }; 1134 }; 1135 1136 tdm_a_sclk_pins: tdm-a-sclk { 1137 mux { 1138 groups = "tdm_a_sclk"; 1139 function = "tdm_a"; 1140 bias-disable; 1141 drive-strength-microamp = <3000>; 1142 }; 1143 }; 1144 1145 tdm_a_slv_fs_pins: tdm-a-slv-fs { 1146 mux { 1147 groups = "tdm_a_slv_fs"; 1148 function = "tdm_a"; 1149 bias-disable; 1150 }; 1151 }; 1152 1153 1154 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 1155 mux { 1156 groups = "tdm_a_slv_sclk"; 1157 function = "tdm_a"; 1158 bias-disable; 1159 }; 1160 }; 1161 1162 tdm_b_din0_pins: tdm-b-din0 { 1163 mux { 1164 groups = "tdm_b_din0"; 1165 function = "tdm_b"; 1166 bias-disable; 1167 }; 1168 }; 1169 1170 tdm_b_din1_pins: tdm-b-din1 { 1171 mux { 1172 groups = "tdm_b_din1"; 1173 function = "tdm_b"; 1174 bias-disable; 1175 }; 1176 }; 1177 1178 tdm_b_din2_pins: tdm-b-din2 { 1179 mux { 1180 groups = "tdm_b_din2"; 1181 function = "tdm_b"; 1182 bias-disable; 1183 }; 1184 }; 1185 1186 tdm_b_din3_a_pins: tdm-b-din3-a { 1187 mux { 1188 groups = "tdm_b_din3_a"; 1189 function = "tdm_b"; 1190 bias-disable; 1191 }; 1192 }; 1193 1194 tdm_b_din3_h_pins: tdm-b-din3-h { 1195 mux { 1196 groups = "tdm_b_din3_h"; 1197 function = "tdm_b"; 1198 bias-disable; 1199 }; 1200 }; 1201 1202 tdm_b_dout0_pins: tdm-b-dout0 { 1203 mux { 1204 groups = "tdm_b_dout0"; 1205 function = "tdm_b"; 1206 bias-disable; 1207 drive-strength-microamp = <3000>; 1208 }; 1209 }; 1210 1211 tdm_b_dout1_pins: tdm-b-dout1 { 1212 mux { 1213 groups = "tdm_b_dout1"; 1214 function = "tdm_b"; 1215 bias-disable; 1216 drive-strength-microamp = <3000>; 1217 }; 1218 }; 1219 1220 tdm_b_dout2_pins: tdm-b-dout2 { 1221 mux { 1222 groups = "tdm_b_dout2"; 1223 function = "tdm_b"; 1224 bias-disable; 1225 drive-strength-microamp = <3000>; 1226 }; 1227 }; 1228 1229 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1230 mux { 1231 groups = "tdm_b_dout3_a"; 1232 function = "tdm_b"; 1233 bias-disable; 1234 drive-strength-microamp = <3000>; 1235 }; 1236 }; 1237 1238 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1239 mux { 1240 groups = "tdm_b_dout3_h"; 1241 function = "tdm_b"; 1242 bias-disable; 1243 drive-strength-microamp = <3000>; 1244 }; 1245 }; 1246 1247 tdm_b_fs_pins: tdm-b-fs { 1248 mux { 1249 groups = "tdm_b_fs"; 1250 function = "tdm_b"; 1251 bias-disable; 1252 drive-strength-microamp = <3000>; 1253 }; 1254 }; 1255 1256 tdm_b_sclk_pins: tdm-b-sclk { 1257 mux { 1258 groups = "tdm_b_sclk"; 1259 function = "tdm_b"; 1260 bias-disable; 1261 drive-strength-microamp = <3000>; 1262 }; 1263 }; 1264 1265 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1266 mux { 1267 groups = "tdm_b_slv_fs"; 1268 function = "tdm_b"; 1269 bias-disable; 1270 }; 1271 }; 1272 1273 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1274 mux { 1275 groups = "tdm_b_slv_sclk"; 1276 function = "tdm_b"; 1277 bias-disable; 1278 }; 1279 }; 1280 1281 tdm_c_din0_a_pins: tdm-c-din0-a { 1282 mux { 1283 groups = "tdm_c_din0_a"; 1284 function = "tdm_c"; 1285 bias-disable; 1286 }; 1287 }; 1288 1289 tdm_c_din0_z_pins: tdm-c-din0-z { 1290 mux { 1291 groups = "tdm_c_din0_z"; 1292 function = "tdm_c"; 1293 bias-disable; 1294 }; 1295 }; 1296 1297 tdm_c_din1_a_pins: tdm-c-din1-a { 1298 mux { 1299 groups = "tdm_c_din1_a"; 1300 function = "tdm_c"; 1301 bias-disable; 1302 }; 1303 }; 1304 1305 tdm_c_din1_z_pins: tdm-c-din1-z { 1306 mux { 1307 groups = "tdm_c_din1_z"; 1308 function = "tdm_c"; 1309 bias-disable; 1310 }; 1311 }; 1312 1313 tdm_c_din2_a_pins: tdm-c-din2-a { 1314 mux { 1315 groups = "tdm_c_din2_a"; 1316 function = "tdm_c"; 1317 bias-disable; 1318 }; 1319 }; 1320 1321 eth_leds_pins: eth-leds { 1322 mux { 1323 groups = "eth_link_led", 1324 "eth_act_led"; 1325 function = "eth"; 1326 bias-disable; 1327 }; 1328 }; 1329 1330 eth_pins: eth { 1331 mux { 1332 groups = "eth_mdio", 1333 "eth_mdc", 1334 "eth_rgmii_rx_clk", 1335 "eth_rx_dv", 1336 "eth_rxd0", 1337 "eth_rxd1", 1338 "eth_txen", 1339 "eth_txd0", 1340 "eth_txd1"; 1341 function = "eth"; 1342 drive-strength-microamp = <4000>; 1343 bias-disable; 1344 }; 1345 }; 1346 1347 eth_rgmii_pins: eth-rgmii { 1348 mux { 1349 groups = "eth_rxd2_rgmii", 1350 "eth_rxd3_rgmii", 1351 "eth_rgmii_tx_clk", 1352 "eth_txd2_rgmii", 1353 "eth_txd3_rgmii"; 1354 function = "eth"; 1355 drive-strength-microamp = <4000>; 1356 bias-disable; 1357 }; 1358 }; 1359 1360 tdm_c_din2_z_pins: tdm-c-din2-z { 1361 mux { 1362 groups = "tdm_c_din2_z"; 1363 function = "tdm_c"; 1364 bias-disable; 1365 }; 1366 }; 1367 1368 tdm_c_din3_a_pins: tdm-c-din3-a { 1369 mux { 1370 groups = "tdm_c_din3_a"; 1371 function = "tdm_c"; 1372 bias-disable; 1373 }; 1374 }; 1375 1376 tdm_c_din3_z_pins: tdm-c-din3-z { 1377 mux { 1378 groups = "tdm_c_din3_z"; 1379 function = "tdm_c"; 1380 bias-disable; 1381 }; 1382 }; 1383 1384 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1385 mux { 1386 groups = "tdm_c_dout0_a"; 1387 function = "tdm_c"; 1388 bias-disable; 1389 drive-strength-microamp = <3000>; 1390 }; 1391 }; 1392 1393 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1394 mux { 1395 groups = "tdm_c_dout0_z"; 1396 function = "tdm_c"; 1397 bias-disable; 1398 drive-strength-microamp = <3000>; 1399 }; 1400 }; 1401 1402 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1403 mux { 1404 groups = "tdm_c_dout1_a"; 1405 function = "tdm_c"; 1406 bias-disable; 1407 drive-strength-microamp = <3000>; 1408 }; 1409 }; 1410 1411 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1412 mux { 1413 groups = "tdm_c_dout1_z"; 1414 function = "tdm_c"; 1415 bias-disable; 1416 drive-strength-microamp = <3000>; 1417 }; 1418 }; 1419 1420 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1421 mux { 1422 groups = "tdm_c_dout2_a"; 1423 function = "tdm_c"; 1424 bias-disable; 1425 drive-strength-microamp = <3000>; 1426 }; 1427 }; 1428 1429 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1430 mux { 1431 groups = "tdm_c_dout2_z"; 1432 function = "tdm_c"; 1433 bias-disable; 1434 drive-strength-microamp = <3000>; 1435 }; 1436 }; 1437 1438 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1439 mux { 1440 groups = "tdm_c_dout3_a"; 1441 function = "tdm_c"; 1442 bias-disable; 1443 drive-strength-microamp = <3000>; 1444 }; 1445 }; 1446 1447 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1448 mux { 1449 groups = "tdm_c_dout3_z"; 1450 function = "tdm_c"; 1451 bias-disable; 1452 drive-strength-microamp = <3000>; 1453 }; 1454 }; 1455 1456 tdm_c_fs_a_pins: tdm-c-fs-a { 1457 mux { 1458 groups = "tdm_c_fs_a"; 1459 function = "tdm_c"; 1460 bias-disable; 1461 drive-strength-microamp = <3000>; 1462 }; 1463 }; 1464 1465 tdm_c_fs_z_pins: tdm-c-fs-z { 1466 mux { 1467 groups = "tdm_c_fs_z"; 1468 function = "tdm_c"; 1469 bias-disable; 1470 drive-strength-microamp = <3000>; 1471 }; 1472 }; 1473 1474 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1475 mux { 1476 groups = "tdm_c_sclk_a"; 1477 function = "tdm_c"; 1478 bias-disable; 1479 drive-strength-microamp = <3000>; 1480 }; 1481 }; 1482 1483 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1484 mux { 1485 groups = "tdm_c_sclk_z"; 1486 function = "tdm_c"; 1487 bias-disable; 1488 drive-strength-microamp = <3000>; 1489 }; 1490 }; 1491 1492 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1493 mux { 1494 groups = "tdm_c_slv_fs_a"; 1495 function = "tdm_c"; 1496 bias-disable; 1497 }; 1498 }; 1499 1500 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1501 mux { 1502 groups = "tdm_c_slv_fs_z"; 1503 function = "tdm_c"; 1504 bias-disable; 1505 }; 1506 }; 1507 1508 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1509 mux { 1510 groups = "tdm_c_slv_sclk_a"; 1511 function = "tdm_c"; 1512 bias-disable; 1513 }; 1514 }; 1515 1516 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1517 mux { 1518 groups = "tdm_c_slv_sclk_z"; 1519 function = "tdm_c"; 1520 bias-disable; 1521 }; 1522 }; 1523 1524 uart_a_pins: uart-a { 1525 mux { 1526 groups = "uart_a_tx", 1527 "uart_a_rx"; 1528 function = "uart_a"; 1529 bias-disable; 1530 }; 1531 }; 1532 1533 uart_a_cts_rts_pins: uart-a-cts-rts { 1534 mux { 1535 groups = "uart_a_cts", 1536 "uart_a_rts"; 1537 function = "uart_a"; 1538 bias-disable; 1539 }; 1540 }; 1541 1542 uart_b_pins: uart-b { 1543 mux { 1544 groups = "uart_b_tx", 1545 "uart_b_rx"; 1546 function = "uart_b"; 1547 bias-disable; 1548 }; 1549 }; 1550 1551 uart_c_pins: uart-c { 1552 mux { 1553 groups = "uart_c_tx", 1554 "uart_c_rx"; 1555 function = "uart_c"; 1556 bias-disable; 1557 }; 1558 }; 1559 1560 uart_c_cts_rts_pins: uart-c-cts-rts { 1561 mux { 1562 groups = "uart_c_cts", 1563 "uart_c_rts"; 1564 function = "uart_c"; 1565 bias-disable; 1566 }; 1567 }; 1568 }; 1569 }; 1570 1571 cpu_temp: temperature-sensor@34800 { 1572 compatible = "amlogic,g12a-cpu-thermal", 1573 "amlogic,g12a-thermal"; 1574 reg = <0x0 0x34800 0x0 0x50>; 1575 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 1576 clocks = <&clkc CLKID_TS>; 1577 #thermal-sensor-cells = <0>; 1578 amlogic,ao-secure = <&sec_AO>; 1579 }; 1580 1581 ddr_temp: temperature-sensor@34c00 { 1582 compatible = "amlogic,g12a-ddr-thermal", 1583 "amlogic,g12a-thermal"; 1584 reg = <0x0 0x34c00 0x0 0x50>; 1585 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; 1586 clocks = <&clkc CLKID_TS>; 1587 #thermal-sensor-cells = <0>; 1588 amlogic,ao-secure = <&sec_AO>; 1589 }; 1590 1591 usb2_phy0: phy@36000 { 1592 compatible = "amlogic,g12a-usb2-phy"; 1593 reg = <0x0 0x36000 0x0 0x2000>; 1594 clocks = <&xtal>; 1595 clock-names = "xtal"; 1596 resets = <&reset RESET_USB_PHY20>; 1597 reset-names = "phy"; 1598 #phy-cells = <0>; 1599 }; 1600 1601 dmc: bus@38000 { 1602 compatible = "simple-bus"; 1603 reg = <0x0 0x38000 0x0 0x400>; 1604 #address-cells = <2>; 1605 #size-cells = <2>; 1606 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1607 1608 canvas: video-lut@48 { 1609 compatible = "amlogic,canvas"; 1610 reg = <0x0 0x48 0x0 0x14>; 1611 }; 1612 }; 1613 1614 usb2_phy1: phy@3a000 { 1615 compatible = "amlogic,g12a-usb2-phy"; 1616 reg = <0x0 0x3a000 0x0 0x2000>; 1617 clocks = <&xtal>; 1618 clock-names = "xtal"; 1619 resets = <&reset RESET_USB_PHY21>; 1620 reset-names = "phy"; 1621 #phy-cells = <0>; 1622 }; 1623 1624 hiu: bus@3c000 { 1625 compatible = "simple-bus"; 1626 reg = <0x0 0x3c000 0x0 0x1400>; 1627 #address-cells = <2>; 1628 #size-cells = <2>; 1629 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1630 1631 hhi: system-controller@0 { 1632 compatible = "amlogic,meson-gx-hhi-sysctrl", 1633 "simple-mfd", "syscon"; 1634 reg = <0 0 0 0x400>; 1635 1636 clkc: clock-controller { 1637 compatible = "amlogic,g12a-clkc"; 1638 #clock-cells = <1>; 1639 clocks = <&xtal>; 1640 clock-names = "xtal"; 1641 }; 1642 1643 pwrc: power-controller { 1644 compatible = "amlogic,meson-g12a-pwrc"; 1645 #power-domain-cells = <1>; 1646 amlogic,ao-sysctrl = <&rti>; 1647 resets = <&reset RESET_VIU>, 1648 <&reset RESET_VENC>, 1649 <&reset RESET_VCBUS>, 1650 <&reset RESET_BT656>, 1651 <&reset RESET_RDMA>, 1652 <&reset RESET_VENCI>, 1653 <&reset RESET_VENCP>, 1654 <&reset RESET_VDAC>, 1655 <&reset RESET_VDI6>, 1656 <&reset RESET_VENCL>, 1657 <&reset RESET_VID_LOCK>; 1658 reset-names = "viu", "venc", "vcbus", "bt656", 1659 "rdma", "venci", "vencp", "vdac", 1660 "vdi6", "vencl", "vid_lock"; 1661 clocks = <&clkc CLKID_VPU>, 1662 <&clkc CLKID_VAPB>; 1663 clock-names = "vpu", "vapb"; 1664 /* 1665 * VPU clocking is provided by two identical clock paths 1666 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1667 * free mux to safely change frequency while running. 1668 * Same for VAPB but with a final gate after the glitch free mux. 1669 */ 1670 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1671 <&clkc CLKID_VPU_0>, 1672 <&clkc CLKID_VPU>, /* Glitch free mux */ 1673 <&clkc CLKID_VAPB_0_SEL>, 1674 <&clkc CLKID_VAPB_0>, 1675 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1676 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1677 <0>, /* Do Nothing */ 1678 <&clkc CLKID_VPU_0>, 1679 <&clkc CLKID_FCLK_DIV4>, 1680 <0>, /* Do Nothing */ 1681 <&clkc CLKID_VAPB_0>; 1682 assigned-clock-rates = <0>, /* Do Nothing */ 1683 <666666666>, 1684 <0>, /* Do Nothing */ 1685 <0>, /* Do Nothing */ 1686 <250000000>, 1687 <0>; /* Do Nothing */ 1688 }; 1689 }; 1690 }; 1691 1692 usb3_pcie_phy: phy@46000 { 1693 compatible = "amlogic,g12a-usb3-pcie-phy"; 1694 reg = <0x0 0x46000 0x0 0x2000>; 1695 clocks = <&clkc CLKID_PCIE_PLL>; 1696 clock-names = "ref_clk"; 1697 resets = <&reset RESET_PCIE_PHY>; 1698 reset-names = "phy"; 1699 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1700 assigned-clock-rates = <100000000>; 1701 #phy-cells = <1>; 1702 }; 1703 1704 eth_phy: mdio-multiplexer@4c000 { 1705 compatible = "amlogic,g12a-mdio-mux"; 1706 reg = <0x0 0x4c000 0x0 0xa4>; 1707 clocks = <&clkc CLKID_ETH_PHY>, 1708 <&xtal>, 1709 <&clkc CLKID_MPLL_50M>; 1710 clock-names = "pclk", "clkin0", "clkin1"; 1711 mdio-parent-bus = <&mdio0>; 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 1715 ext_mdio: mdio@0 { 1716 reg = <0>; 1717 #address-cells = <1>; 1718 #size-cells = <0>; 1719 }; 1720 1721 int_mdio: mdio@1 { 1722 reg = <1>; 1723 #address-cells = <1>; 1724 #size-cells = <0>; 1725 1726 internal_ephy: ethernet_phy@8 { 1727 compatible = "ethernet-phy-id0180.3301", 1728 "ethernet-phy-ieee802.3-c22"; 1729 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1730 reg = <8>; 1731 max-speed = <100>; 1732 }; 1733 }; 1734 }; 1735 }; 1736 1737 aobus: bus@ff800000 { 1738 compatible = "simple-bus"; 1739 reg = <0x0 0xff800000 0x0 0x100000>; 1740 #address-cells = <2>; 1741 #size-cells = <2>; 1742 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1743 1744 rti: sys-ctrl@0 { 1745 compatible = "amlogic,meson-gx-ao-sysctrl", 1746 "simple-mfd", "syscon"; 1747 reg = <0x0 0x0 0x0 0x100>; 1748 #address-cells = <2>; 1749 #size-cells = <2>; 1750 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1751 1752 clkc_AO: clock-controller { 1753 compatible = "amlogic,meson-g12a-aoclkc"; 1754 #clock-cells = <1>; 1755 #reset-cells = <1>; 1756 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1757 clock-names = "xtal", "mpeg-clk"; 1758 }; 1759 1760 ao_pinctrl: pinctrl@14 { 1761 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1762 #address-cells = <2>; 1763 #size-cells = <2>; 1764 ranges; 1765 1766 gpio_ao: bank@14 { 1767 reg = <0x0 0x14 0x0 0x8>, 1768 <0x0 0x1c 0x0 0x8>, 1769 <0x0 0x24 0x0 0x14>; 1770 reg-names = "mux", 1771 "ds", 1772 "gpio"; 1773 gpio-controller; 1774 #gpio-cells = <2>; 1775 gpio-ranges = <&ao_pinctrl 0 0 15>; 1776 }; 1777 1778 i2c_ao_sck_pins: i2c_ao_sck_pins { 1779 mux { 1780 groups = "i2c_ao_sck"; 1781 function = "i2c_ao"; 1782 bias-disable; 1783 drive-strength-microamp = <3000>; 1784 }; 1785 }; 1786 1787 i2c_ao_sda_pins: i2c_ao_sda { 1788 mux { 1789 groups = "i2c_ao_sda"; 1790 function = "i2c_ao"; 1791 bias-disable; 1792 drive-strength-microamp = <3000>; 1793 }; 1794 }; 1795 1796 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1797 mux { 1798 groups = "i2c_ao_sck_e"; 1799 function = "i2c_ao"; 1800 bias-disable; 1801 drive-strength-microamp = <3000>; 1802 }; 1803 }; 1804 1805 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1806 mux { 1807 groups = "i2c_ao_sda_e"; 1808 function = "i2c_ao"; 1809 bias-disable; 1810 drive-strength-microamp = <3000>; 1811 }; 1812 }; 1813 1814 mclk0_ao_pins: mclk0-ao { 1815 mux { 1816 groups = "mclk0_ao"; 1817 function = "mclk0_ao"; 1818 bias-disable; 1819 drive-strength-microamp = <3000>; 1820 }; 1821 }; 1822 1823 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1824 mux { 1825 groups = "tdm_ao_b_din0"; 1826 function = "tdm_ao_b"; 1827 bias-disable; 1828 }; 1829 }; 1830 1831 spdif_ao_out_pins: spdif-ao-out { 1832 mux { 1833 groups = "spdif_ao_out"; 1834 function = "spdif_ao_out"; 1835 drive-strength-microamp = <500>; 1836 bias-disable; 1837 }; 1838 }; 1839 1840 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1841 mux { 1842 groups = "tdm_ao_b_din1"; 1843 function = "tdm_ao_b"; 1844 bias-disable; 1845 }; 1846 }; 1847 1848 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1849 mux { 1850 groups = "tdm_ao_b_din2"; 1851 function = "tdm_ao_b"; 1852 bias-disable; 1853 }; 1854 }; 1855 1856 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1857 mux { 1858 groups = "tdm_ao_b_dout0"; 1859 function = "tdm_ao_b"; 1860 bias-disable; 1861 drive-strength-microamp = <3000>; 1862 }; 1863 }; 1864 1865 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1866 mux { 1867 groups = "tdm_ao_b_dout1"; 1868 function = "tdm_ao_b"; 1869 bias-disable; 1870 drive-strength-microamp = <3000>; 1871 }; 1872 }; 1873 1874 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1875 mux { 1876 groups = "tdm_ao_b_dout2"; 1877 function = "tdm_ao_b"; 1878 bias-disable; 1879 drive-strength-microamp = <3000>; 1880 }; 1881 }; 1882 1883 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1884 mux { 1885 groups = "tdm_ao_b_fs"; 1886 function = "tdm_ao_b"; 1887 bias-disable; 1888 drive-strength-microamp = <3000>; 1889 }; 1890 }; 1891 1892 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1893 mux { 1894 groups = "tdm_ao_b_sclk"; 1895 function = "tdm_ao_b"; 1896 bias-disable; 1897 drive-strength-microamp = <3000>; 1898 }; 1899 }; 1900 1901 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1902 mux { 1903 groups = "tdm_ao_b_slv_fs"; 1904 function = "tdm_ao_b"; 1905 bias-disable; 1906 }; 1907 }; 1908 1909 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1910 mux { 1911 groups = "tdm_ao_b_slv_sclk"; 1912 function = "tdm_ao_b"; 1913 bias-disable; 1914 }; 1915 }; 1916 1917 uart_ao_a_pins: uart-a-ao { 1918 mux { 1919 groups = "uart_ao_a_tx", 1920 "uart_ao_a_rx"; 1921 function = "uart_ao_a"; 1922 bias-disable; 1923 }; 1924 }; 1925 1926 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1927 mux { 1928 groups = "uart_ao_a_cts", 1929 "uart_ao_a_rts"; 1930 function = "uart_ao_a"; 1931 bias-disable; 1932 }; 1933 }; 1934 1935 pwm_a_e_pins: pwm-a-e { 1936 mux { 1937 groups = "pwm_a_e"; 1938 function = "pwm_a_e"; 1939 bias-disable; 1940 }; 1941 }; 1942 1943 pwm_ao_a_pins: pwm-ao-a { 1944 mux { 1945 groups = "pwm_ao_a"; 1946 function = "pwm_ao_a"; 1947 bias-disable; 1948 }; 1949 }; 1950 1951 pwm_ao_b_pins: pwm-ao-b { 1952 mux { 1953 groups = "pwm_ao_b"; 1954 function = "pwm_ao_b"; 1955 bias-disable; 1956 }; 1957 }; 1958 1959 pwm_ao_c_4_pins: pwm-ao-c-4 { 1960 mux { 1961 groups = "pwm_ao_c_4"; 1962 function = "pwm_ao_c"; 1963 bias-disable; 1964 }; 1965 }; 1966 1967 pwm_ao_c_6_pins: pwm-ao-c-6 { 1968 mux { 1969 groups = "pwm_ao_c_6"; 1970 function = "pwm_ao_c"; 1971 bias-disable; 1972 }; 1973 }; 1974 1975 pwm_ao_d_5_pins: pwm-ao-d-5 { 1976 mux { 1977 groups = "pwm_ao_d_5"; 1978 function = "pwm_ao_d"; 1979 bias-disable; 1980 }; 1981 }; 1982 1983 pwm_ao_d_10_pins: pwm-ao-d-10 { 1984 mux { 1985 groups = "pwm_ao_d_10"; 1986 function = "pwm_ao_d"; 1987 bias-disable; 1988 }; 1989 }; 1990 1991 pwm_ao_d_e_pins: pwm-ao-d-e { 1992 mux { 1993 groups = "pwm_ao_d_e"; 1994 function = "pwm_ao_d"; 1995 }; 1996 }; 1997 1998 remote_input_ao_pins: remote-input-ao { 1999 mux { 2000 groups = "remote_ao_input"; 2001 function = "remote_ao_input"; 2002 bias-disable; 2003 }; 2004 }; 2005 }; 2006 }; 2007 2008 vrtc: rtc@0a8 { 2009 compatible = "amlogic,meson-vrtc"; 2010 reg = <0x0 0x000a8 0x0 0x4>; 2011 }; 2012 2013 cec_AO: cec@100 { 2014 compatible = "amlogic,meson-gx-ao-cec"; 2015 reg = <0x0 0x00100 0x0 0x14>; 2016 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2017 clocks = <&clkc_AO CLKID_AO_CEC>; 2018 clock-names = "core"; 2019 status = "disabled"; 2020 }; 2021 2022 sec_AO: ao-secure@140 { 2023 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2024 reg = <0x0 0x140 0x0 0x140>; 2025 amlogic,has-chip-id; 2026 }; 2027 2028 cecb_AO: cec@280 { 2029 compatible = "amlogic,meson-g12a-ao-cec"; 2030 reg = <0x0 0x00280 0x0 0x1c>; 2031 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2032 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2033 clock-names = "oscin"; 2034 status = "disabled"; 2035 }; 2036 2037 pwm_AO_cd: pwm@2000 { 2038 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2039 reg = <0x0 0x2000 0x0 0x20>; 2040 #pwm-cells = <3>; 2041 status = "disabled"; 2042 }; 2043 2044 uart_AO: serial@3000 { 2045 compatible = "amlogic,meson-gx-uart", 2046 "amlogic,meson-ao-uart"; 2047 reg = <0x0 0x3000 0x0 0x18>; 2048 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2049 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2050 clock-names = "xtal", "pclk", "baud"; 2051 status = "disabled"; 2052 }; 2053 2054 uart_AO_B: serial@4000 { 2055 compatible = "amlogic,meson-gx-uart", 2056 "amlogic,meson-ao-uart"; 2057 reg = <0x0 0x4000 0x0 0x18>; 2058 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2059 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2060 clock-names = "xtal", "pclk", "baud"; 2061 status = "disabled"; 2062 }; 2063 2064 i2c_AO: i2c@5000 { 2065 compatible = "amlogic,meson-axg-i2c"; 2066 status = "disabled"; 2067 reg = <0x0 0x05000 0x0 0x20>; 2068 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2069 #address-cells = <1>; 2070 #size-cells = <0>; 2071 clocks = <&clkc CLKID_I2C>; 2072 }; 2073 2074 pwm_AO_ab: pwm@7000 { 2075 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2076 reg = <0x0 0x7000 0x0 0x20>; 2077 #pwm-cells = <3>; 2078 status = "disabled"; 2079 }; 2080 2081 ir: ir@8000 { 2082 compatible = "amlogic,meson-gxbb-ir"; 2083 reg = <0x0 0x8000 0x0 0x20>; 2084 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2085 status = "disabled"; 2086 }; 2087 2088 saradc: adc@9000 { 2089 compatible = "amlogic,meson-g12a-saradc", 2090 "amlogic,meson-saradc"; 2091 reg = <0x0 0x9000 0x0 0x48>; 2092 #io-channel-cells = <1>; 2093 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2094 clocks = <&xtal>, 2095 <&clkc_AO CLKID_AO_SAR_ADC>, 2096 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2097 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2098 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2099 status = "disabled"; 2100 }; 2101 }; 2102 2103 vdec: video-decoder@ff620000 { 2104 compatible = "amlogic,g12a-vdec"; 2105 reg = <0x0 0xff620000 0x0 0x10000>, 2106 <0x0 0xffd0e180 0x0 0xe4>; 2107 reg-names = "dos", "esparser"; 2108 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 2109 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 2110 interrupt-names = "vdec", "esparser"; 2111 2112 amlogic,ao-sysctrl = <&rti>; 2113 amlogic,canvas = <&canvas>; 2114 2115 clocks = <&clkc CLKID_PARSER>, 2116 <&clkc CLKID_DOS>, 2117 <&clkc CLKID_VDEC_1>, 2118 <&clkc CLKID_VDEC_HEVC>, 2119 <&clkc CLKID_VDEC_HEVCF>; 2120 clock-names = "dos_parser", "dos", "vdec_1", 2121 "vdec_hevc", "vdec_hevcf"; 2122 resets = <&reset RESET_PARSER>; 2123 reset-names = "esparser"; 2124 }; 2125 2126 vpu: vpu@ff900000 { 2127 compatible = "amlogic,meson-g12a-vpu"; 2128 reg = <0x0 0xff900000 0x0 0x100000>, 2129 <0x0 0xff63c000 0x0 0x1000>; 2130 reg-names = "vpu", "hhi"; 2131 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2132 #address-cells = <1>; 2133 #size-cells = <0>; 2134 amlogic,canvas = <&canvas>; 2135 2136 /* CVBS VDAC output port */ 2137 cvbs_vdac_port: port@0 { 2138 reg = <0>; 2139 }; 2140 2141 /* HDMI-TX output port */ 2142 hdmi_tx_port: port@1 { 2143 reg = <1>; 2144 2145 hdmi_tx_out: endpoint { 2146 remote-endpoint = <&hdmi_tx_in>; 2147 }; 2148 }; 2149 }; 2150 2151 gic: interrupt-controller@ffc01000 { 2152 compatible = "arm,gic-400"; 2153 reg = <0x0 0xffc01000 0 0x1000>, 2154 <0x0 0xffc02000 0 0x2000>, 2155 <0x0 0xffc04000 0 0x2000>, 2156 <0x0 0xffc06000 0 0x2000>; 2157 interrupt-controller; 2158 interrupts = <GIC_PPI 9 2159 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2160 #interrupt-cells = <3>; 2161 #address-cells = <0>; 2162 }; 2163 2164 cbus: bus@ffd00000 { 2165 compatible = "simple-bus"; 2166 reg = <0x0 0xffd00000 0x0 0x100000>; 2167 #address-cells = <2>; 2168 #size-cells = <2>; 2169 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2170 2171 reset: reset-controller@1004 { 2172 compatible = "amlogic,meson-axg-reset"; 2173 reg = <0x0 0x1004 0x0 0x9c>; 2174 #reset-cells = <1>; 2175 }; 2176 2177 gpio_intc: interrupt-controller@f080 { 2178 compatible = "amlogic,meson-g12a-gpio-intc", 2179 "amlogic,meson-gpio-intc"; 2180 reg = <0x0 0xf080 0x0 0x10>; 2181 interrupt-controller; 2182 #interrupt-cells = <2>; 2183 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2184 }; 2185 2186 spicc0: spi@13000 { 2187 compatible = "amlogic,meson-g12a-spicc"; 2188 reg = <0x0 0x13000 0x0 0x44>; 2189 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2190 clocks = <&clkc CLKID_SPICC0>, 2191 <&clkc CLKID_SPICC0_SCLK>; 2192 clock-names = "core", "pclk"; 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 status = "disabled"; 2196 }; 2197 2198 spicc1: spi@15000 { 2199 compatible = "amlogic,meson-g12a-spicc"; 2200 reg = <0x0 0x15000 0x0 0x44>; 2201 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2202 clocks = <&clkc CLKID_SPICC1>, 2203 <&clkc CLKID_SPICC1_SCLK>; 2204 clock-names = "core", "pclk"; 2205 #address-cells = <1>; 2206 #size-cells = <0>; 2207 status = "disabled"; 2208 }; 2209 2210 spifc: spi@14000 { 2211 compatible = "amlogic,meson-gxbb-spifc"; 2212 status = "disabled"; 2213 reg = <0x0 0x14000 0x0 0x80>; 2214 #address-cells = <1>; 2215 #size-cells = <0>; 2216 clocks = <&clkc CLKID_CLK81>; 2217 }; 2218 2219 pwm_ef: pwm@19000 { 2220 compatible = "amlogic,meson-g12a-ee-pwm"; 2221 reg = <0x0 0x19000 0x0 0x20>; 2222 #pwm-cells = <3>; 2223 status = "disabled"; 2224 }; 2225 2226 pwm_cd: pwm@1a000 { 2227 compatible = "amlogic,meson-g12a-ee-pwm"; 2228 reg = <0x0 0x1a000 0x0 0x20>; 2229 #pwm-cells = <3>; 2230 status = "disabled"; 2231 }; 2232 2233 pwm_ab: pwm@1b000 { 2234 compatible = "amlogic,meson-g12a-ee-pwm"; 2235 reg = <0x0 0x1b000 0x0 0x20>; 2236 #pwm-cells = <3>; 2237 status = "disabled"; 2238 }; 2239 2240 i2c3: i2c@1c000 { 2241 compatible = "amlogic,meson-axg-i2c"; 2242 status = "disabled"; 2243 reg = <0x0 0x1c000 0x0 0x20>; 2244 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2245 #address-cells = <1>; 2246 #size-cells = <0>; 2247 clocks = <&clkc CLKID_I2C>; 2248 }; 2249 2250 i2c2: i2c@1d000 { 2251 compatible = "amlogic,meson-axg-i2c"; 2252 status = "disabled"; 2253 reg = <0x0 0x1d000 0x0 0x20>; 2254 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2255 #address-cells = <1>; 2256 #size-cells = <0>; 2257 clocks = <&clkc CLKID_I2C>; 2258 }; 2259 2260 i2c1: i2c@1e000 { 2261 compatible = "amlogic,meson-axg-i2c"; 2262 status = "disabled"; 2263 reg = <0x0 0x1e000 0x0 0x20>; 2264 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2265 #address-cells = <1>; 2266 #size-cells = <0>; 2267 clocks = <&clkc CLKID_I2C>; 2268 }; 2269 2270 i2c0: i2c@1f000 { 2271 compatible = "amlogic,meson-axg-i2c"; 2272 status = "disabled"; 2273 reg = <0x0 0x1f000 0x0 0x20>; 2274 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2275 #address-cells = <1>; 2276 #size-cells = <0>; 2277 clocks = <&clkc CLKID_I2C>; 2278 }; 2279 2280 clk_msr: clock-measure@18000 { 2281 compatible = "amlogic,meson-g12a-clk-measure"; 2282 reg = <0x0 0x18000 0x0 0x10>; 2283 }; 2284 2285 uart_C: serial@22000 { 2286 compatible = "amlogic,meson-gx-uart"; 2287 reg = <0x0 0x22000 0x0 0x18>; 2288 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2289 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2290 clock-names = "xtal", "pclk", "baud"; 2291 status = "disabled"; 2292 }; 2293 2294 uart_B: serial@23000 { 2295 compatible = "amlogic,meson-gx-uart"; 2296 reg = <0x0 0x23000 0x0 0x18>; 2297 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2298 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2299 clock-names = "xtal", "pclk", "baud"; 2300 status = "disabled"; 2301 }; 2302 2303 uart_A: serial@24000 { 2304 compatible = "amlogic,meson-gx-uart"; 2305 reg = <0x0 0x24000 0x0 0x18>; 2306 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2307 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2308 clock-names = "xtal", "pclk", "baud"; 2309 status = "disabled"; 2310 }; 2311 }; 2312 2313 sd_emmc_a: sd@ffe03000 { 2314 compatible = "amlogic,meson-axg-mmc"; 2315 reg = <0x0 0xffe03000 0x0 0x800>; 2316 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; 2317 status = "disabled"; 2318 clocks = <&clkc CLKID_SD_EMMC_A>, 2319 <&clkc CLKID_SD_EMMC_A_CLK0>, 2320 <&clkc CLKID_FCLK_DIV2>; 2321 clock-names = "core", "clkin0", "clkin1"; 2322 resets = <&reset RESET_SD_EMMC_A>; 2323 }; 2324 2325 sd_emmc_b: sd@ffe05000 { 2326 compatible = "amlogic,meson-axg-mmc"; 2327 reg = <0x0 0xffe05000 0x0 0x800>; 2328 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2329 status = "disabled"; 2330 clocks = <&clkc CLKID_SD_EMMC_B>, 2331 <&clkc CLKID_SD_EMMC_B_CLK0>, 2332 <&clkc CLKID_FCLK_DIV2>; 2333 clock-names = "core", "clkin0", "clkin1"; 2334 resets = <&reset RESET_SD_EMMC_B>; 2335 }; 2336 2337 sd_emmc_c: mmc@ffe07000 { 2338 compatible = "amlogic,meson-axg-mmc"; 2339 reg = <0x0 0xffe07000 0x0 0x800>; 2340 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2341 status = "disabled"; 2342 clocks = <&clkc CLKID_SD_EMMC_C>, 2343 <&clkc CLKID_SD_EMMC_C_CLK0>, 2344 <&clkc CLKID_FCLK_DIV2>; 2345 clock-names = "core", "clkin0", "clkin1"; 2346 resets = <&reset RESET_SD_EMMC_C>; 2347 }; 2348 2349 usb: usb@ffe09000 { 2350 status = "disabled"; 2351 compatible = "amlogic,meson-g12a-usb-ctrl"; 2352 reg = <0x0 0xffe09000 0x0 0xa0>; 2353 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2354 #address-cells = <2>; 2355 #size-cells = <2>; 2356 ranges; 2357 2358 clocks = <&clkc CLKID_USB>; 2359 resets = <&reset RESET_USB>; 2360 2361 dr_mode = "otg"; 2362 2363 phys = <&usb2_phy0>, <&usb2_phy1>, 2364 <&usb3_pcie_phy PHY_TYPE_USB3>; 2365 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2366 2367 dwc2: usb@ff400000 { 2368 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2369 reg = <0x0 0xff400000 0x0 0x40000>; 2370 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2371 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2372 clock-names = "otg"; 2373 phys = <&usb2_phy1>; 2374 phy-names = "usb2-phy"; 2375 dr_mode = "peripheral"; 2376 g-rx-fifo-size = <192>; 2377 g-np-tx-fifo-size = <128>; 2378 g-tx-fifo-size = <128 128 16 16 16>; 2379 }; 2380 2381 dwc3: usb@ff500000 { 2382 compatible = "snps,dwc3"; 2383 reg = <0x0 0xff500000 0x0 0x100000>; 2384 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2385 dr_mode = "host"; 2386 snps,dis_u2_susphy_quirk; 2387 snps,quirk-frame-length-adjustment; 2388 snps,parkmode-disable-ss-quirk; 2389 }; 2390 }; 2391 2392 mali: gpu@ffe40000 { 2393 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2394 reg = <0x0 0xffe40000 0x0 0x40000>; 2395 interrupt-parent = <&gic>; 2396 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2399 interrupt-names = "job", "mmu", "gpu"; 2400 clocks = <&clkc CLKID_MALI>; 2401 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2402 operating-points-v2 = <&gpu_opp_table>; 2403 #cooling-cells = <2>; 2404 }; 2405 }; 2406 2407 timer { 2408 compatible = "arm,armv8-timer"; 2409 interrupts = <GIC_PPI 13 2410 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2411 <GIC_PPI 14 2412 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2413 <GIC_PPI 11 2414 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2415 <GIC_PPI 10 2416 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2417 arm,no-tick-in-suspend; 2418 }; 2419 2420 xtal: xtal-clk { 2421 compatible = "fixed-clock"; 2422 clock-frequency = <24000000>; 2423 clock-output-names = "xtal"; 2424 #clock-cells = <0>; 2425 }; 2426 2427}; 2428
