Lines Matching +full:0 +full:x32000
2 &l4_cfg { /* 0x4a000000 */
4 reg = <0x4a000000 0x800>,
5 <0x4a000800 0x800>,
6 <0x4a001000 0x1000>;
10 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
11 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
12 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
13 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
14 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
15 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
16 <0x00300000 0x4a300000 0x080000>; /* segment 6 */
18 segment@0 { /* 0x4a000000 */
22 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
23 <0x00001000 0x00001000 0x001000>, /* ap 1 */
24 <0x00000800 0x00000800 0x000800>, /* ap 2 */
25 <0x00002000 0x00002000 0x001000>, /* ap 3 */
26 <0x00003000 0x00003000 0x001000>, /* ap 4 */
27 <0x00004000 0x00004000 0x001000>, /* ap 5 */
28 <0x00005000 0x00005000 0x001000>, /* ap 6 */
29 <0x00056000 0x00056000 0x001000>, /* ap 7 */
30 <0x00057000 0x00057000 0x001000>, /* ap 8 */
31 <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
32 <0x00058000 0x00058000 0x004000>, /* ap 10 */
33 <0x00062000 0x00062000 0x001000>, /* ap 11 */
34 <0x00063000 0x00063000 0x001000>, /* ap 12 */
35 <0x00008000 0x00008000 0x002000>, /* ap 23 */
36 <0x0000a000 0x0000a000 0x001000>, /* ap 24 */
37 <0x00066000 0x00066000 0x001000>, /* ap 25 */
38 <0x00067000 0x00067000 0x001000>, /* ap 26 */
39 <0x0005e000 0x0005e000 0x002000>, /* ap 80 */
40 <0x00060000 0x00060000 0x001000>, /* ap 81 */
41 <0x00064000 0x00064000 0x001000>, /* ap 86 */
42 <0x00065000 0x00065000 0x001000>; /* ap 87 */
44 target-module@2000 { /* 0x4a002000, ap 3 06.0 */
47 reg = <0x2000 0x4>,
48 <0x2010 0x4>;
57 ranges = <0x0 0x2000 0x1000>;
59 omap4_scm_core: scm@0 {
61 reg = <0x0 0x1000>;
64 ranges = <0 0 0x1000>;
66 scm_conf: scm_conf@0 {
68 reg = <0x0 0x800>;
75 reg = <0x300 0x4>;
81 reg = <0x33c 0x4>;
87 target-module@4000 { /* 0x4a004000, ap 5 02.0 */
89 reg = <0x4000 0x4>;
93 ranges = <0x0 0x4000 0x1000>;
95 cm1: cm1@0 {
97 reg = <0x0 0x2000>;
100 ranges = <0 0 0x2000>;
104 #size-cells = <0>;
112 target-module@8000 { /* 0x4a008000, ap 23 32.0 */
114 reg = <0x8000 0x4>;
118 ranges = <0x0 0x8000 0x2000>;
120 cm2: cm2@0 {
122 reg = <0x0 0x2000>;
125 ranges = <0 0 0x2000>;
129 #size-cells = <0>;
137 target-module@56000 { /* 0x4a056000, ap 7 0a.0 */
139 reg = <0x56000 0x4>,
140 <0x5602c 0x4>,
141 <0x56028 0x4>;
155 clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>;
159 ranges = <0x0 0x56000 0x1000>;
161 sdma: dma-controller@0 {
163 reg = <0x0 0x1000>;
174 target-module@58000 { /* 0x4a058000, ap 10 0e.0 */
176 reg = <0x58000 0x4>,
177 <0x58010 0x4>,
178 <0x58014 0x4>;
193 clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
197 ranges = <0x0 0x58000 0x5000>;
199 hsi: hsi@0 {
201 reg = <0x0 0x4000>,
202 <0x5000 0x1000>;
205 clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
213 ranges = <0 0 0x4000>;
217 reg = <0x2000 0x800>,
218 <0x2800 0x800>;
225 reg = <0x3000 0x800>,
226 <0x3800 0x800>;
233 target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */
238 ranges = <0x0 0x5e000 0x2000>;
241 target-module@62000 { /* 0x4a062000, ap 11 16.0 */
243 reg = <0x62000 0x4>,
244 <0x62010 0x4>,
245 <0x62014 0x4>;
255 clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>;
259 ranges = <0x0 0x62000 0x1000>;
261 usbhstll: usbhstll@0 {
263 reg = <0x0 0x1000>;
268 target-module@64000 { /* 0x4a064000, ap 86 1e.0 */
270 reg = <0x64000 0x4>,
271 <0x64010 0x4>,
272 <0x64014 0x4>;
284 clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>;
288 ranges = <0x0 0x64000 0x1000>;
290 usbhshost: usbhshost@0 {
292 reg = <0x0 0x800>;
295 ranges = <0 0 0x1000>;
305 reg = <0x800 0x400>;
312 reg = <0xc00 0x400>;
318 target-module@66000 { /* 0x4a066000, ap 25 26.0 */
320 reg = <0x66000 0x4>,
321 <0x66010 0x4>,
322 <0x66014 0x4>;
331 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
337 ranges = <0x0 0x66000 0x1000>;
339 mmu_dsp: mmu@0 {
341 reg = <0x0 0x100>;
343 #iommu-cells = <0>;
348 segment@80000 { /* 0x4a080000 */
352 ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
353 <0x0005a000 0x000da000 0x001000>, /* ap 14 */
354 <0x0005b000 0x000db000 0x001000>, /* ap 15 */
355 <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
356 <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
357 <0x0005e000 0x000de000 0x001000>, /* ap 18 */
358 <0x00060000 0x000e0000 0x001000>, /* ap 19 */
359 <0x00061000 0x000e1000 0x001000>, /* ap 20 */
360 <0x00074000 0x000f4000 0x001000>, /* ap 27 */
361 <0x00075000 0x000f5000 0x001000>, /* ap 28 */
362 <0x00076000 0x000f6000 0x001000>, /* ap 29 */
363 <0x00077000 0x000f7000 0x001000>, /* ap 30 */
364 <0x00036000 0x000b6000 0x001000>, /* ap 69 */
365 <0x00037000 0x000b7000 0x001000>, /* ap 70 */
366 <0x0004d000 0x000cd000 0x001000>, /* ap 78 */
367 <0x0004e000 0x000ce000 0x001000>, /* ap 79 */
368 <0x00029000 0x000a9000 0x001000>, /* ap 82 */
369 <0x0002a000 0x000aa000 0x001000>, /* ap 83 */
370 <0x0002b000 0x000ab000 0x001000>, /* ap 84 */
371 <0x0002c000 0x000ac000 0x001000>, /* ap 85 */
372 <0x0002d000 0x000ad000 0x001000>, /* ap 88 */
373 <0x0002e000 0x000ae000 0x001000>; /* ap 89 */
375 target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */
380 ranges = <0x0 0x29000 0x1000>;
383 target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
385 reg = <0x2b400 0x4>,
386 <0x2b404 0x4>,
387 <0x2b408 0x4>;
401 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
405 ranges = <0x0 0x2b000 0x1000>;
407 usb_otg_hs: usb_otg_hs@0 {
409 reg = <0x0 0x7ff>;
422 target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */
424 reg = <0x2d000 0x4>,
425 <0x2d010 0x4>,
426 <0x2d014 0x4>;
435 clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>;
439 ranges = <0x0 0x2d000 0x1000>;
441 ocp2scp@0 {
443 reg = <0x0 0x1f>;
446 ranges = <0 0 0x1000>;
449 reg = <0x80 0x58>;
453 #phy-cells = <0>;
459 target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */
461 reg = <0x36000 0x4>,
462 <0x36010 0x4>,
463 <0x36014 0x4>;
472 clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
476 ranges = <0x0 0x36000 0x1000>;
480 target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */
482 reg = <0x4d000 0x4>,
483 <0x4d010 0x4>,
484 <0x4d014 0x4>;
493 clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
497 ranges = <0x0 0x4d000 0x1000>;
500 target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */
502 reg = <0x59038 0x4>;
510 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>;
514 ranges = <0x0 0x59000 0x1000>;
516 smartreflex_mpu: smartreflex@0 {
518 reg = <0x0 0x80>;
523 target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */
525 reg = <0x5b038 0x4>;
533 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>;
537 ranges = <0x0 0x5b000 0x1000>;
539 smartreflex_iva: smartreflex@0 {
541 reg = <0x0 0x80>;
546 target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */
548 reg = <0x5d038 0x4>;
556 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>;
560 ranges = <0x0 0x5d000 0x1000>;
562 smartreflex_core: smartreflex@0 {
564 reg = <0x0 0x80>;
569 target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */
574 ranges = <0x0 0x60000 0x1000>;
577 target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */
579 reg = <0x74000 0x4>,
580 <0x74010 0x4>;
587 clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>;
591 ranges = <0x0 0x74000 0x1000>;
593 mailbox: mailbox@0 {
595 reg = <0x0 0x200>;
601 ti,mbox-tx = <0 0 0>;
602 ti,mbox-rx = <1 0 0>;
605 ti,mbox-tx = <3 0 0>;
606 ti,mbox-rx = <2 0 0>;
611 target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */
613 reg = <0x76000 0x4>,
614 <0x76010 0x4>,
615 <0x76014 0x4>;
626 clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>;
630 ranges = <0x0 0x76000 0x1000>;
632 hwspinlock: spinlock@0 {
634 reg = <0x0 0x1000>;
640 segment@100000 { /* 0x4a100000 */
644 ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */
645 <0x00001000 0x00101000 0x001000>, /* ap 22 */
646 <0x00002000 0x00102000 0x001000>, /* ap 61 */
647 <0x00003000 0x00103000 0x001000>, /* ap 62 */
648 <0x00008000 0x00108000 0x001000>, /* ap 63 */
649 <0x00009000 0x00109000 0x001000>, /* ap 64 */
650 <0x0000a000 0x0010a000 0x001000>, /* ap 65 */
651 <0x0000b000 0x0010b000 0x001000>; /* ap 66 */
653 target-module@0 { /* 0x4a100000, ap 21 2a.0 */
656 reg = <0x0 0x4>,
657 <0x10 0x4>;
666 ranges = <0x0 0x0 0x1000>;
671 reg = <0x40 0x0196>;
673 #size-cells = <0>;
678 pinctrl-single,function-mask = <0x7fff>;
684 reg = <0x5a0 0x170>;
687 ranges = <0 0x5a0 0x170>;
691 reg = <0x60 0x4>;
702 target-module@2000 { /* 0x4a102000, ap 61 3c.0 */
707 ranges = <0x0 0x2000 0x1000>;
710 target-module@8000 { /* 0x4a108000, ap 63 62.0 */
715 ranges = <0x0 0x8000 0x1000>;
718 target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
720 reg = <0xa000 0x4>,
721 <0xa010 0x4>;
732 clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>;
736 ranges = <0x0 0xa000 0x1000>;
742 segment@180000 { /* 0x4a180000 */
748 segment@200000 { /* 0x4a200000 */
752 ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */
753 <0x0001f000 0x0021f000 0x001000>, /* ap 32 */
754 <0x0000a000 0x0020a000 0x001000>, /* ap 33 */
755 <0x0000b000 0x0020b000 0x001000>, /* ap 34 */
756 <0x00004000 0x00204000 0x001000>, /* ap 35 */
757 <0x00005000 0x00205000 0x001000>, /* ap 36 */
758 <0x00006000 0x00206000 0x001000>, /* ap 37 */
759 <0x00007000 0x00207000 0x001000>, /* ap 38 */
760 <0x00012000 0x00212000 0x001000>, /* ap 39 */
761 <0x00013000 0x00213000 0x001000>, /* ap 40 */
762 <0x0000c000 0x0020c000 0x001000>, /* ap 41 */
763 <0x0000d000 0x0020d000 0x001000>, /* ap 42 */
764 <0x00010000 0x00210000 0x001000>, /* ap 43 */
765 <0x00011000 0x00211000 0x001000>, /* ap 44 */
766 <0x00016000 0x00216000 0x001000>, /* ap 45 */
767 <0x00017000 0x00217000 0x001000>, /* ap 46 */
768 <0x00014000 0x00214000 0x001000>, /* ap 47 */
769 <0x00015000 0x00215000 0x001000>, /* ap 48 */
770 <0x00018000 0x00218000 0x001000>, /* ap 49 */
771 <0x00019000 0x00219000 0x001000>, /* ap 50 */
772 <0x00020000 0x00220000 0x001000>, /* ap 51 */
773 <0x00021000 0x00221000 0x001000>, /* ap 52 */
774 <0x00026000 0x00226000 0x001000>, /* ap 53 */
775 <0x00027000 0x00227000 0x001000>, /* ap 54 */
776 <0x00028000 0x00228000 0x001000>, /* ap 55 */
777 <0x00029000 0x00229000 0x001000>, /* ap 56 */
778 <0x0002a000 0x0022a000 0x001000>, /* ap 57 */
779 <0x0002b000 0x0022b000 0x001000>, /* ap 58 */
780 <0x0001c000 0x0021c000 0x001000>, /* ap 59 */
781 <0x0001d000 0x0021d000 0x001000>; /* ap 60 */
783 target-module@4000 { /* 0x4a204000, ap 35 42.0 */
788 ranges = <0x0 0x4000 0x1000>;
791 target-module@6000 { /* 0x4a206000, ap 37 4a.0 */
796 ranges = <0x0 0x6000 0x1000>;
799 target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */
804 ranges = <0x0 0xa000 0x1000>;
807 target-module@c000 { /* 0x4a20c000, ap 41 20.0 */
812 ranges = <0x0 0xc000 0x1000>;
815 target-module@10000 { /* 0x4a210000, ap 43 52.0 */
820 ranges = <0x0 0x10000 0x1000>;
823 target-module@12000 { /* 0x4a212000, ap 39 18.0 */
828 ranges = <0x0 0x12000 0x1000>;
831 target-module@14000 { /* 0x4a214000, ap 47 30.0 */
836 ranges = <0x0 0x14000 0x1000>;
839 target-module@16000 { /* 0x4a216000, ap 45 28.0 */
844 ranges = <0x0 0x16000 0x1000>;
847 target-module@18000 { /* 0x4a218000, ap 49 38.0 */
852 ranges = <0x0 0x18000 0x1000>;
855 target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */
860 ranges = <0x0 0x1c000 0x1000>;
863 target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */
868 ranges = <0x0 0x1e000 0x1000>;
871 target-module@20000 { /* 0x4a220000, ap 51 40.0 */
876 ranges = <0x0 0x20000 0x1000>;
879 target-module@26000 { /* 0x4a226000, ap 53 34.0 */
884 ranges = <0x0 0x26000 0x1000>;
887 target-module@28000 { /* 0x4a228000, ap 55 2e.0 */
892 ranges = <0x0 0x28000 0x1000>;
895 target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */
900 ranges = <0x0 0x2a000 0x1000>;
904 segment@280000 { /* 0x4a280000 */
910 l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */
914 ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
915 <0x00040000 0x00340000 0x001000>, /* ap 68 */
916 <0x00020000 0x00320000 0x004000>, /* ap 71 */
917 <0x00024000 0x00324000 0x002000>, /* ap 72 */
918 <0x00026000 0x00326000 0x001000>, /* ap 73 */
919 <0x00027000 0x00327000 0x001000>, /* ap 74 */
920 <0x00028000 0x00328000 0x001000>, /* ap 75 */
921 <0x00029000 0x00329000 0x001000>, /* ap 76 */
922 <0x00030000 0x00330000 0x010000>, /* ap 77 */
923 <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
924 <0x0002c000 0x0032c000 0x004000>; /* ap 91 */
926 l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */
931 ranges = <0x00000000 0x00000000 0x00020000>,
932 <0x00020000 0x00020000 0x00004000>,
933 <0x00024000 0x00024000 0x00002000>,
934 <0x00026000 0x00026000 0x00001000>,
935 <0x00027000 0x00027000 0x00001000>,
936 <0x00028000 0x00028000 0x00001000>,
937 <0x00029000 0x00029000 0x00001000>,
938 <0x0002a000 0x0002a000 0x00002000>,
939 <0x0002c000 0x0002c000 0x00004000>,
940 <0x00030000 0x00030000 0x00010000>;
945 &l4_wkup { /* 0x4a300000 */
947 reg = <0x4a300000 0x800>,
948 <0x4a300800 0x800>,
949 <0x4a301000 0x1000>;
953 ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */
954 <0x00010000 0x4a310000 0x010000>, /* segment 1 */
955 <0x00020000 0x4a320000 0x010000>; /* segment 2 */
957 segment@0 { /* 0x4a300000 */
961 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
962 <0x00001000 0x00001000 0x001000>, /* ap 1 */
963 <0x00000800 0x00000800 0x000800>, /* ap 2 */
964 <0x00006000 0x00006000 0x002000>, /* ap 3 */
965 <0x00008000 0x00008000 0x001000>, /* ap 4 */
966 <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
967 <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
968 <0x00004000 0x00004000 0x001000>, /* ap 17 */
969 <0x00005000 0x00005000 0x001000>, /* ap 18 */
970 <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
971 <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
973 target-module@4000 { /* 0x4a304000, ap 17 24.0 */
975 reg = <0x4000 0x4>,
976 <0x4004 0x4>;
981 clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>;
985 ranges = <0x0 0x4000 0x1000>;
987 counter32k: counter@0 {
989 reg = <0x0 0x20>;
993 target-module@6000 { /* 0x4a306000, ap 3 08.0 */
995 reg = <0x6000 0x4>;
999 ranges = <0x0 0x6000 0x2000>;
1001 prm: prm@0 {
1003 reg = <0x0 0x2000>;
1007 ranges = <0 0 0x2000>;
1011 #size-cells = <0>;
1019 target-module@a000 { /* 0x4a30a000, ap 15 34.0 */
1021 reg = <0xa000 0x4>;
1025 ranges = <0x0 0xa000 0x1000>;
1027 scrm: scrm@0 {
1029 reg = <0x0 0x2000>;
1033 #size-cells = <0>;
1041 target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */
1044 reg = <0xc000 0x4>,
1045 <0xc010 0x4>;
1054 ranges = <0x0 0xc000 0x1000>;
1058 reg = <0xc000 0x1000>;
1063 segment@10000 { /* 0x4a310000 */
1067 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
1068 <0x00001000 0x00011000 0x001000>, /* ap 6 */
1069 <0x00004000 0x00014000 0x001000>, /* ap 7 */
1070 <0x00005000 0x00015000 0x001000>, /* ap 8 */
1071 <0x00008000 0x00018000 0x001000>, /* ap 9 */
1072 <0x00009000 0x00019000 0x001000>, /* ap 10 */
1073 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
1074 <0x0000d000 0x0001d000 0x001000>, /* ap 12 */
1075 <0x0000e000 0x0001e000 0x001000>, /* ap 21 */
1076 <0x0000f000 0x0001f000 0x001000>; /* ap 22 */
1078 gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */
1080 reg = <0x0 0x4>,
1081 <0x10 0x4>,
1082 <0x114 0x4>;
1093 clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>,
1098 ranges = <0x0 0x0 0x1000>;
1100 gpio1: gpio@0 {
1102 reg = <0x0 0x200>;
1112 target-module@4000 { /* 0x4a314000, ap 7 18.0 */
1114 reg = <0x4000 0x4>,
1115 <0x4010 0x4>,
1116 <0x4014 0x4>;
1126 clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>;
1130 ranges = <0x0 0x4000 0x1000>;
1132 wdt2: wdt@0 {
1134 reg = <0x0 0x80>;
1139 timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
1141 reg = <0x8000 0x4>,
1142 <0x8010 0x4>,
1143 <0x8014 0x4>;
1155 clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>;
1159 ranges = <0x0 0x8000 0x1000>;
1161 timer1: timer@0 {
1163 reg = <0x0 0x80>;
1172 target-module@c000 { /* 0x4a31c000, ap 11 20.0 */
1174 reg = <0xc000 0x4>,
1175 <0xc010 0x4>,
1176 <0xc014 0x4>;
1188 clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>;
1192 ranges = <0x0 0xc000 0x1000>;
1194 keypad: keypad@0 {
1196 reg = <0x0 0x80>;
1202 target-module@e000 { /* 0x4a31e000, ap 21 30.0 */
1205 reg = <0xe000 0x4>,
1206 <0xe010 0x4>;
1215 ranges = <0x0 0xe000 0x1000>;
1220 reg = <0x40 0x0038>;
1222 #size-cells = <0>;
1227 pinctrl-single,function-mask = <0x7fff>;
1232 segment@20000 { /* 0x4a320000 */
1236 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
1237 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
1238 <0x00000000 0x00020000 0x001000>, /* ap 23 */
1239 <0x00001000 0x00021000 0x001000>, /* ap 24 */
1240 <0x00002000 0x00022000 0x001000>, /* ap 25 */
1241 <0x00003000 0x00023000 0x001000>, /* ap 26 */
1242 <0x00004000 0x00024000 0x001000>, /* ap 27 */
1243 <0x00005000 0x00025000 0x001000>, /* ap 28 */
1244 <0x00007000 0x00027000 0x000400>, /* ap 29 */
1245 <0x00008000 0x00028000 0x000800>, /* ap 30 */
1246 <0x00009000 0x00029000 0x000400>; /* ap 31 */
1248 target-module@0 { /* 0x4a320000, ap 23 04.0 */
1253 ranges = <0x0 0x0 0x1000>;
1256 target-module@2000 { /* 0x4a322000, ap 25 0c.0 */
1261 ranges = <0x0 0x2000 0x1000>;
1264 target-module@4000 { /* 0x4a324000, ap 27 10.0 */
1269 ranges = <0x0 0x4000 0x1000>;
1272 target-module@6000 { /* 0x4a326000, ap 13 28.0 */
1277 ranges = <0x00000000 0x00006000 0x00001000>,
1278 <0x00001000 0x00007000 0x00000400>,
1279 <0x00002000 0x00008000 0x00000800>,
1280 <0x00003000 0x00009000 0x00000400>;
1285 &l4_per { /* 0x48000000 */
1287 reg = <0x48000000 0x800>,
1288 <0x48000800 0x800>,
1289 <0x48001000 0x400>,
1290 <0x48001400 0x400>,
1291 <0x48001800 0x400>,
1292 <0x48001c00 0x400>;
1296 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1297 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1299 segment@0 { /* 0x48000000 */
1303 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1304 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1305 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1306 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1307 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1308 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1309 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1310 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1311 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1312 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1313 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1314 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1315 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1316 <0x00040000 0x00040000 0x010000>, /* ap 13 */
1317 <0x00050000 0x00050000 0x001000>, /* ap 14 */
1318 <0x00055000 0x00055000 0x001000>, /* ap 15 */
1319 <0x00056000 0x00056000 0x001000>, /* ap 16 */
1320 <0x00057000 0x00057000 0x001000>, /* ap 17 */
1321 <0x00058000 0x00058000 0x001000>, /* ap 18 */
1322 <0x00059000 0x00059000 0x001000>, /* ap 19 */
1323 <0x0005a000 0x0005a000 0x001000>, /* ap 20 */
1324 <0x0005b000 0x0005b000 0x001000>, /* ap 21 */
1325 <0x0005c000 0x0005c000 0x001000>, /* ap 22 */
1326 <0x0005d000 0x0005d000 0x001000>, /* ap 23 */
1327 <0x0005e000 0x0005e000 0x001000>, /* ap 24 */
1328 <0x00060000 0x00060000 0x001000>, /* ap 25 */
1329 <0x0006a000 0x0006a000 0x001000>, /* ap 26 */
1330 <0x0006b000 0x0006b000 0x001000>, /* ap 27 */
1331 <0x0006c000 0x0006c000 0x001000>, /* ap 28 */
1332 <0x0006d000 0x0006d000 0x001000>, /* ap 29 */
1333 <0x0006e000 0x0006e000 0x001000>, /* ap 30 */
1334 <0x0006f000 0x0006f000 0x001000>, /* ap 31 */
1335 <0x00070000 0x00070000 0x001000>, /* ap 32 */
1336 <0x00071000 0x00071000 0x001000>, /* ap 33 */
1337 <0x00072000 0x00072000 0x001000>, /* ap 34 */
1338 <0x00073000 0x00073000 0x001000>, /* ap 35 */
1339 <0x00061000 0x00061000 0x001000>, /* ap 36 */
1340 <0x00096000 0x00096000 0x001000>, /* ap 37 */
1341 <0x00097000 0x00097000 0x001000>, /* ap 38 */
1342 <0x00076000 0x00076000 0x001000>, /* ap 39 */
1343 <0x00077000 0x00077000 0x001000>, /* ap 40 */
1344 <0x00078000 0x00078000 0x001000>, /* ap 41 */
1345 <0x00079000 0x00079000 0x001000>, /* ap 42 */
1346 <0x00086000 0x00086000 0x001000>, /* ap 43 */
1347 <0x00087000 0x00087000 0x001000>, /* ap 44 */
1348 <0x00088000 0x00088000 0x001000>, /* ap 45 */
1349 <0x00089000 0x00089000 0x001000>, /* ap 46 */
1350 <0x000b0000 0x000b0000 0x001000>, /* ap 47 */
1351 <0x000b1000 0x000b1000 0x001000>, /* ap 48 */
1352 <0x00098000 0x00098000 0x001000>, /* ap 49 */
1353 <0x00099000 0x00099000 0x001000>, /* ap 50 */
1354 <0x0009a000 0x0009a000 0x001000>, /* ap 51 */
1355 <0x0009b000 0x0009b000 0x001000>, /* ap 52 */
1356 <0x0009c000 0x0009c000 0x001000>, /* ap 53 */
1357 <0x0009d000 0x0009d000 0x001000>, /* ap 54 */
1358 <0x0009e000 0x0009e000 0x001000>, /* ap 55 */
1359 <0x0009f000 0x0009f000 0x001000>, /* ap 56 */
1360 <0x00090000 0x00090000 0x002000>, /* ap 57 */
1361 <0x00092000 0x00092000 0x001000>, /* ap 58 */
1362 <0x000a4000 0x000a4000 0x001000>, /* ap 59 */
1363 <0x000a6000 0x000a6000 0x001000>, /* ap 60 */
1364 <0x000a8000 0x000a8000 0x004000>, /* ap 61 */
1365 <0x000ac000 0x000ac000 0x001000>, /* ap 62 */
1366 <0x000ad000 0x000ad000 0x001000>, /* ap 63 */
1367 <0x000ae000 0x000ae000 0x001000>, /* ap 64 */
1368 <0x000b2000 0x000b2000 0x001000>, /* ap 65 */
1369 <0x000b3000 0x000b3000 0x001000>, /* ap 66 */
1370 <0x000b4000 0x000b4000 0x001000>, /* ap 67 */
1371 <0x000b5000 0x000b5000 0x001000>, /* ap 68 */
1372 <0x000b8000 0x000b8000 0x001000>, /* ap 69 */
1373 <0x000b9000 0x000b9000 0x001000>, /* ap 70 */
1374 <0x000ba000 0x000ba000 0x001000>, /* ap 71 */
1375 <0x000bb000 0x000bb000 0x001000>, /* ap 72 */
1376 <0x000d1000 0x000d1000 0x001000>, /* ap 73 */
1377 <0x000d2000 0x000d2000 0x001000>, /* ap 74 */
1378 <0x000d5000 0x000d5000 0x001000>, /* ap 75 */
1379 <0x000d6000 0x000d6000 0x001000>, /* ap 76 */
1380 <0x000a2000 0x000a2000 0x001000>, /* ap 79 */
1381 <0x000a3000 0x000a3000 0x001000>, /* ap 80 */
1382 <0x00001400 0x00001400 0x000400>, /* ap 81 */
1383 <0x00001800 0x00001800 0x000400>, /* ap 82 */
1384 <0x00001c00 0x00001c00 0x000400>, /* ap 83 */
1385 <0x000a5000 0x000a5000 0x001000>; /* ap 84 */
1387 target-module@20000 { /* 0x48020000, ap 3 06.0 */
1389 reg = <0x20050 0x4>,
1390 <0x20054 0x4>,
1391 <0x20058 0x4>;
1402 clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>;
1406 ranges = <0x0 0x20000 0x1000>;
1408 uart3: serial@0 {
1410 reg = <0x0 0x100>;
1416 target-module@32000 { /* 0x48032000, ap 5 02.0 */
1418 reg = <0x32000 0x4>,
1419 <0x32010 0x4>,
1420 <0x32014 0x4>;
1432 clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>;
1436 ranges = <0x0 0x32000 0x1000>;
1438 timer2: timer@0 {
1440 reg = <0x0 0x80>;
1448 target-module@34000 { /* 0x48034000, ap 7 04.0 */
1450 reg = <0x34000 0x4>,
1451 <0x34010 0x4>;
1460 clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>;
1464 ranges = <0x0 0x34000 0x1000>;
1466 timer3: timer@0 {
1468 reg = <0x0 0x80>;
1476 target-module@36000 { /* 0x48036000, ap 9 0e.0 */
1478 reg = <0x36000 0x4>,
1479 <0x36010 0x4>;
1488 clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>;
1492 ranges = <0x0 0x36000 0x1000>;
1494 timer4: timer@0 {
1496 reg = <0x0 0x80>;
1504 target-module@3e000 { /* 0x4803e000, ap 11 08.0 */
1506 reg = <0x3e000 0x4>,
1507 <0x3e010 0x4>;
1516 clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>;
1520 ranges = <0x0 0x3e000 0x1000>;
1522 timer9: timer@0 {
1524 reg = <0x0 0x80>;
1534 target-module@40000 { /* 0x48040000, ap 13 0a.0 */
1539 ranges = <0x0 0x40000 0x10000>;
1542 target-module@55000 { /* 0x48055000, ap 15 0c.0 */
1544 reg = <0x55000 0x4>,
1545 <0x55010 0x4>,
1546 <0x55114 0x4>;
1557 clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>,
1562 ranges = <0x0 0x55000 0x1000>;
1564 gpio2: gpio@0 {
1566 reg = <0x0 0x200>;
1575 target-module@57000 { /* 0x48057000, ap 17 16.0 */
1577 reg = <0x57000 0x4>,
1578 <0x57010 0x4>,
1579 <0x57114 0x4>;
1590 clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>,
1595 ranges = <0x0 0x57000 0x1000>;
1597 gpio3: gpio@0 {
1599 reg = <0x0 0x200>;
1608 target-module@59000 { /* 0x48059000, ap 19 10.0 */
1610 reg = <0x59000 0x4>,
1611 <0x59010 0x4>,
1612 <0x59114 0x4>;
1623 clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>,
1628 ranges = <0x0 0x59000 0x1000>;
1630 gpio4: gpio@0 {
1632 reg = <0x0 0x200>;
1641 target-module@5b000 { /* 0x4805b000, ap 21 12.0 */
1643 reg = <0x5b000 0x4>,
1644 <0x5b010 0x4>,
1645 <0x5b114 0x4>;
1656 clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>,
1661 ranges = <0x0 0x5b000 0x1000>;
1663 gpio5: gpio@0 {
1665 reg = <0x0 0x200>;
1674 target-module@5d000 { /* 0x4805d000, ap 23 14.0 */
1676 reg = <0x5d000 0x4>,
1677 <0x5d010 0x4>,
1678 <0x5d114 0x4>;
1689 clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>,
1694 ranges = <0x0 0x5d000 0x1000>;
1696 gpio6: gpio@0 {
1698 reg = <0x0 0x200>;
1707 target-module@60000 { /* 0x48060000, ap 25 1e.0 */
1709 reg = <0x60000 0x8>,
1710 <0x60010 0x8>,
1711 <0x60090 0x8>;
1723 clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>;
1727 ranges = <0x0 0x60000 0x1000>;
1729 i2c3: i2c@0 {
1731 reg = <0x0 0x100>;
1734 #size-cells = <0>;
1738 target-module@6a000 { /* 0x4806a000, ap 26 18.0 */
1740 reg = <0x6a050 0x4>,
1741 <0x6a054 0x4>,
1742 <0x6a058 0x4>;
1753 clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>;
1757 ranges = <0x0 0x6a000 0x1000>;
1759 uart1: serial@0 {
1761 reg = <0x0 0x100>;
1767 target-module@6c000 { /* 0x4806c000, ap 28 20.0 */
1769 reg = <0x6c050 0x4>,
1770 <0x6c054 0x4>,
1771 <0x6c058 0x4>;
1782 clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>;
1786 ranges = <0x0 0x6c000 0x1000>;
1788 uart2: serial@0 {
1790 reg = <0x0 0x100>;
1796 target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */
1798 reg = <0x6e050 0x4>,
1799 <0x6e054 0x4>,
1800 <0x6e058 0x4>;
1811 clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>;
1815 ranges = <0x0 0x6e000 0x1000>;
1817 uart4: serial@0 {
1819 reg = <0x0 0x100>;
1825 target-module@70000 { /* 0x48070000, ap 32 28.0 */
1827 reg = <0x70000 0x8>,
1828 <0x70010 0x8>,
1829 <0x70090 0x8>;
1841 clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>;
1845 ranges = <0x0 0x70000 0x1000>;
1847 i2c1: i2c@0 {
1849 reg = <0x0 0x100>;
1852 #size-cells = <0>;
1856 target-module@72000 { /* 0x48072000, ap 34 30.0 */
1858 reg = <0x72000 0x8>,
1859 <0x72010 0x8>,
1860 <0x72090 0x8>;
1872 clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>;
1876 ranges = <0x0 0x72000 0x1000>;
1878 i2c2: i2c@0 {
1880 reg = <0x0 0x100>;
1883 #size-cells = <0>;
1887 target-module@76000 { /* 0x48076000, ap 39 38.0 */
1889 reg = <0x76000 0x4>,
1890 <0x76010 0x4>;
1898 clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>;
1902 ranges = <0x0 0x76000 0x1000>;
1907 target-module@78000 { /* 0x48078000, ap 41 1a.0 */
1909 reg = <0x78000 0x4>,
1910 <0x78010 0x4>,
1911 <0x78014 0x4>;
1921 clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>;
1925 ranges = <0x0 0x78000 0x1000>;
1927 elm: elm@0 {
1929 reg = <0x0 0x2000>;
1935 target-module@86000 { /* 0x48086000, ap 43 24.0 */
1937 reg = <0x86000 0x4>,
1938 <0x86010 0x4>,
1939 <0x86014 0x4>;
1951 clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>;
1955 ranges = <0x0 0x86000 0x1000>;
1957 timer10: timer@0 {
1959 reg = <0x0 0x80>;
1968 target-module@88000 { /* 0x48088000, ap 45 2e.0 */
1970 reg = <0x88000 0x4>,
1971 <0x88010 0x4>;
1980 clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>;
1984 ranges = <0x0 0x88000 0x1000>;
1986 timer11: timer@0 {
1988 reg = <0x0 0x80>;
1997 rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */
1999 reg = <0x91fe0 0x4>,
2000 <0x91fe4 0x4>;
2006 clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>;
2010 ranges = <0x0 0x90000 0x2000>;
2012 rng: rng@0 {
2014 reg = <0x0 0x2000>;
2019 target-module@96000 { /* 0x48096000, ap 37 26.0 */
2021 reg = <0x9608c 0x4>;
2030 clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>;
2034 ranges = <0x0 0x96000 0x1000>;
2036 mcbsp4: mcbsp@0 {
2038 reg = <0x0 0xff>; /* L4 Interconnect */
2050 target-module@98000 { /* 0x48098000, ap 49 22.0 */
2052 reg = <0x98000 0x4>,
2053 <0x98010 0x4>;
2062 clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>;
2066 ranges = <0x0 0x98000 0x1000>;
2068 mcspi1: spi@0 {
2070 reg = <0x0 0x200>;
2073 #size-cells = <0>;
2088 target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */
2090 reg = <0x9a000 0x4>,
2091 <0x9a010 0x4>;
2100 clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>;
2104 ranges = <0x0 0x9a000 0x1000>;
2106 mcspi2: spi@0 {
2108 reg = <0x0 0x200>;
2111 #size-cells = <0>;
2121 target-module@9c000 { /* 0x4809c000, ap 53 36.0 */
2123 reg = <0x9c000 0x4>,
2124 <0x9c010 0x4>;
2137 clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>;
2141 ranges = <0x0 0x9c000 0x1000>;
2143 mmc1: mmc@0 {
2145 reg = <0x0 0x400>;
2155 target-module@9e000 { /* 0x4809e000, ap 55 48.0 */
2160 ranges = <0x0 0x9e000 0x1000>;
2163 target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */
2168 ranges = <0x0 0xa2000 0x1000>;
2171 target-module@a4000 { /* 0x480a4000, ap 59 34.0 */
2176 ranges = <0x00000000 0x000a4000 0x00001000>,
2177 <0x00001000 0x000a5000 0x00001000>;
2180 des_target: target-module@a5000 { /* 0x480a5000 */
2182 reg = <0xa5030 0x4>,
2183 <0xa5034 0x4>,
2184 <0xa5038 0x4>;
2194 clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>;
2198 ranges = <0 0xa5000 0x00001000>;
2200 des: des@0 {
2202 reg = <0 0xa0>;
2209 target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
2214 ranges = <0x0 0xa8000 0x4000>;
2217 target-module@ad000 { /* 0x480ad000, ap 63 50.0 */
2219 reg = <0xad000 0x4>,
2220 <0xad010 0x4>;
2233 clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>;
2237 ranges = <0x0 0xad000 0x1000>;
2239 mmc3: mmc@0 {
2241 reg = <0x0 0x400>;
2249 target-module@b0000 { /* 0x480b0000, ap 47 40.0 */
2254 ranges = <0x0 0xb0000 0x1000>;
2257 target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */
2259 reg = <0xb2000 0x4>,
2260 <0xb2014 0x4>,
2261 <0xb2018 0x4>;
2268 clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>;
2272 ranges = <0x0 0xb2000 0x1000>;
2274 hdqw1w: 1w@0 {
2276 reg = <0x0 0x1000>;
2281 target-module@b4000 { /* 0x480b4000, ap 67 46.0 */
2283 reg = <0xb4000 0x4>,
2284 <0xb4010 0x4>;
2297 clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>;
2301 ranges = <0x0 0xb4000 0x1000>;
2303 mmc2: mmc@0 {
2305 reg = <0x0 0x400>;
2313 target-module@b8000 { /* 0x480b8000, ap 69 58.0 */
2315 reg = <0xb8000 0x4>,
2316 <0xb8010 0x4>;
2325 clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>;
2329 ranges = <0x0 0xb8000 0x1000>;
2331 mcspi3: spi@0 {
2333 reg = <0x0 0x200>;
2336 #size-cells = <0>;
2343 target-module@ba000 { /* 0x480ba000, ap 71 32.0 */
2345 reg = <0xba000 0x4>,
2346 <0xba010 0x4>;
2355 clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>;
2359 ranges = <0x0 0xba000 0x1000>;
2361 mcspi4: spi@0 {
2363 reg = <0x0 0x200>;
2366 #size-cells = <0>;
2373 target-module@d1000 { /* 0x480d1000, ap 73 44.0 */
2375 reg = <0xd1000 0x4>,
2376 <0xd1010 0x4>;
2389 clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>;
2393 ranges = <0x0 0xd1000 0x1000>;
2395 mmc4: mmc@0 {
2397 reg = <0x0 0x400>;
2405 target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */
2407 reg = <0xd5000 0x4>,
2408 <0xd5010 0x4>;
2421 clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>;
2425 ranges = <0x0 0xd5000 0x1000>;
2427 mmc5: mmc@0 {
2429 reg = <0x0 0x400>;
2438 segment@200000 { /* 0x48200000 */
2442 ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */
2443 <0x00151000 0x00351000 0x001000>; /* ap 78 */
2445 target-module@150000 { /* 0x48350000, ap 77 4c.0 */
2447 reg = <0x150000 0x8>,
2448 <0x150010 0x8>,
2449 <0x150090 0x8>;
2461 clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>;
2465 ranges = <0x0 0x150000 0x1000>;
2467 i2c4: i2c@0 {
2469 reg = <0x0 0x100>;
2472 #size-cells = <0>;