Lines Matching +full:0 +full:x32000
1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
10 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
11 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
12 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
13 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
14 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
15 <0x00300000 0x4a300000 0x080000>; /* segment 6 */
17 segment@0 { /* 0x4a000000 */
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
22 <0x00001000 0x00001000 0x001000>, /* ap 1 */
23 <0x00000800 0x00000800 0x000800>, /* ap 2 */
24 <0x00002000 0x00002000 0x001000>, /* ap 3 */
25 <0x00003000 0x00003000 0x001000>, /* ap 4 */
26 <0x00004000 0x00004000 0x001000>, /* ap 5 */
27 <0x00005000 0x00005000 0x001000>, /* ap 6 */
28 <0x00056000 0x00056000 0x001000>, /* ap 7 */
29 <0x00057000 0x00057000 0x001000>, /* ap 8 */
30 <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
31 <0x00058000 0x00058000 0x001000>, /* ap 10 */
32 <0x00062000 0x00062000 0x001000>, /* ap 11 */
33 <0x00063000 0x00063000 0x001000>, /* ap 12 */
34 <0x00008000 0x00008000 0x002000>, /* ap 21 */
35 <0x0000a000 0x0000a000 0x001000>, /* ap 22 */
36 <0x00066000 0x00066000 0x001000>, /* ap 23 */
37 <0x00067000 0x00067000 0x001000>, /* ap 24 */
38 <0x0005e000 0x0005e000 0x002000>, /* ap 69 */
39 <0x00060000 0x00060000 0x001000>, /* ap 70 */
40 <0x00064000 0x00064000 0x001000>, /* ap 71 */
41 <0x00065000 0x00065000 0x001000>, /* ap 72 */
42 <0x0005a000 0x0005a000 0x001000>, /* ap 77 */
43 <0x0005b000 0x0005b000 0x001000>, /* ap 78 */
44 <0x00070000 0x00070000 0x004000>, /* ap 79 */
45 <0x00074000 0x00074000 0x001000>, /* ap 80 */
46 <0x00075000 0x00075000 0x001000>, /* ap 81 */
47 <0x00076000 0x00076000 0x001000>, /* ap 82 */
48 <0x00020000 0x00020000 0x020000>, /* ap 109 */
49 <0x00040000 0x00040000 0x001000>, /* ap 110 */
50 <0x00059000 0x00059000 0x001000>; /* ap 111 */
52 target-module@2000 { /* 0x4a002000, ap 3 44.0 */
54 reg = <0x2000 0x4>;
58 ranges = <0x0 0x2000 0x1000>;
60 scm_core: scm@0 {
62 reg = <0x0 0x1000>;
65 ranges = <0 0 0x800>;
67 scm_conf: scm_conf@0 {
69 reg = <0x0 0x800>;
80 ranges = <0 0x800 0x800>;
85 reg = <0x40 0x01b6>;
87 #size-cells = <0>;
92 pinctrl-single,function-mask = <0x7fff>;
98 reg = <0x5a0 0xec>;
101 ranges = <0 0x5a0 0xec>;
105 reg = <0x60 0x4>;
117 target-module@4000 { /* 0x4a004000, ap 5 5c.0 */
119 reg = <0x4000 0x4>;
123 ranges = <0x0 0x4000 0x1000>;
125 cm_core_aon: cm_core_aon@0 {
128 reg = <0x0 0x2000>;
131 ranges = <0 0 0x1000>;
135 #size-cells = <0>;
143 target-module@8000 { /* 0x4a008000, ap 21 4c.0 */
145 reg = <0x8000 0x4>;
149 ranges = <0x0 0x8000 0x2000>;
151 cm_core: cm_core@0 {
153 reg = <0x0 0x2000>;
156 ranges = <0 0 0x2000>;
160 #size-cells = <0>;
168 target-module@20000 { /* 0x4a020000, ap 109 08.0 */
170 reg = <0x20000 0x4>,
171 <0x20010 0x4>;
183 clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>;
187 ranges = <0x0 0x20000 0x20000>;
189 usb3: omap_dwc3@0 {
191 reg = <0x0 0x10000>;
196 ranges = <0 0 0x20000>;
199 reg = <0x10000 0x10000>;
213 target-module@56000 { /* 0x4a056000, ap 7 02.0 */
215 reg = <0x56000 0x4>,
216 <0x5602c 0x4>,
217 <0x56028 0x4>;
231 clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>;
235 ranges = <0x0 0x56000 0x1000>;
237 sdma: dma-controller@0 {
239 reg = <0x0 0x1000>;
250 target-module@58000 { /* 0x4a058000, ap 10 06.0 */
255 ranges = <0x00000000 0x00058000 0x00001000>,
256 <0x00001000 0x00059000 0x00001000>,
257 <0x00002000 0x0005a000 0x00001000>,
258 <0x00003000 0x0005b000 0x00001000>;
261 target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */
266 ranges = <0x0 0x5e000 0x2000>;
269 target-module@62000 { /* 0x4a062000, ap 11 0e.0 */
271 reg = <0x62000 0x4>,
272 <0x62010 0x4>,
273 <0x62014 0x4>;
284 clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>;
288 ranges = <0x0 0x62000 0x1000>;
290 usbhstll: usbhstll@0 {
292 reg = <0x0 0x1000>;
297 target-module@64000 { /* 0x4a064000, ap 71 1e.0 */
299 reg = <0x64000 0x4>,
300 <0x64010 0x4>;
312 clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>;
316 ranges = <0x0 0x64000 0x1000>;
318 usbhshost: usbhshost@0 {
320 reg = <0x0 0x800>;
323 ranges = <0 0 0x1000>;
333 reg = <0x800 0x400>;
340 reg = <0xc00 0x400>;
346 target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
348 reg = <0x66000 0x4>,
349 <0x66010 0x4>,
350 <0x66014 0x4>;
360 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
366 ranges = <0x0 0x66000 0x1000>;
368 mmu_dsp: mmu@0 {
370 reg = <0x0 0x100>;
372 #iommu-cells = <0>;
376 target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
381 ranges = <0x0 0x70000 0x4000>;
384 target-module@75000 { /* 0x4a075000, ap 81 32.0 */
389 ranges = <0x0 0x75000 0x1000>;
393 segment@80000 { /* 0x4a080000 */
397 ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
398 <0x0005a000 0x000da000 0x001000>, /* ap 14 */
399 <0x0005b000 0x000db000 0x001000>, /* ap 15 */
400 <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
401 <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
402 <0x0005e000 0x000de000 0x001000>, /* ap 18 */
403 <0x00060000 0x000e0000 0x001000>, /* ap 19 */
404 <0x00061000 0x000e1000 0x001000>, /* ap 20 */
405 <0x00074000 0x000f4000 0x001000>, /* ap 25 */
406 <0x00075000 0x000f5000 0x001000>, /* ap 26 */
407 <0x00076000 0x000f6000 0x001000>, /* ap 27 */
408 <0x00077000 0x000f7000 0x001000>, /* ap 28 */
409 <0x00036000 0x000b6000 0x001000>, /* ap 65 */
410 <0x00037000 0x000b7000 0x001000>, /* ap 66 */
411 <0x0004d000 0x000cd000 0x001000>, /* ap 67 */
412 <0x0004e000 0x000ce000 0x001000>, /* ap 68 */
413 <0x00000000 0x00080000 0x004000>, /* ap 83 */
414 <0x00004000 0x00084000 0x001000>, /* ap 84 */
415 <0x00005000 0x00085000 0x001000>, /* ap 85 */
416 <0x00006000 0x00086000 0x001000>, /* ap 86 */
417 <0x00007000 0x00087000 0x001000>, /* ap 87 */
418 <0x00008000 0x00088000 0x001000>, /* ap 88 */
419 <0x00010000 0x00090000 0x004000>, /* ap 89 */
420 <0x00014000 0x00094000 0x001000>, /* ap 90 */
421 <0x00015000 0x00095000 0x001000>, /* ap 91 */
422 <0x00016000 0x00096000 0x001000>, /* ap 92 */
423 <0x00017000 0x00097000 0x001000>, /* ap 93 */
424 <0x00018000 0x00098000 0x001000>, /* ap 94 */
425 <0x00020000 0x000a0000 0x004000>, /* ap 95 */
426 <0x00024000 0x000a4000 0x001000>, /* ap 96 */
427 <0x00025000 0x000a5000 0x001000>, /* ap 97 */
428 <0x00026000 0x000a6000 0x001000>, /* ap 98 */
429 <0x00027000 0x000a7000 0x001000>, /* ap 99 */
430 <0x00028000 0x000a8000 0x001000>; /* ap 100 */
432 target-module@0 { /* 0x4a080000, ap 83 28.0 */
434 reg = <0x0 0x4>,
435 <0x10 0x4>,
436 <0x14 0x4>;
445 clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>;
449 ranges = <0x00000000 0x00000000 0x00004000>,
450 <0x00004000 0x00004000 0x00001000>,
451 <0x00005000 0x00005000 0x00001000>,
452 <0x00006000 0x00006000 0x00001000>,
453 <0x00007000 0x00007000 0x00001000>;
455 ocp2scp@0 {
459 reg = <0 0x20>;
464 reg = <0x4000 0x7c>;
465 syscon-phy-power = <&scm_conf 0x300>;
469 #phy-cells = <0>;
474 reg = <0x4400 0x80>,
475 <0x4800 0x64>,
476 <0x4c00 0x40>;
478 syscon-phy-power = <&scm_conf 0x370>;
485 #phy-cells = <0>;
489 target-module@10000 { /* 0x4a090000, ap 89 36.0 */
491 reg = <0x10000 0x4>,
492 <0x10010 0x4>,
493 <0x10014 0x4>;
502 clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>;
506 ranges = <0x00000000 0x00010000 0x00004000>,
507 <0x00004000 0x00014000 0x00001000>,
508 <0x00005000 0x00015000 0x00001000>,
509 <0x00006000 0x00016000 0x00001000>,
510 <0x00007000 0x00017000 0x00001000>;
512 ocp2scp@0 {
516 reg = <0x0 0x20>;
521 reg = <0x6000 0x80>, /* phy_rx */
522 <0x6400 0x64>, /* phy_tx */
523 <0x6800 0x40>; /* pll_ctrl */
525 syscon-phy-power = <&scm_conf 0x374>;
529 #phy-cells = <0>;
533 target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */
538 ranges = <0x00000000 0x00020000 0x00004000>,
539 <0x00004000 0x00024000 0x00001000>,
540 <0x00005000 0x00025000 0x00001000>,
541 <0x00006000 0x00026000 0x00001000>,
542 <0x00007000 0x00027000 0x00001000>;
545 target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */
550 ranges = <0x0 0x36000 0x1000>;
553 target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */
558 ranges = <0x0 0x4d000 0x1000>;
561 target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */
566 ranges = <0x0 0x59000 0x1000>;
569 target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */
574 ranges = <0x0 0x5b000 0x1000>;
577 target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */
582 ranges = <0x0 0x5d000 0x1000>;
585 target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */
590 ranges = <0x0 0x60000 0x1000>;
593 target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */
595 reg = <0x74000 0x4>,
596 <0x74010 0x4>;
603 clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>;
607 ranges = <0x0 0x74000 0x1000>;
609 mailbox: mailbox@0 {
611 reg = <0x0 0x200>;
617 ti,mbox-tx = <0 0 0>;
618 ti,mbox-rx = <1 0 0>;
621 ti,mbox-tx = <3 0 0>;
622 ti,mbox-rx = <2 0 0>;
627 target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */
629 reg = <0x76000 0x4>,
630 <0x76010 0x4>,
631 <0x76014 0x4>;
642 clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>;
646 ranges = <0x0 0x76000 0x1000>;
648 hwspinlock: spinlock@0 {
650 reg = <0x0 0x1000>;
656 segment@100000 { /* 0x4a100000 */
660 ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */
661 <0x00003000 0x00103000 0x001000>, /* ap 60 */
662 <0x00008000 0x00108000 0x001000>, /* ap 61 */
663 <0x00009000 0x00109000 0x001000>, /* ap 62 */
664 <0x0000a000 0x0010a000 0x001000>, /* ap 63 */
665 <0x0000b000 0x0010b000 0x001000>, /* ap 64 */
666 <0x00040000 0x00140000 0x010000>, /* ap 101 */
667 <0x00050000 0x00150000 0x001000>; /* ap 102 */
669 target-module@2000 { /* 0x4a102000, ap 59 2c.0 */
674 ranges = <0x0 0x2000 0x1000>;
677 target-module@8000 { /* 0x4a108000, ap 61 26.0 */
682 ranges = <0x0 0x8000 0x1000>;
685 target-module@a000 { /* 0x4a10a000, ap 63 22.0 */
690 ranges = <0x0 0xa000 0x1000>;
693 target-module@40000 { /* 0x4a140000, ap 101 16.0 */
698 ranges = <0x0 0x40000 0x10000>;
702 segment@180000 { /* 0x4a180000 */
708 segment@200000 { /* 0x4a200000 */
712 ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */
713 <0x0001f000 0x0021f000 0x001000>, /* ap 30 */
714 <0x0000a000 0x0020a000 0x001000>, /* ap 31 */
715 <0x0000b000 0x0020b000 0x001000>, /* ap 32 */
716 <0x00006000 0x00206000 0x001000>, /* ap 33 */
717 <0x00007000 0x00207000 0x001000>, /* ap 34 */
718 <0x00004000 0x00204000 0x001000>, /* ap 35 */
719 <0x00005000 0x00205000 0x001000>, /* ap 36 */
720 <0x00012000 0x00212000 0x001000>, /* ap 37 */
721 <0x00013000 0x00213000 0x001000>, /* ap 38 */
722 <0x0000c000 0x0020c000 0x001000>, /* ap 39 */
723 <0x0000d000 0x0020d000 0x001000>, /* ap 40 */
724 <0x00010000 0x00210000 0x001000>, /* ap 41 */
725 <0x00011000 0x00211000 0x001000>, /* ap 42 */
726 <0x00016000 0x00216000 0x001000>, /* ap 43 */
727 <0x00017000 0x00217000 0x001000>, /* ap 44 */
728 <0x00014000 0x00214000 0x001000>, /* ap 45 */
729 <0x00015000 0x00215000 0x001000>, /* ap 46 */
730 <0x00018000 0x00218000 0x001000>, /* ap 47 */
731 <0x00019000 0x00219000 0x001000>, /* ap 48 */
732 <0x00020000 0x00220000 0x001000>, /* ap 49 */
733 <0x00021000 0x00221000 0x001000>, /* ap 50 */
734 <0x00026000 0x00226000 0x001000>, /* ap 51 */
735 <0x00027000 0x00227000 0x001000>, /* ap 52 */
736 <0x00028000 0x00228000 0x001000>, /* ap 53 */
737 <0x00029000 0x00229000 0x001000>, /* ap 54 */
738 <0x0002a000 0x0022a000 0x001000>, /* ap 55 */
739 <0x0002b000 0x0022b000 0x001000>, /* ap 56 */
740 <0x0001c000 0x0021c000 0x001000>, /* ap 57 */
741 <0x0001d000 0x0021d000 0x001000>, /* ap 58 */
742 <0x0001a000 0x0021a000 0x001000>, /* ap 73 */
743 <0x0001b000 0x0021b000 0x001000>, /* ap 74 */
744 <0x00024000 0x00224000 0x001000>, /* ap 75 */
745 <0x00025000 0x00225000 0x001000>, /* ap 76 */
746 <0x00002000 0x00202000 0x001000>, /* ap 103 */
747 <0x00003000 0x00203000 0x001000>, /* ap 104 */
748 <0x00008000 0x00208000 0x001000>, /* ap 105 */
749 <0x00009000 0x00209000 0x001000>, /* ap 106 */
750 <0x00022000 0x00222000 0x001000>, /* ap 107 */
751 <0x00023000 0x00223000 0x001000>; /* ap 108 */
753 target-module@2000 { /* 0x4a202000, ap 103 3c.0 */
758 ranges = <0x0 0x2000 0x1000>;
761 target-module@4000 { /* 0x4a204000, ap 35 46.0 */
766 ranges = <0x0 0x4000 0x1000>;
769 target-module@6000 { /* 0x4a206000, ap 33 4e.0 */
774 ranges = <0x0 0x6000 0x1000>;
777 target-module@8000 { /* 0x4a208000, ap 105 34.0 */
782 ranges = <0x0 0x8000 0x1000>;
785 target-module@a000 { /* 0x4a20a000, ap 31 30.0 */
790 ranges = <0x0 0xa000 0x1000>;
793 target-module@c000 { /* 0x4a20c000, ap 39 14.0 */
798 ranges = <0x0 0xc000 0x1000>;
801 target-module@10000 { /* 0x4a210000, ap 41 56.0 */
806 ranges = <0x0 0x10000 0x1000>;
809 target-module@12000 { /* 0x4a212000, ap 37 52.0 */
814 ranges = <0x0 0x12000 0x1000>;
817 target-module@14000 { /* 0x4a214000, ap 45 1c.0 */
822 ranges = <0x0 0x14000 0x1000>;
825 target-module@16000 { /* 0x4a216000, ap 43 42.0 */
830 ranges = <0x0 0x16000 0x1000>;
833 target-module@18000 { /* 0x4a218000, ap 47 1a.0 */
838 ranges = <0x0 0x18000 0x1000>;
841 target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */
846 ranges = <0x0 0x1a000 0x1000>;
849 target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */
854 ranges = <0x0 0x1c000 0x1000>;
857 target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */
862 ranges = <0x0 0x1e000 0x1000>;
865 target-module@20000 { /* 0x4a220000, ap 49 4a.0 */
870 ranges = <0x0 0x20000 0x1000>;
873 target-module@22000 { /* 0x4a222000, ap 107 3a.0 */
878 ranges = <0x0 0x22000 0x1000>;
881 target-module@24000 { /* 0x4a224000, ap 75 48.0 */
886 ranges = <0x0 0x24000 0x1000>;
889 target-module@26000 { /* 0x4a226000, ap 51 24.0 */
894 ranges = <0x0 0x26000 0x1000>;
897 target-module@28000 { /* 0x4a228000, ap 53 38.0 */
902 ranges = <0x0 0x28000 0x1000>;
905 target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */
910 ranges = <0x0 0x2a000 0x1000>;
914 segment@280000 { /* 0x4a280000 */
920 segment@300000 { /* 0x4a300000 */
927 &l4_per { /* 0x48000000 */
929 reg = <0x48000000 0x800>,
930 <0x48000800 0x800>,
931 <0x48001000 0x400>,
932 <0x48001400 0x400>,
933 <0x48001800 0x400>,
934 <0x48001c00 0x400>;
938 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
939 <0x00200000 0x48200000 0x200000>; /* segment 1 */
941 segment@0 { /* 0x48000000 */
945 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
946 <0x00001000 0x00001000 0x000400>, /* ap 1 */
947 <0x00000800 0x00000800 0x000800>, /* ap 2 */
948 <0x00020000 0x00020000 0x001000>, /* ap 3 */
949 <0x00021000 0x00021000 0x001000>, /* ap 4 */
950 <0x00032000 0x00032000 0x001000>, /* ap 5 */
951 <0x00033000 0x00033000 0x001000>, /* ap 6 */
952 <0x00034000 0x00034000 0x001000>, /* ap 7 */
953 <0x00035000 0x00035000 0x001000>, /* ap 8 */
954 <0x00036000 0x00036000 0x001000>, /* ap 9 */
955 <0x00037000 0x00037000 0x001000>, /* ap 10 */
956 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
957 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
958 <0x00055000 0x00055000 0x001000>, /* ap 13 */
959 <0x00056000 0x00056000 0x001000>, /* ap 14 */
960 <0x00057000 0x00057000 0x001000>, /* ap 15 */
961 <0x00058000 0x00058000 0x001000>, /* ap 16 */
962 <0x00059000 0x00059000 0x001000>, /* ap 17 */
963 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
964 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
965 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
966 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
967 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
968 <0x00060000 0x00060000 0x001000>, /* ap 23 */
969 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
970 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
971 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
972 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
973 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
974 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
975 <0x00070000 0x00070000 0x001000>, /* ap 30 */
976 <0x00071000 0x00071000 0x001000>, /* ap 31 */
977 <0x00072000 0x00072000 0x001000>, /* ap 32 */
978 <0x00073000 0x00073000 0x001000>, /* ap 33 */
979 <0x00061000 0x00061000 0x001000>, /* ap 34 */
980 <0x00053000 0x00053000 0x001000>, /* ap 35 */
981 <0x00054000 0x00054000 0x001000>, /* ap 36 */
982 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
983 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
984 <0x00078000 0x00078000 0x001000>, /* ap 39 */
985 <0x00079000 0x00079000 0x001000>, /* ap 40 */
986 <0x00086000 0x00086000 0x001000>, /* ap 41 */
987 <0x00087000 0x00087000 0x001000>, /* ap 42 */
988 <0x00088000 0x00088000 0x001000>, /* ap 43 */
989 <0x00089000 0x00089000 0x001000>, /* ap 44 */
990 <0x00051000 0x00051000 0x001000>, /* ap 45 */
991 <0x00052000 0x00052000 0x001000>, /* ap 46 */
992 <0x00098000 0x00098000 0x001000>, /* ap 47 */
993 <0x00099000 0x00099000 0x001000>, /* ap 48 */
994 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
995 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
996 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
997 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
998 <0x00068000 0x00068000 0x001000>, /* ap 53 */
999 <0x00069000 0x00069000 0x001000>, /* ap 54 */
1000 <0x00090000 0x00090000 0x002000>, /* ap 55 */
1001 <0x00092000 0x00092000 0x001000>, /* ap 56 */
1002 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1003 <0x000a5000 0x000a5000 0x001000>,
1004 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1005 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1006 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1007 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1008 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1009 <0x00066000 0x00066000 0x001000>, /* ap 63 */
1010 <0x00067000 0x00067000 0x001000>, /* ap 64 */
1011 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1012 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1013 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1014 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1015 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1016 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1017 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1018 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1019 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1020 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1021 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1022 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1023 <0x00001400 0x00001400 0x000400>, /* ap 77 */
1024 <0x00001800 0x00001800 0x000400>, /* ap 78 */
1025 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1026 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1027 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1028 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1029 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1030 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1032 target-module@20000 { /* 0x48020000, ap 3 04.0 */
1034 reg = <0x20050 0x4>,
1035 <0x20054 0x4>,
1036 <0x20058 0x4>;
1047 clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>;
1051 ranges = <0x0 0x20000 0x1000>;
1053 uart3: serial@0 {
1055 reg = <0x0 0x100>;
1061 target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1063 reg = <0x32000 0x4>,
1064 <0x32010 0x4>;
1073 clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>;
1077 ranges = <0x0 0x32000 0x1000>;
1079 timer2: timer@0 {
1081 reg = <0x0 0x80>;
1089 target-module@34000 { /* 0x48034000, ap 7 46.0 */
1091 reg = <0x34000 0x4>,
1092 <0x34010 0x4>;
1101 clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>;
1105 ranges = <0x0 0x34000 0x1000>;
1107 timer3: timer@0 {
1109 reg = <0x0 0x80>;
1117 target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1119 reg = <0x36000 0x4>,
1120 <0x36010 0x4>;
1129 clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>;
1133 ranges = <0x0 0x36000 0x1000>;
1135 timer4: timer@0 {
1137 reg = <0x0 0x80>;
1145 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1147 reg = <0x3e000 0x4>,
1148 <0x3e010 0x4>;
1157 clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>;
1161 ranges = <0x0 0x3e000 0x1000>;
1163 timer9: timer@0 {
1165 reg = <0x0 0x80>;
1174 target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1176 reg = <0x51000 0x4>,
1177 <0x51010 0x4>,
1178 <0x51114 0x4>;
1189 clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>,
1194 ranges = <0x0 0x51000 0x1000>;
1196 gpio7: gpio@0 {
1198 reg = <0x0 0x200>;
1207 target-module@53000 { /* 0x48053000, ap 35 36.0 */
1209 reg = <0x53000 0x4>,
1210 <0x53010 0x4>,
1211 <0x53114 0x4>;
1222 clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>,
1227 ranges = <0x0 0x53000 0x1000>;
1229 gpio8: gpio@0 {
1231 reg = <0x0 0x200>;
1240 target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1242 reg = <0x55000 0x4>,
1243 <0x55010 0x4>,
1244 <0x55114 0x4>;
1255 clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>,
1260 ranges = <0x0 0x55000 0x1000>;
1262 gpio2: gpio@0 {
1264 reg = <0x0 0x200>;
1273 target-module@57000 { /* 0x48057000, ap 15 06.0 */
1275 reg = <0x57000 0x4>,
1276 <0x57010 0x4>,
1277 <0x57114 0x4>;
1288 clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>,
1293 ranges = <0x0 0x57000 0x1000>;
1295 gpio3: gpio@0 {
1297 reg = <0x0 0x200>;
1306 target-module@59000 { /* 0x48059000, ap 17 16.0 */
1308 reg = <0x59000 0x4>,
1309 <0x59010 0x4>,
1310 <0x59114 0x4>;
1321 clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>,
1326 ranges = <0x0 0x59000 0x1000>;
1328 gpio4: gpio@0 {
1330 reg = <0x0 0x200>;
1339 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1341 reg = <0x5b000 0x4>,
1342 <0x5b010 0x4>,
1343 <0x5b114 0x4>;
1354 clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>,
1359 ranges = <0x0 0x5b000 0x1000>;
1361 gpio5: gpio@0 {
1363 reg = <0x0 0x200>;
1372 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1374 reg = <0x5d000 0x4>,
1375 <0x5d010 0x4>,
1376 <0x5d114 0x4>;
1387 clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>,
1392 ranges = <0x0 0x5d000 0x1000>;
1394 gpio6: gpio@0 {
1396 reg = <0x0 0x200>;
1405 target-module@60000 { /* 0x48060000, ap 23 24.0 */
1407 reg = <0x60000 0x8>,
1408 <0x60010 0x8>,
1409 <0x60090 0x8>;
1421 clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>;
1425 ranges = <0x0 0x60000 0x1000>;
1427 i2c3: i2c@0 {
1429 reg = <0x0 0x100>;
1432 #size-cells = <0>;
1436 target-module@66000 { /* 0x48066000, ap 63 4c.0 */
1438 reg = <0x66050 0x4>,
1439 <0x66054 0x4>,
1440 <0x66058 0x4>;
1451 clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>;
1455 ranges = <0x0 0x66000 0x1000>;
1457 uart5: serial@0 {
1459 reg = <0x0 0x100>;
1465 target-module@68000 { /* 0x48068000, ap 53 54.0 */
1467 reg = <0x68050 0x4>,
1468 <0x68054 0x4>,
1469 <0x68058 0x4>;
1480 clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>;
1484 ranges = <0x0 0x68000 0x1000>;
1486 uart6: serial@0 {
1488 reg = <0x0 0x100>;
1494 target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */
1496 reg = <0x6a050 0x4>,
1497 <0x6a054 0x4>,
1498 <0x6a058 0x4>;
1509 clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>;
1513 ranges = <0x0 0x6a000 0x1000>;
1515 uart1: serial@0 {
1517 reg = <0x0 0x100>;
1523 target-module@6c000 { /* 0x4806c000, ap 26 22.0 */
1525 reg = <0x6c050 0x4>,
1526 <0x6c054 0x4>,
1527 <0x6c058 0x4>;
1538 clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>;
1542 ranges = <0x0 0x6c000 0x1000>;
1544 uart2: serial@0 {
1546 reg = <0x0 0x100>;
1552 target-module@6e000 { /* 0x4806e000, ap 28 44.1 */
1554 reg = <0x6e050 0x4>,
1555 <0x6e054 0x4>,
1556 <0x6e058 0x4>;
1567 clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>;
1571 ranges = <0x0 0x6e000 0x1000>;
1573 uart4: serial@0 {
1575 reg = <0x0 0x100>;
1581 target-module@70000 { /* 0x48070000, ap 30 14.0 */
1583 reg = <0x70000 0x8>,
1584 <0x70010 0x8>,
1585 <0x70090 0x8>;
1597 clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>;
1601 ranges = <0x0 0x70000 0x1000>;
1603 i2c1: i2c@0 {
1605 reg = <0x0 0x100>;
1608 #size-cells = <0>;
1612 target-module@72000 { /* 0x48072000, ap 32 1c.0 */
1614 reg = <0x72000 0x8>,
1615 <0x72010 0x8>,
1616 <0x72090 0x8>;
1628 clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>;
1632 ranges = <0x0 0x72000 0x1000>;
1634 i2c2: i2c@0 {
1636 reg = <0x0 0x100>;
1639 #size-cells = <0>;
1643 target-module@78000 { /* 0x48078000, ap 39 12.0 */
1648 ranges = <0x0 0x78000 0x1000>;
1651 target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */
1653 reg = <0x7a000 0x8>,
1654 <0x7a010 0x8>,
1655 <0x7a090 0x8>;
1667 clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>;
1671 ranges = <0x0 0x7a000 0x1000>;
1673 i2c4: i2c@0 {
1675 reg = <0x0 0x100>;
1678 #size-cells = <0>;
1682 target-module@7c000 { /* 0x4807c000, ap 83 34.0 */
1684 reg = <0x7c000 0x8>,
1685 <0x7c010 0x8>,
1686 <0x7c090 0x8>;
1698 clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>;
1702 ranges = <0x0 0x7c000 0x1000>;
1704 i2c5: i2c@0 {
1706 reg = <0x0 0x100>;
1709 #size-cells = <0>;
1713 target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1715 reg = <0x86000 0x4>,
1716 <0x86010 0x4>;
1725 clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>;
1729 ranges = <0x0 0x86000 0x1000>;
1731 timer10: timer@0 {
1733 reg = <0x0 0x80>;
1742 target-module@88000 { /* 0x48088000, ap 43 66.0 */
1744 reg = <0x88000 0x4>,
1745 <0x88010 0x4>;
1754 clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>;
1758 ranges = <0x0 0x88000 0x1000>;
1760 timer11: timer@0 {
1762 reg = <0x0 0x80>;
1771 rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */
1773 reg = <0x91fe0 0x4>,
1774 <0x91fe4 0x4>;
1780 clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
1784 ranges = <0x0 0x90000 0x2000>;
1786 rng: rng@0 {
1788 reg = <0x0 0x2000>;
1793 target-module@98000 { /* 0x48098000, ap 47 08.0 */
1795 reg = <0x98000 0x4>,
1796 <0x98010 0x4>;
1805 clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>;
1809 ranges = <0x0 0x98000 0x1000>;
1811 mcspi1: spi@0 {
1813 reg = <0x0 0x200>;
1816 #size-cells = <0>;
1831 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1833 reg = <0x9a000 0x4>,
1834 <0x9a010 0x4>;
1843 clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>;
1847 ranges = <0x0 0x9a000 0x1000>;
1849 mcspi2: spi@0 {
1851 reg = <0x0 0x200>;
1854 #size-cells = <0>;
1864 target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */
1866 reg = <0x9c000 0x4>,
1867 <0x9c010 0x4>;
1880 clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>;
1884 ranges = <0x0 0x9c000 0x1000>;
1886 mmc1: mmc@0 {
1888 reg = <0x0 0x400>;
1898 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
1903 ranges = <0x0 0xa2000 0x1000>;
1906 target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */
1911 ranges = <0x00000000 0x000a4000 0x00001000>,
1912 <0x00001000 0x000a5000 0x00001000>;
1915 des_target: target-module@a5000 { /* 0x480a5000 */
1917 reg = <0xa5030 0x4>,
1918 <0xa5034 0x4>,
1919 <0xa5038 0x4>;
1929 clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>;
1933 ranges = <0 0xa5000 0x00001000>;
1936 des: des@0 {
1938 reg = <0 0xa0>;
1945 target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */
1950 ranges = <0x0 0xa8000 0x4000>;
1953 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
1955 reg = <0xad000 0x4>,
1956 <0xad010 0x4>;
1969 clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>;
1973 ranges = <0x0 0xad000 0x1000>;
1975 mmc3: mmc@0 {
1977 reg = <0x0 0x400>;
1985 target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */
1990 ranges = <0x0 0xb2000 0x1000>;
1993 target-module@b4000 { /* 0x480b4000, ap 65 42.0 */
1995 reg = <0xb4000 0x4>,
1996 <0xb4010 0x4>;
2009 clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>;
2013 ranges = <0x0 0xb4000 0x1000>;
2015 mmc2: mmc@0 {
2017 reg = <0x0 0x400>;
2025 target-module@b8000 { /* 0x480b8000, ap 67 32.0 */
2027 reg = <0xb8000 0x4>,
2028 <0xb8010 0x4>;
2037 clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>;
2041 ranges = <0x0 0xb8000 0x1000>;
2043 mcspi3: spi@0 {
2045 reg = <0x0 0x200>;
2048 #size-cells = <0>;
2055 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2057 reg = <0xba000 0x4>,
2058 <0xba010 0x4>;
2067 clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>;
2071 ranges = <0x0 0xba000 0x1000>;
2073 mcspi4: spi@0 {
2075 reg = <0x0 0x200>;
2078 #size-cells = <0>;
2085 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2087 reg = <0xd1000 0x4>,
2088 <0xd1010 0x4>;
2101 clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>;
2105 ranges = <0x0 0xd1000 0x1000>;
2107 mmc4: mmc@0 {
2109 reg = <0x0 0x400>;
2117 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2119 reg = <0xd5000 0x4>,
2120 <0xd5010 0x4>;
2133 clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>;
2137 ranges = <0x0 0xd5000 0x1000>;
2139 mmc5: mmc@0 {
2141 reg = <0x0 0x400>;
2150 segment@200000 { /* 0x48200000 */
2157 &l4_wkup { /* 0x4ae00000 */
2159 reg = <0x4ae00000 0x800>,
2160 <0x4ae00800 0x800>,
2161 <0x4ae01000 0x1000>;
2165 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
2166 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
2167 <0x00020000 0x4ae20000 0x010000>; /* segment 2 */
2169 segment@0 { /* 0x4ae00000 */
2173 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2174 <0x00001000 0x00001000 0x001000>, /* ap 1 */
2175 <0x00000800 0x00000800 0x000800>, /* ap 2 */
2176 <0x00006000 0x00006000 0x002000>, /* ap 3 */
2177 <0x00008000 0x00008000 0x001000>, /* ap 4 */
2178 <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
2179 <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
2180 <0x00004000 0x00004000 0x001000>, /* ap 17 */
2181 <0x00005000 0x00005000 0x001000>, /* ap 18 */
2182 <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
2183 <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
2185 target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
2187 reg = <0x4000 0x4>,
2188 <0x4010 0x4>;
2193 clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>;
2197 ranges = <0x0 0x4000 0x1000>;
2199 counter32k: counter@0 {
2201 reg = <0x0 0x40>;
2205 target-module@6000 { /* 0x4ae06000, ap 3 08.0 */
2207 reg = <0x6000 0x4>;
2211 ranges = <0x0 0x6000 0x2000>;
2213 prm: prm@0 {
2215 reg = <0x0 0x2000>;
2219 ranges = <0 0 0x2000>;
2223 #size-cells = <0>;
2231 target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */
2233 reg = <0xa000 0x4>;
2237 ranges = <0x0 0xa000 0x1000>;
2239 scrm: scrm@0 {
2241 reg = <0x0 0x1000>;
2245 #size-cells = <0>;
2253 target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */
2255 reg = <0xc000 0x4>;
2259 ranges = <0x0 0xc000 0x1000>;
2264 reg = <0x840 0x003c>;
2266 #size-cells = <0>;
2271 pinctrl-single,function-mask = <0x7fff>;
2277 reg = <0xda0 0x60>;
2280 ranges = <0 0 0x60>;
2282 scm_wkup_pad_conf: scm_conf@0 {
2284 reg = <0x0 0x60>;
2287 ranges = <0 0x0 0x60>;
2289 scm_wkup_pad_conf_clocks: clocks@0 {
2291 #size-cells = <0>;
2298 segment@10000 { /* 0x4ae10000 */
2302 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
2303 <0x00001000 0x00011000 0x001000>, /* ap 6 */
2304 <0x00004000 0x00014000 0x001000>, /* ap 7 */
2305 <0x00005000 0x00015000 0x001000>, /* ap 8 */
2306 <0x00008000 0x00018000 0x001000>, /* ap 9 */
2307 <0x00009000 0x00019000 0x001000>, /* ap 10 */
2308 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
2309 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
2311 target-module@0 { /* 0x4ae10000, ap 5 10.0 */
2313 reg = <0x0 0x4>,
2314 <0x10 0x4>,
2315 <0x114 0x4>;
2326 clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>,
2331 ranges = <0x0 0x0 0x1000>;
2333 gpio1: gpio@0 {
2335 reg = <0x0 0x200>;
2345 target-module@4000 { /* 0x4ae14000, ap 7 14.0 */
2347 reg = <0x4000 0x4>,
2348 <0x4010 0x4>,
2349 <0x4014 0x4>;
2359 clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>;
2363 ranges = <0x0 0x4000 0x1000>;
2365 wdt2: wdt@0 {
2367 reg = <0x0 0x80>;
2372 timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
2374 reg = <0x8000 0x4>,
2375 <0x8010 0x4>;
2384 clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>;
2388 ranges = <0x0 0x8000 0x1000>;
2390 timer1: timer@0 {
2392 reg = <0x0 0x80>;
2401 target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */
2403 reg = <0xc000 0x4>,
2404 <0xc010 0x4>;
2412 clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>;
2416 ranges = <0x0 0xc000 0x1000>;
2418 keypad: keypad@0 {
2420 reg = <0x0 0x400>;
2425 segment@20000 { /* 0x4ae20000 */
2429 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
2430 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
2431 <0x00000000 0x00020000 0x001000>, /* ap 21 */
2432 <0x00001000 0x00021000 0x001000>, /* ap 22 */
2433 <0x00002000 0x00022000 0x001000>, /* ap 23 */
2434 <0x00003000 0x00023000 0x001000>, /* ap 24 */
2435 <0x00007000 0x00027000 0x000400>, /* ap 25 */
2436 <0x00008000 0x00028000 0x000800>, /* ap 26 */
2437 <0x00009000 0x00029000 0x000100>, /* ap 27 */
2438 <0x00008800 0x00028800 0x000200>, /* ap 28 */
2439 <0x00008a00 0x00028a00 0x000100>; /* ap 29 */
2441 target-module@0 { /* 0x4ae20000, ap 21 04.0 */
2446 ranges = <0x0 0x0 0x1000>;
2449 target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */
2454 ranges = <0x0 0x2000 0x1000>;
2457 target-module@6000 { /* 0x4ae26000, ap 13 24.0 */
2462 ranges = <0x00000000 0x00006000 0x00001000>,
2463 <0x00001000 0x00007000 0x00000400>,
2464 <0x00002000 0x00008000 0x00000800>,
2465 <0x00002800 0x00008800 0x00000200>,
2466 <0x00002a00 0x00008a00 0x00000100>,
2467 <0x00003000 0x00009000 0x00000100>;