Searched refs:uint32 (Results 1 – 25 of 204) sorted by relevance
123456789
75 #define MC_RGM_FES_SWT1_RST_MASK32 ((uint32)0x00000080U)76 #define MC_RGM_FES_SWT1_RST_MASK ((uint32)0x00000000U)77 #define MC_RGM_FERD_D_SWT1_RST_MASK ((uint32)0x00000000U)81 #define MC_RGM_FES_SWT2_RST_MASK32 ((uint32)0x00000100U)82 #define MC_RGM_FES_SWT2_RST_MASK ((uint32)0x00000000U)83 #define MC_RGM_FERD_D_SWT2_RST_MASK ((uint32)0x00000000U)87 #define MC_RGM_FES_SWT3_RST_MASK32 ((uint32)0x00000400U)88 #define MC_RGM_FES_SWT3_RST_MASK ((uint32)0x00000000U)89 #define MC_RGM_FERD_D_SWT3_RST_MASK ((uint32)0x00000000U)93 #define MC_RGM_FES_PLL_AUX_MASK32 ((uint32)0x00001000U)[all …]
80 #define PMC_LVSC_RAMP_UP_RESET_FLAGS_RWBITS_MASK32 ((uint32)0x80F30000U)81 #define PMC_LVSC_RESET_FLAGS_RWBITS_MASK32 ((uint32)0x83F30000U)82 #define PMC_LVSC_OV_UV_STATUS_FLAGS_MASK32 ((uint32)0x00001D00U)83 #define PMC_LVSC_OV_UV_IRQ_FLAGS_MASK32 ((uint32)0x0000001DU)85 #define PMC_LVSC_UV_IRQ_FLAGS_MASK32 ((uint32)0x00000010U)86 #define PMC_LVSC_OV_IRQ_FLAGS_MASK32 ((uint32)0x0000000DU)88 #define PMC_LVSC_RWBITS_MASK32 ((uint32)0x83F3001DU)89 #define PMC_LVSC_RESET_MASK32 ((uint32)0x00001000U)90 #define PMC_LVSC_RESERVED_MASK32 ((uint32)( (uint32)(~PMC_LVSC_RWBITS_MASK32…95 #define PMC_CONFIG_LVD_INTERRUPTS_ENABLE ((uint32)PMC_CONFIG_LVDIE_MASK)[all …]
277 #define GIC500_GICD_IROUTER_AFF2(x) (((uint32)(((uint32)(x)) << GIC500_GICD_IROUTER_…281 #define GIC500_GICD_IROUTER_AFF1(x) (((uint32)(((uint32)(x)) << GIC500_GICD_IROUTER_…285 #define GIC500_GICD_IROUTER_AFF0(x) (((uint32)(((uint32)(x)) << GIC500_GICD_IROUTER_…289 #define GIC500_GICD_IROUTER_IRM(x) (((uint32)(((uint32)(x)) << GIC500_GICD_IROUTER_…295 volatile uint32 CTLR; /* +0x0000 - RW - Distributor Control Register */296 … const volatile uint32 TYPER; /* +0x0004 - RO - Interrupt Controller Type Register */297 …const volatile uint32 IIDR; /* +0x0008 - RO - Distributor Implementer Identification…298 const volatile uint32 padding0[13]; /* Reserved */ 299 …volatile uint32 SETSPI_NSR; /* +0x0040 - WO - Non-Secure SPI Set Register (Used when SPI i…300 const volatile uint32 padding1; /* Reserved */[all …]
76 uint32 Frequency;131 uint32 Clock_Ip_Get_RTC_CLK_Frequency_TrustedCall(void);132 static uint32 Clock_Ip_PLL_VCO(const PLL_Type *Base);133 static uint32 Clock_Ip_Get_Zero_Frequency(void);134 static uint32 Clock_Ip_Get_FIRC_CLK_Frequency(void);135 static uint32 Clock_Ip_Get_FIRC_STANDBY_CLK_Frequency(void);136 static uint32 Clock_Ip_Get_SIRC_CLK_Frequency(void);137 static uint32 Clock_Ip_Get_SIRC_STANDBY_CLK_Frequency(void);138 static uint32 Clock_Ip_Get_FXOSC_CLK_Frequency(void);140 static uint32 Clock_Ip_Get_SXOSC_CLK_Frequency(void);[all …]
233 uint32 StartTime; in Power_Ip_PMC_PowerInit()234 uint32 ElapsedTime; in Power_Ip_PMC_PowerInit()235 uint32 TimeoutTicks; in Power_Ip_PMC_PowerInit()237 uint32 LvscValue; in Power_Ip_PMC_PowerInit()238 uint32 LastMileRegValue; in Power_Ip_PMC_PowerInit()240 uint32 ConfigValue = 0; in Power_Ip_PMC_PowerInit()256 ConfigValue &= (~(uint32)PMC_CONFIG_RWBITS_MASK); in Power_Ip_PMC_PowerInit()257 ConfigValue |= (ConfigPtr->ConfigRegister & (uint32)PMC_CONFIG_RWBITS_MASK); in Power_Ip_PMC_PowerInit()263 IP_PMC->CONFIG = (uint32)(ConfigPtr->ConfigRegister & (~(uint32)PMC_CONFIG_LMEN_MASK)); in Power_Ip_PMC_PowerInit()279 ConfigValue = (uint32)(ConfigValue & (~(uint32)PMC_CONFIG_LMEN_MASK)); in Power_Ip_PMC_PowerInit()[all …]
96 #define ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN ((uint32)1U << 0U)97 #define ADC_SAR_IP_NOTIF_FLAG_NORMAL_EOC ((uint32)1U << 1U)98 #define ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN ((uint32)1U << 2U)99 #define ADC_SAR_IP_NOTIF_FLAG_INJECTED_EOC ((uint32)1U << 3U)100 #define ADC_SAR_IP_NOTIF_FLAG_CTU_EOC ((uint32)1U << 4U)106 #define ADC_SAR_IP_STATUS_FLAG_CALIBRATED ((uint32)1U << 5U)107 #define ADC_SAR_IP_STATUS_FLAG_NORMAL_STARTED ((uint32)1U << 6U)108 #define ADC_SAR_IP_STATUS_FLAG_INJECTED_STARTED ((uint32)1U << 7U)109 #define ADC_SAR_IP_STATUS_FLAG_INJECTED_ABORTED ((uint32)1U << 8U)110 #define ADC_SAR_IP_STATUS_FLAG_CTU_STARTED ((uint32)1U << 9U)[all …]
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */74 …#define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR…76 …#define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR…78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)[all …]
47 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */49 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */52 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */54 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */59 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */61 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */69 …#define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR…71 …#define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR…73 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)77 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)[all …]
78 uint32 Frequency;168 static uint32 PLL_VCO(const PLLDIG_Type *Base);169 static uint32 LFAST_PLL_VCO(const LFAST_Type *Base);170 static uint32 DFS_OUTPUT(const DFS_Type *Base, uint32 Channel, uint32 Fin);171 static uint32 Clock_Ip_Get_Zero_Frequency(void);172 static uint32 Clock_Ip_Get_FIRC_CLK_Frequency(void);173 static uint32 Clock_Ip_Get_FXOSC_CLK_Frequency(void);174 static uint32 Clock_Ip_Get_SIRC_CLK_Frequency(void);176 static uint32 Clock_Ip_Get_FIRC_AE_CLK_Frequency(void);178 static uint32 Clock_Ip_Get_COREPLL_CLK_Frequency(void);[all …]
160 uint32 SwitchPortEgressBitMask; /*!< Port Bitmap */161 uint32 ET_EID; /*!< Egress Treatment Table Entry ID */175 uint32 PortMembershipBitmap; /*!< Port Membership Bitmap */176 uint32 VlanID; /*!< Vlan ID */178 …uint32 EgressTreatmentApplicabilityPortBitmap; /*!< Egress Treatment Applicability Port Bitma…179 uint32 BaseEgressTreatmentEntryID; /*!< Base Egress Treatment Entry ID */206 typedef uint32 Netc_EthSwt_Ip_CBDRStatusType;278 #define NETC_ETHSWT_IP_CMDBD_REQFMT_REQUEST_LENGTH(x) (((uint32)(((uint32)(x)) << …291 #define NETC_ETHSWT_IP_CMDBD_REQFMT_RESPONSE_LENGTH(x) (((uint32)(((uint32)(x)) <<…298 #define NETC_ETHSWT_IP_CMDBD_REQFMT_CONFIG_FIELD_CMD(x) (((uint32)(((uint32)(x)) <<…[all …]
91 uint32 RegValue = (uint32)BaseAddr->MCR; in Qspi_Ip_GetClrTxStatus()113 uint32 RegValue = (uint32)BaseAddr->SPTRCLR; in Qspi_Ip_GetClrAhbStatus()247 uint32 RegValue = (uint32)BaseAddr->MCR; in Qspi_Ip_SetIdleLineValuesA()250 RegValue &= (uint32)(~(QuadSPI_MCR_ISD2FA_MASK | QuadSPI_MCR_ISD3FA_MASK)); in Qspi_Ip_SetIdleLineValuesA()254 BaseAddr->MCR = (uint32)RegValue; in Qspi_Ip_SetIdleLineValuesA()278 uint32 RegValue = (uint32)BaseAddr->DLLCRA; in Qspi_Ip_DLLSlaveEnA()280 RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_SLV_EN_MASK)); in Qspi_Ip_DLLSlaveEnA()282 BaseAddr->DLLCRA = (uint32)RegValue; in Qspi_Ip_DLLSlaveEnA()292 uint32 RegValue = (uint32)BaseAddr->DLLCRA; in Qspi_Ip_DLLSlaveUpdateA()294 RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_SLV_UPD_MASK)); in Qspi_Ip_DLLSlaveUpdateA()[all …]
