1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GIC.h 10 * @version 1.3 11 * @date 2021-07-14 12 * @brief Peripheral Access Layer for S32Z2_GIC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GIC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GIC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- S32_GIC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup S32_GIC_Peripheral_Access_Layer S32_GIC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) 72 */ 73 74 /** S32_GICD - Size of Registers Arrays */ 75 #define S32_GICD_IGROUPR_COUNT 30u 76 #define S32_GICD_ISENABLER_COUNT 30u 77 #define S32_GICD_ICENABLER_COUNT 30u 78 #define S32_GICD_ISPENDR_COUNT 30u 79 #define S32_GICD_ICPENDR_COUNT 30u 80 #define S32_GICD_ISACTIVER_COUNT 30u 81 #define S32_GICD_ICACTIVER_COUNT 30u 82 #define S32_GICD_IPRIORITYR_COUNT 240u 83 #define S32_GICD_ICFGR_COUNT 60u 84 #define S32_GICD_IROUTER_COUNT 960u 85 typedef struct 86 { 87 __IO uint32_t GICD_CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ 88 __I uint32_t GICD_TYPRE; /*!< \brief Offset: 0x004 (RO) Interrupt Controller Type Register */ 89 __I uint32_t GICD_IIDR; /*!< \brief Offset: 0x008 (RO) Distributor Implementer Identification Register */ 90 uint32_t RESERVED_0[30]; 91 __IO uint32_t GICD_IGROUPR[S32_GICD_IGROUPR_COUNT]; /*!< \brief Offset: 0x084 (R/W) Interrupt Group Registers */ 92 uint32_t RESERVED_1[2]; 93 __IO uint32_t GICD_ISENABLER[S32_GICD_ISENABLER_COUNT]; /*!< \brief Offset: 0x104 (R/W) Interrupt Set-Enable Registers */ 94 uint32_t RESERVED_2[2]; 95 __IO uint32_t GICD_ICENABLER[S32_GICD_ICENABLER_COUNT]; /*!< \brief Offset: 0x184 (R/W) Interrupt Clear-Enable Registers */ 96 uint32_t RESERVED_3[2]; 97 __IO uint32_t GICD_ISPENDR[S32_GICD_ISPENDR_COUNT]; /*!< \brief Offset: 0x204 (R/W) Interrupt Set-Pending Registers */ 98 uint32_t RESERVED_4[2]; 99 __IO uint32_t GICD_ICPENDR[S32_GICD_ICPENDR_COUNT]; /*!< \brief Offset: 0x284 (R/W) Interrupt Clear-Pending Registers */ 100 uint32_t RESERVED_5[2]; 101 __IO uint32_t GICD_ISACTIVER[S32_GICD_ISACTIVER_COUNT]; /*!< \brief Offset: 0x304 (R/W) Interrupt Set-Active Registers */ 102 uint32_t RESERVED_6[2]; 103 __IO uint32_t GICD_ICACTIVER[S32_GICD_ICACTIVER_COUNT]; /*!< \brief Offset: 0x384 (R/W) Interrupt Clear-Active Registers */ 104 uint32_t RESERVED_7[9]; 105 __IO uint32_t GICD_IPRIORITYR[S32_GICD_IPRIORITYR_COUNT]; /*!< \brief Offset: 0x420 (R/W) Interrupt Priority Registers */ 106 uint32_t RESERVED_8[266]; 107 __IO uint32_t GICD_ICFGR[S32_GICD_ICFGR_COUNT]; /*!< \brief Offset: 0xC08 (R/W) Interrupt Configuration Registers */ 108 uint32_t RESERVED_9[5378]; 109 __IO uint64_t GICD_IROUTER[S32_GICD_IROUTER_COUNT]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ 110 uint32_t RESERVED_10[8244]; 111 __I uint32_t GICD_PIDR4; /*!< \brief Offset: +0xFFD0 - RO - Identification Register */ 112 __I uint32_t GICD_PIDR5; /*!< \brief Offset: +0xFFD4 - RO - Identification Register */ 113 __I uint32_t GICD_PIDR6; /*!< \brief Offset: +0xFFD8 - RO - Identification Register */ 114 __I uint32_t GICD_PIDR7; /*!< \brief Offset: +0xFFDC - RO - Identification Register */ 115 __I uint32_t GICD_PIDR0; /*!< \brief Offset: +0xFFE0 - RO - Identification Register */ 116 __I uint32_t GICD_PIDR1; /*!< \brief Offset: +0xFFE4 - RO - Identification Register */ 117 __I uint32_t GICD_PIDR2; /*!< \brief Offset: +0xFFE8 - RO - Identification Register */ 118 __I uint32_t GICD_PIDR3; /*!< \brief Offset: +0xFFEC - RO - Identification Register */ 119 __I uint32_t GICD_CIDR0; /*!< \brief Offset: +0xFFF0 - RO - Component Identification Register */ 120 __I uint32_t GICD_CIDR1; /*!< \brief Offset: +0xFFF4 - RO - Component Identification Register */ 121 __I uint32_t GICD_CIDR2; /*!< \brief Offset: +0xFFF8 - RO - Component Identification Register */ 122 __I uint32_t GICD_CIDR3; /*!< \brief Offset: +0xFFFC - RO - Component Identification Register */ 123 } S32_GICD_Type, *S32_GICDMemMapPtr; 124 125 /* S32_GICD - Peripheral instance base addresses */ 126 /** Peripheral S32_GICD base address */ 127 #define IP_S32_GICD_BASE (0x47800000u) 128 /** Peripheral S32_GICD base pointer */ 129 #define S32_GICD ((S32_GICD_Type *)IP_S32_GICD_BASE) 130 131 /** \brief Structure type to access the Generic Interrupt Controller Redistributor (GICR) 132 */ 133 134 /** S32_GICR - Size of Registers Arrays */ 135 #define S32_GICR_IPRIORITYR_COUNT 8u 136 137 typedef struct 138 { 139 __I uint32_t GICR_CTLR; /*!< \brief Offset: 0x000 (RO) Redistributor Control Register */ 140 __I uint32_t GICR_IIDR; /*!< \brief Offset: 0x004 (RO) Redistributor Implementer Identification Register */ 141 __I uint32_t GICR_TYPER; /*!< \brief Offset: 0x008 (RO) Interrupt Controller Type Register */ 142 uint32_t RESERVED_0; 143 __IO uint32_t GICR_WAKER; /*!< \brief Offset: 0x014 (R/W) Redistributor Wake Register */ 144 uint32_t RESERVED_1[26]; 145 __IO uint32_t GICR_IGROUPR; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ 146 uint32_t RESERVED_2[31]; 147 __IO uint32_t GICR_ISENABLER; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ 148 uint32_t RESERVED_3[31]; 149 __IO uint32_t GICR_ICENABLER; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ 150 uint32_t RESERVED_4[31]; 151 __IO uint32_t GICR_ISPENDR; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ 152 uint32_t RESERVED_5[31]; 153 __IO uint32_t GICR_ICPENDR; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ 154 uint32_t RESERVED_6[31]; 155 __IO uint32_t GICR_ISACTIVER; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ 156 uint32_t RESERVED_7[31]; 157 __IO uint32_t GICR_ICACTIVER; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ 158 uint32_t RESERVED_8[31]; 159 __IO uint32_t GICR_IPRIORITYR[S32_GICR_IPRIORITYR_COUNT]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ 160 uint32_t RESERVED_9[504]; 161 __IO uint32_t GICR_ICFGR0; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers 0 */ 162 __IO uint32_t GICR_ICFGR1; /*!< \brief Offset: 0xC04 (R/W) Interrupt Configuration Registers 1 */ 163 uint32_t RESERVED_10[15602]; 164 __I uint32_t GICR_PIDR4; /*!< \brief Offset: +0xFFD0 - RO - Identification Register */ 165 __I uint32_t GICR_PIDR5; /*!< \brief Offset: +0xFFD4 - RO - Identification Register */ 166 __I uint32_t GICR_PIDR6; /*!< \brief Offset: +0xFFD8 - RO - Identification Register */ 167 __I uint32_t GICR_PIDR7; /*!< \brief Offset: +0xFFDC - RO - Identification Register */ 168 __I uint32_t GICR_PIDR0; /*!< \brief Offset: +0xFFE0 - RO - Identification Register */ 169 __I uint32_t GICR_PIDR1; /*!< \brief Offset: +0xFFE4 - RO - Identification Register */ 170 __I uint32_t GICR_PIDR2; /*!< \brief Offset: +0xFFE8 - RO - Identification Register */ 171 __I uint32_t GICR_PIDR3; /*!< \brief Offset: +0xFFEC - RO - Identification Register */ 172 __I uint32_t GICR_CIDR0; /*!< \brief Offset: +0xFFF0 - RO - Component Identification Register */ 173 __I uint32_t GICR_CIDR1; /*!< \brief Offset: +0xFFF4 - RO - Component Identification Register */ 174 __I uint32_t GICR_CIDR2; /*!< \brief Offset: +0xFFF8 - RO - Component Identification Register */ 175 __I uint32_t GICR_CIDR3; /*!< \brief Offset: +0xFFFC - RO - Component Identification Register */ 176 } S32_GICR_Type, *S32_GICRMemMapPtr; 177 178 /* S32_GICR - Peripheral instance base addresses */ 179 /** Peripheral S32_GICR base address */ 180 #define IP_S32_GICR_BASE (0x47800000u) 181 /** Peripheral S32_GICR base pointer */ 182 #define S32_GICR ((S32_GICR_Type *)IP_S32_GICR_BASE) 183 184 /* ---------------------------------------------------------------------------- 185 -- S32_GIC Register Masks 186 ---------------------------------------------------------------------------- */ 187 188 189 /*! 190 * @} 191 */ /* end of group S32_GIC_Register_Masks */ 192 193 /*! 194 * @} 195 */ /* end of group S32_GIC_Peripheral_Access_Layer */ 196 /* Set this to 20, as stated by the R52 TRM, if the current value doesn't work */ 197 #define GIC500_MSB (20U) 198 #define GIC500_REDIST_OFFSET (1U << GIC500_MSB) 199 #define GIC500_PADDING_BYTES (GIC500_REDIST_OFFSET - 0x40000U) 200 201 #define IP_GIC500_BASE (0x47800000U) 202 #define IP_GIC500 ((GIC500_Type *)IP_GIC500_BASE) 203 #define IP_GIC500_BASE_ADDRS { IP_GIC500_BASE } 204 #define IP_GIC500_BASE_PTRS { IP_GIC500 } 205 206 /*================================================================================================== 207 * ENUMS 208 ==================================================================================================*/ 209 typedef enum { 210 GIC500_INTG_G0, 211 GIC500_INTG_G1 212 213 } GIC500_IntGroupType; 214 215 typedef enum { 216 GIC500_INTS_LEVEL, 217 GIC500_INTS_EDGE 218 219 } GIC500_IntSignalType; 220 221 /* Follows the MPIDR_EL1 layout of Aff1 and Aff0 */ 222 #define GIC500_AFF_CLUSTER0_CPU0 (0x0000UL) 223 #define GIC500_AFF_CLUSTER0_CPU1 (0x0001UL) 224 #define GIC500_AFF_CLUSTER0_CPU2 (0x0002UL) 225 #define GIC500_AFF_CLUSTER0_CPU3 (0x0003UL) 226 227 #define GIC500_AFF_CLUSTER1_CPU0 (0x0100UL) 228 #define GIC500_AFF_CLUSTER1_CPU1 (0x0101UL) 229 #define GIC500_AFF_CLUSTER1_CPU2 (0x0102UL) 230 #define GIC500_AFF_CLUSTER1_CPU3 (0x0103UL) 231 232 /* Special value - Use this to route to the executing core */ 233 #define GIC500_AFF_CURRENT_PE (0xFF55UL) 234 235 /* Special value - Use this to route to any participating PE ("1 of N") */ 236 #define GIC500_AFF_ANY_PE (0xFFAAUL) 237 238 /* 239 * The GIC-500 only supports topologies where affinity levels 2 and above are the same. That is, 240 * all cores must have MPIDR values of the form 0.0.c.d, where c and d are variables. The range 241 * for c is assumed to start at 0 and be contiguous. The range for d is also assumed to start at 0 and 242 * be contiguous for each c. For example, the first processor must have IDs 0.0.0.0 to 0.0.0.x and 243 * the second processor must have IDs 0.0.1.0 to 0.0.1.y 244 */ 245 246 /* Clusters map to Aff1 */ 247 #define GIC500_CLUSTER_COUNT (2U) 248 /* Cores map to Aff0 */ 249 #define GIC500_CPU_PER_CLUSTER_COUNT (4U) 250 251 252 #define GIC500_PRIO_BITS_COUNT (5U) 253 254 255 #define GIC500_MIN_SGI_ID (0U) 256 #define GIC500_MIN_PPI_ID (16U) 257 #define GIC500_MIN_SPI_ID (32U) 258 #define GIC500_MAX_SPI_ID (960U) 259 #define GIC500_MAX_INT_ID (GIC500_MAX_SPI_ID + 32U) 260 261 262 /* MSB = 17 + max(1, ceil(log2 (total_number_of_cpus))) */ 263 #define GIC500_CPU_COUNT (GIC500_CLUSTER_COUNT * GIC500_CPU_PER_CLUSTER_COUNT) 264 /* Set this to 20, as stated by the R52 TRM, if the current value doesn't work */ 265 #define GIC500_MSB (20U) 266 #define GIC500_REDIST_OFFSET (1U << GIC500_MSB) 267 #define GIC500_PADDING_BYTES (GIC500_REDIST_OFFSET - 0x40000U) 268 269 270 #define IP_GIC500_BASE (0x47800000U) 271 #define IP_GIC500 ((GIC500_Type *)IP_GIC500_BASE) 272 #define IP_GIC500_BASE_ADDRS { IP_GIC500_BASE } 273 #define IP_GIC500_BASE_PTRS { IP_GIC500 } 274 275 #define GIC500_GICD_IROUTER_AFF2_MASK (0x00FF0000UL) 276 #define GIC500_GICD_IROUTER_AFF2_SHIFT (16UL) 277 #define GIC500_GICD_IROUTER_AFF2(x) (((uint32)(((uint32)(x)) << GIC500_GICD_IROUTER_AFF2_SHIFT)) & GIC500_GICD_IROUTER_AFF2_MASK) 278 279 #define GIC500_GICD_IROUTER_AFF1_MASK (0x0000FF00UL) 280 #define GIC500_GICD_IROUTER_AFF1_SHIFT (8UL) 281 #define GIC500_GICD_IROUTER_AFF1(x) (((uint32)(((uint32)(x)) << GIC500_GICD_IROUTER_AFF1_SHIFT)) & GIC500_GICD_IROUTER_AFF1_MASK) 282 283 #define GIC500_GICD_IROUTER_AFF0_MASK (0x000000FFUL) 284 #define GIC500_GICD_IROUTER_AFF0_SHIFT (0UL) 285 #define GIC500_GICD_IROUTER_AFF0(x) (((uint32)(((uint32)(x)) << GIC500_GICD_IROUTER_AFF0_SHIFT)) & GIC500_GICD_IROUTER_AFF0_MASK) 286 287 #define GIC500_GICD_IROUTER_IRM_MASK (0x80000000UL) 288 #define GIC500_GICD_IROUTER_IRM_SHIFT (31UL) 289 #define GIC500_GICD_IROUTER_IRM(x) (((uint32)(((uint32)(x)) << GIC500_GICD_IROUTER_IRM_SHIFT)) & GIC500_GICD_IROUTER_IRM_MASK) 290 /*================================================================================================== 291 * USER TYPES 292 ==================================================================================================*/ 293 struct gic500_gicd_if 294 { 295 volatile uint32 CTLR; /* +0x0000 - RW - Distributor Control Register */ 296 const volatile uint32 TYPER; /* +0x0004 - RO - Interrupt Controller Type Register */ 297 const volatile uint32 IIDR; /* +0x0008 - RO - Distributor Implementer Identification Register */ 298 const volatile uint32 padding0[13]; /* Reserved */ 299 volatile uint32 SETSPI_NSR; /* +0x0040 - WO - Non-Secure SPI Set Register (Used when SPI is signalled using MSI) */ 300 const volatile uint32 padding1; /* Reserved */ 301 volatile uint32 CLRSPI_NSR; /* +0x0048 - WO - Non-Secure SPI Clear Register (Used when SPI is signalled using MSI) */ 302 const volatile uint32 padding2; /* Reserved */ 303 volatile uint32 SETSPI_SR; /* +0x0050 - WO - Secure SPI Set Register (Used when SPI is signalled using MSI) */ 304 const volatile uint32 padding3; /* Reserved */ 305 volatile uint32 CLRSPI_SR; /* +0x0058 - WO - Secure SPI Clear Register (Used when SPI is signalled using MSI) */ 306 const volatile uint32 padding4[9]; /* Reserved */ 307 volatile uint32 IGROUPR[31]; /* +0x0080 - RW - Interrupt Group Registers */ 308 const volatile uint32 padding5; /* Reserved */ 309 volatile uint32 ISENABLER[31]; /* +0x0100 - RW - Interrupt Set-Enable Registers */ 310 const volatile uint32 padding6; /* Reserved */ 311 volatile uint32 ICENABLER[31]; /* +0x0180 - RW - Interrupt Clear-Enable Registers */ 312 const volatile uint32 padding7; /* Reserved */ 313 volatile uint32 ISPENDR[31]; /* +0x0200 - RW - Interrupt Set-Pending Registers */ 314 const volatile uint32 padding8; /* Reserved */ 315 volatile uint32 ICPENDR[31]; /* +0x0280 - RW - Interrupt Clear-Pending Registers */ 316 const volatile uint32 padding9; /* Reserved */ 317 volatile uint32 ISACTIVER[31]; /* +0x0300 - RW - Interrupt Set-Active Register */ 318 const volatile uint32 padding10; /* Reserved */ 319 volatile uint32 ICACTIVER[31]; /* +0x0380 - RW - Interrupt Clear-Active Register */ 320 const volatile uint32 padding11; /* Reserved */ 321 volatile uint32 IPRIORITYR[248]; /* +0x0400 - RW - Interrupt Priority Registers */ 322 const volatile uint32 padding12[8]; /* Reserved */ 323 volatile uint32 ITARGETSR[248]; /* +0x0800 - RW - Interrupt Processor Targets Registers */ 324 const volatile uint32 padding13[8]; /* Reserved */ 325 volatile uint32 ICFGR[62]; /* +0x0C00 - RW - Interrupt Configuration Registers */ 326 const volatile uint32 padding14[2]; /* Reserved */ 327 const volatile uint32 padding15[31]; /* Reserved */ 328 const volatile uint32 padding16[33]; /* Reserved */ 329 volatile uint32 NSACR[62]; /* +0x0E00 - RW - Non-Secure Access Control Registers */ 330 const volatile uint32 padding17[2]; /* Reserved */ 331 volatile uint32 SGIR; /* +0x0F00 - WO - Software Generated Interrupt Register */ 332 const volatile uint32 padding18[3]; /* Reserved */ 333 volatile uint32 CPENDSGIR[4]; /* +0x0F10 - RW - SGI Clear-Pending Registers */ 334 volatile uint32 SPENDSGIR[4]; /* +0x0F20 - RW - SGI Set-Pending Registers */ 335 const volatile uint32 padding19[5236]; /* Reserved */ 336 volatile uint64 IROUTER[960]; /* +0x6100 - RW - Interrupt Routing Registers (Controls SPI routing when ARE=1) */ 337 const volatile uint32 padding20[4160]; /* Reserved */ 338 const volatile uint32 ESTATUSR; /* +0xC000 - RO - Extended Status Register*/ 339 volatile uint32 ERRTESTR; /* +0xC004 - WO - Error Test Register*/ 340 const volatile uint32 padding21[31]; /* Reserved */ 341 const volatile uint32 SPISR[30]; /* +0xC084 - RO - GIC-500 Shared Peripheral Interrupt Status Registers */ 342 const volatile uint32 padding22[4021]; /* Reserved */ 343 const volatile uint32 PIDR4; /* +0xFFD0 - RO - Peripheral ID 4 Register */ 344 const volatile uint32 PIDR5; /* +0xFFD4 - RO - Peripheral ID 5 Register */ 345 const volatile uint32 PIDR6; /* +0xFFD8 - RO - Peripheral ID 6 Register */ 346 const volatile uint32 PIDR7; /* +0xFFDC - RO - Peripheral ID 7 Register */ 347 const volatile uint32 PIDR0; /* +0xFFE0 - RO - Peripheral ID 0 Register */ 348 const volatile uint32 PIDR1; /* +0xFFE4 - RO - Peripheral ID 1 Register */ 349 const volatile uint32 PIDR2; /* +0xFFE8 - RO - Peripheral ID 2 Register */ 350 const volatile uint32 PIDR3; /* +0xFFEC - RO - Peripheral ID 3 Register */ 351 const volatile uint32 CIDR0; /* +0xFFF0 - RO - Component ID 0 Register */ 352 const volatile uint32 CIDR1; /* +0xFFF4 - RO - Component ID 1 Register */ 353 const volatile uint32 CIDR2; /* +0xFFF8 - RO - Component ID 2 Register */ 354 const volatile uint32 CIDR3; /* +0xFFFC - RO - Component ID 3 Register */ 355 }; 356 357 struct gic500_gicd_mbspi_if 358 { 359 const volatile uint32 padding0[16]; /* Reserved */ 360 volatile uint32 SETSPI_NSR; /* +0x0040 - WO - Aliased Non-secure SPI Set Register */ 361 const volatile uint32 padding1; /* Reserved */ 362 volatile uint32 CLRSPI_NSR; /* +0x0048 - WO - Aliased Non-secure SPI Clear Register */ 363 const volatile uint32 padding2; /* Reserved */ 364 volatile uint32 SETSPI_SR; /* +0x0050 - WO - Aliased Secure SPI Set Register */ 365 const volatile uint32 padding3; /* Reserved */ 366 volatile uint32 CLRSPI_SR; /* +0x0058 - WO - Aliased Secure SPI Clear Register */ 367 const volatile uint32 padding4[16361]; /* Reserved */ 368 }; 369 370 typedef struct gic500_gicr_if 371 { 372 volatile uint32 CTLR; /* +0x0000 - RW - Redistributor Control Register */ 373 const volatile uint32 IIDR; /* +0x0004 - RO - Redistributor Implementer Identification Register */ 374 const volatile uint64 TYPER; /* +0x0008 - RO - Redistributor Type Register */ 375 const volatile uint32 padding0; /* Reserved */ 376 volatile uint32 WAKER; /* +0x0014 - RW - Power Management Control Register */ 377 const volatile uint32 padding1[22]; /* Reserved */ 378 volatile uint64 PROPBASER; /* +0x0070 - RW - Common LPI Configuration Table Register */ 379 volatile uint64 PENDBASER; /* +0x0078 - RW - LPI Pending Table Base Register */ 380 const volatile uint32 padding2[16340]; /* Reserved */ 381 const volatile uint32 PIDR4; /* +0xFFD0 - RO - Peripheral ID 4 Register */ 382 const volatile uint32 PIDR5; /* +0xFFD4 - RO - Peripheral ID 5 Register */ 383 const volatile uint32 PIDR6; /* +0xFFD8 - RO - Peripheral ID 6 Register */ 384 const volatile uint32 PIDR7; /* +0xFFDC - RO - Peripheral ID 7 Register */ 385 const volatile uint32 PIDR0; /* +0xFFE0 - RO - Peripheral ID 0 Register */ 386 const volatile uint32 PIDR1; /* +0xFFE4 - RO - Peripheral ID 1 Register */ 387 const volatile uint32 PIDR2; /* +0xFFE8 - RO - Peripheral ID 2 Register */ 388 const volatile uint32 PIDR3; /* +0xFFEC - RO - Peripheral ID 3 Register */ 389 const volatile uint32 CIDR0; /* +0xFFF0 - RO - Component ID 0 Register */ 390 const volatile uint32 CIDR1; /* +0xFFF4 - RO - Component ID 1 Register */ 391 const volatile uint32 CIDR2; /* +0xFFF8 - RO - Component ID 2 Register */ 392 const volatile uint32 CIDR3; /* +0xFFFC - RO - Component ID 3 Register */ 393 }gic500_gicr_if; 394 395 struct gic500_gicr_sgii_if 396 { 397 const volatile uint32 padding0[32]; /* Reserved */ 398 volatile uint32 IGROUPR0; /* +0x0080 - RW - Interrupt Group Registers */ 399 const volatile uint32 padding1[31]; /* Reserved */ 400 volatile uint32 ISENABLER0; /* +0x0100 - RW - Interrupt Set-Enable Registers */ 401 const volatile uint32 padding2[31]; /* Reserved */ 402 volatile uint32 ICENABLER0; /* +0x0180 - RW - Interrupt Clear-Enable Registers */ 403 const volatile uint32 padding3[31]; /* Reserved */ 404 volatile uint32 ISPENDR0; /* +0x0200 - RW - Interrupt Set-Pending Registers */ 405 const volatile uint32 padding4[31]; /* Reserved */ 406 volatile uint32 ICPENDR0; /* +0x0280 - RW - Interrupt Clear-Pending Registers */ 407 const volatile uint32 padding5[31]; /* Reserved */ 408 volatile uint32 ISACTIVER0; /* +0x0300 - RW - Interrupt Set-Active Register */ 409 const volatile uint32 padding6[31]; /* Reserved */ 410 volatile uint32 ICACTIVER0; /* +0x0380 - RW - Interrupt Clear-Active Register */ 411 const volatile uint32 padding7[31]; /* Reserved */ 412 volatile uint32 IPRIORITYR[8]; /* +0x0400 - RW - Interrupt Priority Registers */ 413 const volatile uint32 padding8[504]; /* Reserved */ 414 volatile uint32 ICFGR[2]; /* +0x0C00 - RW - Interrupt Configuration Registers */ 415 const volatile uint32 padding9[62]; /* Reserved */ 416 const volatile uint32 padding10; /* Reserved */ 417 const volatile uint32 padding11[63]; /* Reserved */ 418 volatile uint32 NSACR; /* +0x0E00 - RW - Non-Secure Access Control Register */ 419 const volatile uint32 padding12[11391]; /* Reserved */ 420 const volatile uint32 MISCSTATUSR; /* +0xC000 - RO - Miscellaneous Status Register */ 421 const volatile uint32 padding13[31]; /* Reserved */ 422 const volatile uint32 PPISR; /* +0xC080 - RO - Private Peripheral Interrupt Status Register */ 423 const volatile uint32 padding14[4063]; /* Reserved */ 424 }; 425 426 427 struct gic500_gits_if 428 { 429 volatile uint32 CTLR; /* +0x0000 - RW - ITS Control Register */ 430 const volatile uint32 IIDR; /* +0x0004 - RO - Implementer Identification Register */ 431 const volatile uint64 TYPER; /* +0x0008 - RO - ITS Type Register */ 432 const volatile uint32 padding0[28]; /* Reserved */ 433 volatile uint64 CBASER; /* +0x0080 - RW - Command Queue Control Register */ 434 volatile uint64 CWRITER; /* +0x0088 - RW - Command Queue Write Pointer Register */ 435 const volatile uint64 CREADR; /* +0x0090 - RO - Command Queue Read Pointer Register */ 436 const volatile uint32 padding1[26]; /* Reserved */ 437 const volatile uint64 BASER; /* +0x0100 - RW - ITS Table Control Register */ 438 const volatile uint32 padding2[12222]; /* Reserved */ 439 volatile uint32 TRKCTLR; /* +0x0C00 - WO - Tracking Control Register */ 440 const volatile uint32 TRKR; /* +0x0C04 - RO - Tracking Status Register */ 441 const volatile uint32 TRKDIDR; /* +0x0C08 - RO - Debug Tracked DID Register */ 442 const volatile uint32 TRKPIDR; /* +0x0C0C - RO - Debug Tracked PID Register */ 443 const volatile uint32 TRKVIDR; /* +0x0C10 - RO - Debug Tracked VID Register */ 444 const volatile uint32 TRKTGTR; /* +0x0C14 - RO - Debug Tracked Target Register */ 445 const volatile uint32 TRKICR; /* +0x0C18 - RO - Debug ITE Cache Statistics Register */ 446 const volatile uint32 TRKLCR; /* +0x0C1C - RO - Debug LPI Cache Statistics Register */ 447 const volatile uint32 padding3[4076]; /* Reserved */ 448 const volatile uint32 PIDR4; /* +0xFFD0 - RO - Peripheral ID 4 Register */ 449 const volatile uint32 PIDR5; /* +0xFFD4 - RO - Peripheral ID 5 Register */ 450 const volatile uint32 PIDR6; /* +0xFFD8 - RO - Peripheral ID 6 Register */ 451 const volatile uint32 PIDR7; /* +0xFFDC - RO - Peripheral ID 7 Register */ 452 const volatile uint32 PIDR0; /* +0xFFE0 - RO - Peripheral ID 0 Register */ 453 const volatile uint32 PIDR1; /* +0xFFE4 - RO - Peripheral ID 1 Register */ 454 const volatile uint32 PIDR2; /* +0xFFE8 - RO - Peripheral ID 2 Register */ 455 const volatile uint32 PIDR3; /* +0xFFEC - RO - Peripheral ID 3 Register */ 456 const volatile uint32 CIDR0; /* +0xFFF0 - RO - Component ID 0 Register */ 457 const volatile uint32 CIDR1; /* +0xFFF4 - RO - Component ID 1 Register */ 458 const volatile uint32 CIDR2; /* +0xFFF8 - RO - Component ID 2 Register */ 459 const volatile uint32 CIDR3; /* +0xFFFC - RO - Component ID 3 Register */ 460 }; 461 462 463 struct gic500_gits_tln_if 464 { 465 const volatile uint32 padding0[16]; /* Reserved */ 466 volatile uint32 TRANSLATER; /* +0x0040 - WO - ITS Translation Register */ 467 const volatile uint32 padding3[16367]; /* Reserved */ 468 }; 469 470 471 typedef struct { 472 struct gic500_gicd_if GICD; 473 struct gic500_gicd_mbspi_if GICD_MBSPI; 474 struct gic500_gits_if GITS; 475 struct gic500_gits_tln_if GITS_TLN; 476 477 #if (GIC500_PADDING_BYTES > 0) 478 const volatile uint8 padding0[GIC500_PADDING_BYTES]; 479 #endif 480 481 struct wrapper0 { 482 struct gic500_gicr_if GICR; 483 struct gic500_gicr_sgii_if GICR_SGII; 484 } CPU[GIC500_CPU_COUNT]; 485 486 } GIC500_Type; 487 488 489 490 #endif /* #if !defined(S32Z2_GIC_H_) */ 491
