1 /*
2 * Copyright 2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup RTE_MODULE
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Std_Types.h"
25 #include "Mcal.h"
26 #include "OsIf.h"
27 #include "SchM_Can_43_CANEXCEL.h"
28 #ifdef MCAL_TESTING_ENVIRONMENT
29 #include "EUnit.h" /* EUnit Test Suite */
30 #endif
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define SCHM_CAN_43_CANEXCEL_AR_RELEASE_MAJOR_VERSION_C 4
36 #define SCHM_CAN_43_CANEXCEL_AR_RELEASE_MINOR_VERSION_C 7
37 #define SCHM_CAN_43_CANEXCEL_AR_RELEASE_REVISION_VERSION_C 0
38 #define SCHM_CAN_43_CANEXCEL_SW_MAJOR_VERSION_C 0
39 #define SCHM_CAN_43_CANEXCEL_SW_MINOR_VERSION_C 9
40 #define SCHM_CAN_43_CANEXCEL_SW_PATCH_VERSION_C 0
41
42 /*==================================================================================================
43 * LOCAL CONSTANTS
44 ==================================================================================================*/
45 #ifdef MCAL_PLATFORM_ARM
46 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
47 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
48 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
49 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
50 #else
51 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
52 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
53 #else
54 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
55 #endif
56 #endif
57 #else
58 #ifdef MCAL_PLATFORM_S12
59 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
60 #else
61 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
62 #endif
63 #endif
64 /*==================================================================================================
65 * LOCAL MACROS
66 ==================================================================================================*/
67 #ifdef MCAL_PLATFORM_ARM
68 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
69 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
70 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
71 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
72 #else
73 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
74 #endif
75 #else
76 #ifdef MCAL_PLATFORM_S12
77 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
78 #else
79 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
80 #endif
81 #endif
82
83 /*==================================================================================================
84 * FILE VERSION CHECKS
85 ==================================================================================================*/
86
87 /*==================================================================================================
88 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
89 ==================================================================================================*/
90
91
92 /*==================================================================================================
93 * LOCAL VARIABLES
94 ==================================================================================================*/
95 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
96 #include "Rte_MemMap.h"
97 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_00) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
98 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
99 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_01) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
100 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
101 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_02) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
102 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_03) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_04) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_05) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_06) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_07) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_08) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_09) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_10) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_11) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_12) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_13) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_14) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_15) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_16) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_17) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_18) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_19) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(msr_CAN_EXCLUSIVE_AREA_20) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(reentry_guard_CAN_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
139
140 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
141 #include "Rte_MemMap.h"
142 /*==================================================================================================
143 * GLOBAL CONSTANTS
144 ==================================================================================================*/
145
146
147 /*==================================================================================================
148 * GLOBAL VARIABLES
149 ==================================================================================================*/
150
151 /*==================================================================================================
152 * LOCAL FUNCTION PROTOTYPES
153 ==================================================================================================*/
154
155 #ifndef _COSMIC_C_S32ZE_
156 /*================================================================================================*/
157 /**
158 * @brief This function returns the MSR register value (32 bits).
159 * @details This function returns the MSR register value (32 bits).
160 *
161 * @param[in] void No input parameters
162 * @return uint32 msr This function returns the MSR register value (32 bits).
163 *
164 * @pre None
165 * @post None
166 *
167 */
168 uint32 Can_43_CANEXCEL_schm_read_msr(void);
169 #endif /*ifndef _COSMIC_C_S32ZE_*/
170 /*==================================================================================================
171 * LOCAL FUNCTIONS
172 ==================================================================================================*/
173 #define RTE_START_SEC_CODE
174 #include "Rte_MemMap.h"
175
176 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
177 /*================================================================================================*/
178 /**
179 * @brief This macro returns the MSR register value (32 bits).
180 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
181 *
182 * @pre None
183 * @post None
184 *
185 */
186 #ifdef MCAL_PLATFORM_ARM
187 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Can_43_CANEXCEL_schm_read_msr(void)188 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
189 {
190 mrs x0, S3_3_c4_c2_1
191 }
192 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Can_43_CANEXCEL_schm_read_msr(void)193 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
194 {
195 mrs r0, CPSR
196 }
197 #else
Can_43_CANEXCEL_schm_read_msr(void)198 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
199 {
200 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
201 mrs r0, BASEPRI
202 #else
203 mrs r0, PRIMASK
204 #endif
205 }
206 #endif
207 #else
208 #ifdef MCAL_PLATFORM_S12
Can_43_CANEXCEL_schm_read_msr(void)209 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
210 {
211 tfr ccr, d6
212 }
213 #else
Can_43_CANEXCEL_schm_read_msr(void)214 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
215 {
216 mfmsr r3
217 }
218 #endif
219 #endif
220 #endif /*#ifdef GHS||CW*/
221
222 #ifdef _DIABDATA_C_S32ZE_
223 /**
224 * @brief This function returns the MSR register value (32 bits).
225 * @details This function returns the MSR register value (32 bits).
226 *
227 * @param[in] void No input parameters
228 * @return uint32 msr This function returns the MSR register value (32 bits).
229 *
230 * @pre None
231 * @post None
232 *
233 */
234 #ifdef MCAL_PLATFORM_ARM
Can_43_CANEXCEL_schm_read_msr(void)235 uint32 Can_43_CANEXCEL_schm_read_msr(void)
236 {
237 register uint32 reg_tmp;
238 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
239 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
240 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
241 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
242 #else
243 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
244 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
245 #else
246 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
247 #endif
248 #endif
249 return (uint32)reg_tmp;
250 }
251 #else
Can_43_CANEXCEL_schm_read_msr(void)252 ASM_KEYWORD uint32 Can_43_CANEXCEL_schm_read_msr(void)
253 {
254 mfmsr r3
255 }
256 #endif /* MCAL_PLATFORM_ARM */
257
258 #endif /* _DIABDATA_C_S32ZE_*/
259
260 #ifdef _COSMIC_C_S32ZE_
261 /*================================================================================================*/
262 /**
263 * @brief This function returns the MSR register value (32 bits).
264 * @details This function returns the MSR register value (32 bits).
265 *
266 * @param[in] void No input parameters
267 * @return uint32 msr This function returns the MSR register value (32 bits).
268 *
269 * @pre None
270 * @post None
271 *
272 */
273
274 #ifdef MCAL_PLATFORM_S12
275 #define Can_43_CANEXCEL_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
276 #else
277 #define Can_43_CANEXCEL_schm_read_msr() ASM_KEYWORD("mfmsr r3")
278 #endif
279
280 #endif /*Cosmic compiler only*/
281
282
283 #ifdef _HITECH_C_S32ZE_
284 /*================================================================================================*/
285 /**
286 * @brief This function returns the MSR register value (32 bits).
287 * @details This function returns the MSR register value (32 bits).
288 *
289 * @param[in] void No input parameters
290 * @return uint32 msr This function returns the MSR register value (32 bits).
291 *
292 * @pre None
293 * @post None
294 *
295 */
Can_43_CANEXCEL_schm_read_msr(void)296 uint32 Can_43_CANEXCEL_schm_read_msr(void)
297 {
298 uint32 result;
299 __asm volatile("mfmsr %0" : "=r" (result) :);
300 return result;
301 }
302
303 #endif /*HighTec compiler only*/
304 /*================================================================================================*/
305 #ifdef _LINARO_C_S32ZE_
306 /**
307 * @brief This function returns the MSR register value (32 bits).
308 * @details This function returns the MSR register value (32 bits).
309 *
310 * @param[in] void No input parameters
311 * @return uint32 msr This function returns the MSR register value (32 bits).
312 *
313 * @pre None
314 * @post None
315 *
316 */
Can_43_CANEXCEL_schm_read_msr(void)317 uint32 Can_43_CANEXCEL_schm_read_msr(void)
318 {
319 register uint32 reg_tmp;
320 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
321 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
322 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
323 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
324 #else
325 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
326 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
327 #else
328 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
329 #endif
330 #endif
331 return (uint32)reg_tmp;
332 }
333 #endif /* _LINARO_C_S32ZE_*/
334 /*================================================================================================*/
335
336 #ifdef _ARM_DS5_C_S32ZE_
337 /**
338 * @brief This function returns the MSR register value (32 bits).
339 * @details This function returns the MSR register value (32 bits).
340 *
341 * @param[in] void No input parameters
342 * @return uint32 msr This function returns the MSR register value (32 bits).
343 *
344 * @pre None
345 * @post None
346 *
347 */
Can_43_CANEXCEL_schm_read_msr(void)348 uint32 Can_43_CANEXCEL_schm_read_msr(void)
349 {
350 register uint32 reg_tmp;
351 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
352 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
353 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
354 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
355 #else
356 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
357 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
358 #else
359 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
360 #endif
361 #endif
362 return (uint32)reg_tmp;
363 }
364 #endif /* _ARM_DS5_C_S32ZE_ */
365
366 #ifdef _IAR_C_S32ZE_
367 /**
368 * @brief This function returns the MSR register value (32 bits).
369 * @details This function returns the MSR register value (32 bits).
370 *
371 * @param[in] void No input parameters
372 * @return uint32 msr This function returns the MSR register value (32 bits).
373 *
374 * @pre None
375 * @post None
376 *
377 */
Can_43_CANEXCEL_schm_read_msr(void)378 uint32 Can_43_CANEXCEL_schm_read_msr(void)
379 {
380 register uint32 reg_tmp;
381
382 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
383 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
384 #else
385 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
386 #endif
387
388 return (uint32)reg_tmp;
389 }
390 #endif /* _IAR_C_S32ZE_ */
391
392 #define RTE_STOP_SEC_CODE
393 #include "Rte_MemMap.h"
394
395 /*==================================================================================================
396 * GLOBAL FUNCTIONS
397 ==================================================================================================*/
398 #define RTE_START_SEC_CODE
399 #include "Rte_MemMap.h"
400
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_00(void)401 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_00(void)
402 {
403 uint32 msr;
404 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
405
406 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId])
407 {
408 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
409 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
410 #else
411 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
412 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
413 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
414 {
415 OsIf_SuspendAllInterrupts();
416 #ifdef _ARM_DS5_C_S32ZE_
417 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
418 #endif
419 }
420 msr_CAN_EXCLUSIVE_AREA_00[u32CoreId] = msr;
421 }
422 reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId]++;
423 }
424
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_00(void)425 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_00(void)
426 {
427 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
428
429 reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId]--;
430 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
431 {
432 OsIf_ResumeAllInterrupts();
433 #ifdef _ARM_DS5_C_S32ZE_
434 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
435 #endif
436 }
437 }
438
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_01(void)439 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_01(void)
440 {
441 uint32 msr;
442 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
443
444 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId])
445 {
446 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
447 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
448 #else
449 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
450 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
451 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
452 {
453 OsIf_SuspendAllInterrupts();
454 #ifdef _ARM_DS5_C_S32ZE_
455 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
456 #endif
457 }
458 msr_CAN_EXCLUSIVE_AREA_01[u32CoreId] = msr;
459 }
460 reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId]++;
461 }
462
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_01(void)463 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_01(void)
464 {
465 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
466
467 reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId]--;
468 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
469 {
470 OsIf_ResumeAllInterrupts();
471 #ifdef _ARM_DS5_C_S32ZE_
472 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
473 #endif
474 }
475 }
476
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_02(void)477 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_02(void)
478 {
479 uint32 msr;
480 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
481
482 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId])
483 {
484 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
485 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
486 #else
487 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
488 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
489 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
490 {
491 OsIf_SuspendAllInterrupts();
492 #ifdef _ARM_DS5_C_S32ZE_
493 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
494 #endif
495 }
496 msr_CAN_EXCLUSIVE_AREA_02[u32CoreId] = msr;
497 }
498 reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId]++;
499 }
500
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_02(void)501 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_02(void)
502 {
503 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
504
505 reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId]--;
506 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
507 {
508 OsIf_ResumeAllInterrupts();
509 #ifdef _ARM_DS5_C_S32ZE_
510 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
511 #endif
512 }
513 }
514
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_03(void)515 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_03(void)
516 {
517 uint32 msr;
518 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
519
520 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId])
521 {
522 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
523 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
524 #else
525 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
526 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
527 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
528 {
529 OsIf_SuspendAllInterrupts();
530 #ifdef _ARM_DS5_C_S32ZE_
531 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
532 #endif
533 }
534 msr_CAN_EXCLUSIVE_AREA_03[u32CoreId] = msr;
535 }
536 reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId]++;
537 }
538
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_03(void)539 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_03(void)
540 {
541 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
542
543 reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId]--;
544 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
545 {
546 OsIf_ResumeAllInterrupts();
547 #ifdef _ARM_DS5_C_S32ZE_
548 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
549 #endif
550 }
551 }
552
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_04(void)553 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_04(void)
554 {
555 uint32 msr;
556 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
557
558 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId])
559 {
560 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
561 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
562 #else
563 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
564 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
565 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
566 {
567 OsIf_SuspendAllInterrupts();
568 #ifdef _ARM_DS5_C_S32ZE_
569 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
570 #endif
571 }
572 msr_CAN_EXCLUSIVE_AREA_04[u32CoreId] = msr;
573 }
574 reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId]++;
575 }
576
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_04(void)577 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_04(void)
578 {
579 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
580
581 reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId]--;
582 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
583 {
584 OsIf_ResumeAllInterrupts();
585 #ifdef _ARM_DS5_C_S32ZE_
586 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
587 #endif
588 }
589 }
590
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_05(void)591 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_05(void)
592 {
593 uint32 msr;
594 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
595
596 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId])
597 {
598 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
599 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
600 #else
601 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
602 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
603 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
604 {
605 OsIf_SuspendAllInterrupts();
606 #ifdef _ARM_DS5_C_S32ZE_
607 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
608 #endif
609 }
610 msr_CAN_EXCLUSIVE_AREA_05[u32CoreId] = msr;
611 }
612 reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId]++;
613 }
614
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_05(void)615 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_05(void)
616 {
617 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
618
619 reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId]--;
620 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
621 {
622 OsIf_ResumeAllInterrupts();
623 #ifdef _ARM_DS5_C_S32ZE_
624 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
625 #endif
626 }
627 }
628
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_06(void)629 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_06(void)
630 {
631 uint32 msr;
632 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
633
634 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId])
635 {
636 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
637 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
638 #else
639 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
640 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
641 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
642 {
643 OsIf_SuspendAllInterrupts();
644 #ifdef _ARM_DS5_C_S32ZE_
645 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
646 #endif
647 }
648 msr_CAN_EXCLUSIVE_AREA_06[u32CoreId] = msr;
649 }
650 reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId]++;
651 }
652
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_06(void)653 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_06(void)
654 {
655 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
656
657 reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId]--;
658 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
659 {
660 OsIf_ResumeAllInterrupts();
661 #ifdef _ARM_DS5_C_S32ZE_
662 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
663 #endif
664 }
665 }
666
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_07(void)667 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_07(void)
668 {
669 uint32 msr;
670 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
671
672 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId])
673 {
674 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
675 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
676 #else
677 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
678 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
679 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
680 {
681 OsIf_SuspendAllInterrupts();
682 #ifdef _ARM_DS5_C_S32ZE_
683 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
684 #endif
685 }
686 msr_CAN_EXCLUSIVE_AREA_07[u32CoreId] = msr;
687 }
688 reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId]++;
689 }
690
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_07(void)691 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_07(void)
692 {
693 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
694
695 reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId]--;
696 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
697 {
698 OsIf_ResumeAllInterrupts();
699 #ifdef _ARM_DS5_C_S32ZE_
700 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
701 #endif
702 }
703 }
704
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_08(void)705 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_08(void)
706 {
707 uint32 msr;
708 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
709
710 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId])
711 {
712 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
713 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
714 #else
715 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
716 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
717 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
718 {
719 OsIf_SuspendAllInterrupts();
720 #ifdef _ARM_DS5_C_S32ZE_
721 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
722 #endif
723 }
724 msr_CAN_EXCLUSIVE_AREA_08[u32CoreId] = msr;
725 }
726 reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId]++;
727 }
728
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_08(void)729 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_08(void)
730 {
731 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
732
733 reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId]--;
734 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
735 {
736 OsIf_ResumeAllInterrupts();
737 #ifdef _ARM_DS5_C_S32ZE_
738 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
739 #endif
740 }
741 }
742
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_09(void)743 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_09(void)
744 {
745 uint32 msr;
746 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
747
748 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId])
749 {
750 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
751 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
752 #else
753 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
754 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
755 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
756 {
757 OsIf_SuspendAllInterrupts();
758 #ifdef _ARM_DS5_C_S32ZE_
759 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
760 #endif
761 }
762 msr_CAN_EXCLUSIVE_AREA_09[u32CoreId] = msr;
763 }
764 reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId]++;
765 }
766
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_09(void)767 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_09(void)
768 {
769 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
770
771 reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId]--;
772 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
773 {
774 OsIf_ResumeAllInterrupts();
775 #ifdef _ARM_DS5_C_S32ZE_
776 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
777 #endif
778 }
779 }
780
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_10(void)781 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_10(void)
782 {
783 uint32 msr;
784 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
785
786 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId])
787 {
788 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
789 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
790 #else
791 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
792 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
793 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
794 {
795 OsIf_SuspendAllInterrupts();
796 #ifdef _ARM_DS5_C_S32ZE_
797 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
798 #endif
799 }
800 msr_CAN_EXCLUSIVE_AREA_10[u32CoreId] = msr;
801 }
802 reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId]++;
803 }
804
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_10(void)805 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_10(void)
806 {
807 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
808
809 reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId]--;
810 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
811 {
812 OsIf_ResumeAllInterrupts();
813 #ifdef _ARM_DS5_C_S32ZE_
814 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
815 #endif
816 }
817 }
818
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_11(void)819 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_11(void)
820 {
821 uint32 msr;
822 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
823
824 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId])
825 {
826 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
827 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
828 #else
829 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
830 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
831 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
832 {
833 OsIf_SuspendAllInterrupts();
834 #ifdef _ARM_DS5_C_S32ZE_
835 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
836 #endif
837 }
838 msr_CAN_EXCLUSIVE_AREA_11[u32CoreId] = msr;
839 }
840 reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId]++;
841 }
842
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_11(void)843 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_11(void)
844 {
845 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
846
847 reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId]--;
848 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
849 {
850 OsIf_ResumeAllInterrupts();
851 #ifdef _ARM_DS5_C_S32ZE_
852 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
853 #endif
854 }
855 }
856
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_12(void)857 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_12(void)
858 {
859 uint32 msr;
860 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
861
862 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId])
863 {
864 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
865 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
866 #else
867 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
868 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
869 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
870 {
871 OsIf_SuspendAllInterrupts();
872 #ifdef _ARM_DS5_C_S32ZE_
873 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
874 #endif
875 }
876 msr_CAN_EXCLUSIVE_AREA_12[u32CoreId] = msr;
877 }
878 reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId]++;
879 }
880
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_12(void)881 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_12(void)
882 {
883 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
884
885 reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId]--;
886 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
887 {
888 OsIf_ResumeAllInterrupts();
889 #ifdef _ARM_DS5_C_S32ZE_
890 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
891 #endif
892 }
893 }
894
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_13(void)895 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_13(void)
896 {
897 uint32 msr;
898 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
899
900 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId])
901 {
902 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
903 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
904 #else
905 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
906 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
907 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
908 {
909 OsIf_SuspendAllInterrupts();
910 #ifdef _ARM_DS5_C_S32ZE_
911 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
912 #endif
913 }
914 msr_CAN_EXCLUSIVE_AREA_13[u32CoreId] = msr;
915 }
916 reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId]++;
917 }
918
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_13(void)919 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_13(void)
920 {
921 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
922
923 reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId]--;
924 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
925 {
926 OsIf_ResumeAllInterrupts();
927 #ifdef _ARM_DS5_C_S32ZE_
928 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
929 #endif
930 }
931 }
932
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_14(void)933 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_14(void)
934 {
935 uint32 msr;
936 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
937
938 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId])
939 {
940 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
941 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
942 #else
943 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
944 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
945 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
946 {
947 OsIf_SuspendAllInterrupts();
948 #ifdef _ARM_DS5_C_S32ZE_
949 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
950 #endif
951 }
952 msr_CAN_EXCLUSIVE_AREA_14[u32CoreId] = msr;
953 }
954 reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId]++;
955 }
956
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_14(void)957 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_14(void)
958 {
959 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
960
961 reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId]--;
962 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
963 {
964 OsIf_ResumeAllInterrupts();
965 #ifdef _ARM_DS5_C_S32ZE_
966 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
967 #endif
968 }
969 }
970
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_15(void)971 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_15(void)
972 {
973 uint32 msr;
974 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
975
976 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId])
977 {
978 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
979 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
980 #else
981 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
982 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
983 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
984 {
985 OsIf_SuspendAllInterrupts();
986 #ifdef _ARM_DS5_C_S32ZE_
987 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
988 #endif
989 }
990 msr_CAN_EXCLUSIVE_AREA_15[u32CoreId] = msr;
991 }
992 reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId]++;
993 }
994
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_15(void)995 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_15(void)
996 {
997 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
998
999 reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId]--;
1000 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
1001 {
1002 OsIf_ResumeAllInterrupts();
1003 #ifdef _ARM_DS5_C_S32ZE_
1004 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1005 #endif
1006 }
1007 }
1008
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_16(void)1009 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_16(void)
1010 {
1011 uint32 msr;
1012 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1013
1014 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId])
1015 {
1016 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1017 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
1018 #else
1019 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
1020 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1021 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1022 {
1023 OsIf_SuspendAllInterrupts();
1024 #ifdef _ARM_DS5_C_S32ZE_
1025 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1026 #endif
1027 }
1028 msr_CAN_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1029 }
1030 reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId]++;
1031 }
1032
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_16(void)1033 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_16(void)
1034 {
1035 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1036
1037 reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId]--;
1038 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1039 {
1040 OsIf_ResumeAllInterrupts();
1041 #ifdef _ARM_DS5_C_S32ZE_
1042 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1043 #endif
1044 }
1045 }
1046
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_17(void)1047 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_17(void)
1048 {
1049 uint32 msr;
1050 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1051
1052 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId])
1053 {
1054 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1055 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
1056 #else
1057 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
1058 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1059 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1060 {
1061 OsIf_SuspendAllInterrupts();
1062 #ifdef _ARM_DS5_C_S32ZE_
1063 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1064 #endif
1065 }
1066 msr_CAN_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1067 }
1068 reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId]++;
1069 }
1070
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_17(void)1071 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_17(void)
1072 {
1073 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1074
1075 reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId]--;
1076 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1077 {
1078 OsIf_ResumeAllInterrupts();
1079 #ifdef _ARM_DS5_C_S32ZE_
1080 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1081 #endif
1082 }
1083 }
1084
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_18(void)1085 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_18(void)
1086 {
1087 uint32 msr;
1088 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1089
1090 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId])
1091 {
1092 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1093 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
1094 #else
1095 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
1096 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1097 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1098 {
1099 OsIf_SuspendAllInterrupts();
1100 #ifdef _ARM_DS5_C_S32ZE_
1101 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1102 #endif
1103 }
1104 msr_CAN_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1105 }
1106 reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId]++;
1107 }
1108
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_18(void)1109 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_18(void)
1110 {
1111 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1112
1113 reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId]--;
1114 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1115 {
1116 OsIf_ResumeAllInterrupts();
1117 #ifdef _ARM_DS5_C_S32ZE_
1118 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1119 #endif
1120 }
1121 }
1122
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_19(void)1123 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_19(void)
1124 {
1125 uint32 msr;
1126 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1127
1128 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId])
1129 {
1130 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1131 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
1132 #else
1133 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
1134 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1135 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1136 {
1137 OsIf_SuspendAllInterrupts();
1138 #ifdef _ARM_DS5_C_S32ZE_
1139 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1140 #endif
1141 }
1142 msr_CAN_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1143 }
1144 reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId]++;
1145 }
1146
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_19(void)1147 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_19(void)
1148 {
1149 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1150
1151 reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId]--;
1152 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1153 {
1154 OsIf_ResumeAllInterrupts();
1155 #ifdef _ARM_DS5_C_S32ZE_
1156 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1157 #endif
1158 }
1159 }
1160
SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_20(void)1161 void SchM_Enter_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_20(void)
1162 {
1163 uint32 msr;
1164 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1165
1166 if(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId])
1167 {
1168 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1169 msr = OsIf_Trusted_Call_Return(Can_43_CANEXCEL_schm_read_msr);
1170 #else
1171 msr = Can_43_CANEXCEL_schm_read_msr(); /*read MSR (to store interrupts state)*/
1172 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1173 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1174 {
1175 OsIf_SuspendAllInterrupts();
1176 #ifdef _ARM_DS5_C_S32ZE_
1177 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1178 #endif
1179 }
1180 msr_CAN_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1181 }
1182 reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId]++;
1183 }
1184
SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_20(void)1185 void SchM_Exit_Can_43_CANEXCEL_CAN_EXCLUSIVE_AREA_20(void)
1186 {
1187 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1188
1189 reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId]--;
1190 if ((ISR_ON(msr_CAN_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1191 {
1192 OsIf_ResumeAllInterrupts();
1193 #ifdef _ARM_DS5_C_S32ZE_
1194 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1195 #endif
1196 }
1197 }
1198
1199
1200 #ifdef MCAL_TESTING_ENVIRONMENT
1201 /**
1202 @brief This function checks that all entered exclusive areas were also exited.
1203 @details This function checks that all entered exclusive areas were also exited. The check
1204 is done by verifying that all reentry_guard_* static variables are back to the
1205 zero value.
1206
1207 @param[in] void No input parameters
1208 @return void This function does not return a value. Test asserts are used instead.
1209
1210 @pre None
1211 @post None
1212
1213 @remarks Covers
1214 @remarks Implements
1215 */
SchM_Check_can_43_CANEXCEL(void)1216 void SchM_Check_can_43_CANEXCEL(void)
1217 {
1218 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1219
1220 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId]);
1221 reentry_guard_CAN_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_00 for the next test in the suite*/
1222
1223 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId]);
1224 reentry_guard_CAN_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_01 for the next test in the suite*/
1225
1226 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId]);
1227 reentry_guard_CAN_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_02 for the next test in the suite*/
1228
1229 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId]);
1230 reentry_guard_CAN_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_03 for the next test in the suite*/
1231
1232 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId]);
1233 reentry_guard_CAN_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_04 for the next test in the suite*/
1234
1235 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId]);
1236 reentry_guard_CAN_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_05 for the next test in the suite*/
1237
1238 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId]);
1239 reentry_guard_CAN_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_06 for the next test in the suite*/
1240
1241 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId]);
1242 reentry_guard_CAN_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_07 for the next test in the suite*/
1243
1244 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId]);
1245 reentry_guard_CAN_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_08 for the next test in the suite*/
1246
1247 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId]);
1248 reentry_guard_CAN_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_09 for the next test in the suite*/
1249
1250 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId]);
1251 reentry_guard_CAN_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_10 for the next test in the suite*/
1252
1253 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId]);
1254 reentry_guard_CAN_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_11 for the next test in the suite*/
1255
1256 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId]);
1257 reentry_guard_CAN_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_12 for the next test in the suite*/
1258
1259 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId]);
1260 reentry_guard_CAN_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_13 for the next test in the suite*/
1261
1262 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId]);
1263 reentry_guard_CAN_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_14 for the next test in the suite*/
1264
1265 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId]);
1266 reentry_guard_CAN_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_15 for the next test in the suite*/
1267
1268 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId]);
1269 reentry_guard_CAN_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_16 for the next test in the suite*/
1270
1271 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId]);
1272 reentry_guard_CAN_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_17 for the next test in the suite*/
1273
1274 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId]);
1275 reentry_guard_CAN_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_18 for the next test in the suite*/
1276
1277 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId]);
1278 reentry_guard_CAN_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_19 for the next test in the suite*/
1279
1280 EU_ASSERT(0UL == reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId]);
1281 reentry_guard_CAN_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_CAN_EXCLUSIVE_AREA_20 for the next test in the suite*/
1282
1283
1284 }
1285 #endif /*MCAL_TESTING_ENVIRONMENT*/
1286
1287 #define RTE_STOP_SEC_CODE
1288 #include "Rte_MemMap.h"
1289
1290 #ifdef __cplusplus
1291 }
1292 #endif
1293
1294 /** @} */
1295
