1 /*
2 * Copyright 2021-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup RTE_MODULE
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Std_Types.h"
25 #include "Mcal.h"
26 #include "OsIf.h"
27 #include "SchM_Icu.h"
28 #ifdef MCAL_TESTING_ENVIRONMENT
29 #include "EUnit.h" /* EUnit Test Suite */
30 #endif
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define SCHM_ICU_AR_RELEASE_MAJOR_VERSION_C 4
36 #define SCHM_ICU_AR_RELEASE_MINOR_VERSION_C 7
37 #define SCHM_ICU_AR_RELEASE_REVISION_VERSION_C 0
38 #define SCHM_ICU_SW_MAJOR_VERSION_C 0
39 #define SCHM_ICU_SW_MINOR_VERSION_C 9
40 #define SCHM_ICU_SW_PATCH_VERSION_C 0
41
42 /*==================================================================================================
43 * LOCAL CONSTANTS
44 ==================================================================================================*/
45 #ifdef MCAL_PLATFORM_ARM
46 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
47 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
48 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
49 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
50 #else
51 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
52 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
53 #else
54 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
55 #endif
56 #endif
57 #else
58 #ifdef MCAL_PLATFORM_S12
59 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
60 #else
61 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
62 #endif
63 #endif
64 /*==================================================================================================
65 * LOCAL MACROS
66 ==================================================================================================*/
67 #ifdef MCAL_PLATFORM_ARM
68 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
69 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
70 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
71 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
72 #else
73 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
74 #endif
75 #else
76 #ifdef MCAL_PLATFORM_S12
77 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
78 #else
79 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
80 #endif
81 #endif
82
83 /*==================================================================================================
84 * FILE VERSION CHECKS
85 ==================================================================================================*/
86
87 /*==================================================================================================
88 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
89 ==================================================================================================*/
90
91
92 /*==================================================================================================
93 * LOCAL VARIABLES
94 ==================================================================================================*/
95 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
96 #include "Rte_MemMap.h"
97 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_00) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
98 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
99 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_01) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
100 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
101 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_02) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
102 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_03) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_04) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_05) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_06) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_07) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_08) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_09) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_11) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_15) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_16) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_17) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_18) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_19) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_20) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_21) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_22) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_22) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_23) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_23) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_24) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_24) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_25) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_25) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_26) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_26) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_27) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_27) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_28) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
146 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_28) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
147 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_29) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
148 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_29) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
149 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_30) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
150 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_30) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
151 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_31) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
152 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_31) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
153 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_32) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
154 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_32) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
155 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_33) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
156 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_33) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
157 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_44) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
158 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_44) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
159 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_45) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
160 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_45) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
161 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_46) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
162 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_46) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
163 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_47) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_47[NUMBER_OF_CORES];
164 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_47) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_47[NUMBER_OF_CORES];
165 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_48) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_48[NUMBER_OF_CORES];
166 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_48) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_48[NUMBER_OF_CORES];
167 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_49) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_49[NUMBER_OF_CORES];
168 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_49) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_49[NUMBER_OF_CORES];
169 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_50) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
170 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_50) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
171 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_51) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
172 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_51) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
173 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_52) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_52[NUMBER_OF_CORES];
174 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_52) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_52[NUMBER_OF_CORES];
175 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_53) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_53[NUMBER_OF_CORES];
176 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_53) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_53[NUMBER_OF_CORES];
177 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_57) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_57[NUMBER_OF_CORES];
178 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_57) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_57[NUMBER_OF_CORES];
179 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_58) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_58[NUMBER_OF_CORES];
180 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_58) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_58[NUMBER_OF_CORES];
181 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_59) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_59[NUMBER_OF_CORES];
182 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_59) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_59[NUMBER_OF_CORES];
183
184 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
185 #include "Rte_MemMap.h"
186 /*==================================================================================================
187 * GLOBAL CONSTANTS
188 ==================================================================================================*/
189
190
191 /*==================================================================================================
192 * GLOBAL VARIABLES
193 ==================================================================================================*/
194
195 /*==================================================================================================
196 * LOCAL FUNCTION PROTOTYPES
197 ==================================================================================================*/
198
199 #ifndef _COSMIC_C_S32ZE_
200 /*================================================================================================*/
201 /**
202 * @brief This function returns the MSR register value (32 bits).
203 * @details This function returns the MSR register value (32 bits).
204 *
205 * @param[in] void No input parameters
206 * @return uint32 msr This function returns the MSR register value (32 bits).
207 *
208 * @pre None
209 * @post None
210 *
211 */
212 uint32 Icu_schm_read_msr(void);
213 #endif /*ifndef _COSMIC_C_S32ZE_*/
214 /*==================================================================================================
215 * LOCAL FUNCTIONS
216 ==================================================================================================*/
217 #define RTE_START_SEC_CODE
218 #include "Rte_MemMap.h"
219
220 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
221 /*================================================================================================*/
222 /**
223 * @brief This macro returns the MSR register value (32 bits).
224 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
225 *
226 * @pre None
227 * @post None
228 *
229 */
230 #ifdef MCAL_PLATFORM_ARM
231 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Icu_schm_read_msr(void)232 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
233 {
234 mrs x0, S3_3_c4_c2_1
235 }
236 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Icu_schm_read_msr(void)237 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
238 {
239 mrs r0, CPSR
240 }
241 #else
Icu_schm_read_msr(void)242 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
243 {
244 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
245 mrs r0, BASEPRI
246 #else
247 mrs r0, PRIMASK
248 #endif
249 }
250 #endif
251 #else
252 #ifdef MCAL_PLATFORM_S12
Icu_schm_read_msr(void)253 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
254 {
255 tfr ccr, d6
256 }
257 #else
Icu_schm_read_msr(void)258 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
259 {
260 mfmsr r3
261 }
262 #endif
263 #endif
264 #endif /*#ifdef GHS||CW*/
265
266 #ifdef _DIABDATA_C_S32ZE_
267 /**
268 * @brief This function returns the MSR register value (32 bits).
269 * @details This function returns the MSR register value (32 bits).
270 *
271 * @param[in] void No input parameters
272 * @return uint32 msr This function returns the MSR register value (32 bits).
273 *
274 * @pre None
275 * @post None
276 *
277 */
278 #ifdef MCAL_PLATFORM_ARM
Icu_schm_read_msr(void)279 uint32 Icu_schm_read_msr(void)
280 {
281 register uint32 reg_tmp;
282 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
283 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
284 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
285 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
286 #else
287 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
288 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
289 #else
290 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
291 #endif
292 #endif
293 return (uint32)reg_tmp;
294 }
295 #else
Icu_schm_read_msr(void)296 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
297 {
298 mfmsr r3
299 }
300 #endif /* MCAL_PLATFORM_ARM */
301
302 #endif /* _DIABDATA_C_S32ZE_*/
303
304 #ifdef _COSMIC_C_S32ZE_
305 /*================================================================================================*/
306 /**
307 * @brief This function returns the MSR register value (32 bits).
308 * @details This function returns the MSR register value (32 bits).
309 *
310 * @param[in] void No input parameters
311 * @return uint32 msr This function returns the MSR register value (32 bits).
312 *
313 * @pre None
314 * @post None
315 *
316 */
317
318 #ifdef MCAL_PLATFORM_S12
319 #define Icu_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
320 #else
321 #define Icu_schm_read_msr() ASM_KEYWORD("mfmsr r3")
322 #endif
323
324 #endif /*Cosmic compiler only*/
325
326
327 #ifdef _HITECH_C_S32ZE_
328 /*================================================================================================*/
329 /**
330 * @brief This function returns the MSR register value (32 bits).
331 * @details This function returns the MSR register value (32 bits).
332 *
333 * @param[in] void No input parameters
334 * @return uint32 msr This function returns the MSR register value (32 bits).
335 *
336 * @pre None
337 * @post None
338 *
339 */
Icu_schm_read_msr(void)340 uint32 Icu_schm_read_msr(void)
341 {
342 uint32 result;
343 __asm volatile("mfmsr %0" : "=r" (result) :);
344 return result;
345 }
346
347 #endif /*HighTec compiler only*/
348 /*================================================================================================*/
349 #ifdef _LINARO_C_S32ZE_
350 /**
351 * @brief This function returns the MSR register value (32 bits).
352 * @details This function returns the MSR register value (32 bits).
353 *
354 * @param[in] void No input parameters
355 * @return uint32 msr This function returns the MSR register value (32 bits).
356 *
357 * @pre None
358 * @post None
359 *
360 */
Icu_schm_read_msr(void)361 uint32 Icu_schm_read_msr(void)
362 {
363 register uint32 reg_tmp;
364 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
365 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
366 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
367 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
368 #else
369 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
370 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
371 #else
372 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
373 #endif
374 #endif
375 return (uint32)reg_tmp;
376 }
377 #endif /* _LINARO_C_S32ZE_*/
378 /*================================================================================================*/
379
380 #ifdef _ARM_DS5_C_S32ZE_
381 /**
382 * @brief This function returns the MSR register value (32 bits).
383 * @details This function returns the MSR register value (32 bits).
384 *
385 * @param[in] void No input parameters
386 * @return uint32 msr This function returns the MSR register value (32 bits).
387 *
388 * @pre None
389 * @post None
390 *
391 */
Icu_schm_read_msr(void)392 uint32 Icu_schm_read_msr(void)
393 {
394 register uint32 reg_tmp;
395 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
396 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
397 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
398 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
399 #else
400 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
401 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
402 #else
403 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
404 #endif
405 #endif
406 return (uint32)reg_tmp;
407 }
408 #endif /* _ARM_DS5_C_S32ZE_ */
409
410 #ifdef _IAR_C_S32ZE_
411 /**
412 * @brief This function returns the MSR register value (32 bits).
413 * @details This function returns the MSR register value (32 bits).
414 *
415 * @param[in] void No input parameters
416 * @return uint32 msr This function returns the MSR register value (32 bits).
417 *
418 * @pre None
419 * @post None
420 *
421 */
Icu_schm_read_msr(void)422 uint32 Icu_schm_read_msr(void)
423 {
424 register uint32 reg_tmp;
425
426 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
427 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
428 #else
429 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
430 #endif
431
432 return (uint32)reg_tmp;
433 }
434 #endif /* _IAR_C_S32ZE_ */
435
436 #define RTE_STOP_SEC_CODE
437 #include "Rte_MemMap.h"
438
439 /*==================================================================================================
440 * GLOBAL FUNCTIONS
441 ==================================================================================================*/
442 #define RTE_START_SEC_CODE
443 #include "Rte_MemMap.h"
444
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_00(void)445 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_00(void)
446 {
447 uint32 msr;
448 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
449
450 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId])
451 {
452 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
453 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
454 #else
455 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
456 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
457 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
458 {
459 OsIf_SuspendAllInterrupts();
460 #ifdef _ARM_DS5_C_S32ZE_
461 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
462 #endif
463 }
464 msr_ICU_EXCLUSIVE_AREA_00[u32CoreId] = msr;
465 }
466 reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId]++;
467 }
468
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_00(void)469 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_00(void)
470 {
471 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
472
473 reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId]--;
474 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
475 {
476 OsIf_ResumeAllInterrupts();
477 #ifdef _ARM_DS5_C_S32ZE_
478 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
479 #endif
480 }
481 }
482
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_01(void)483 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_01(void)
484 {
485 uint32 msr;
486 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
487
488 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId])
489 {
490 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
491 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
492 #else
493 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
494 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
495 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
496 {
497 OsIf_SuspendAllInterrupts();
498 #ifdef _ARM_DS5_C_S32ZE_
499 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
500 #endif
501 }
502 msr_ICU_EXCLUSIVE_AREA_01[u32CoreId] = msr;
503 }
504 reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId]++;
505 }
506
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_01(void)507 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_01(void)
508 {
509 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
510
511 reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId]--;
512 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
513 {
514 OsIf_ResumeAllInterrupts();
515 #ifdef _ARM_DS5_C_S32ZE_
516 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
517 #endif
518 }
519 }
520
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_02(void)521 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_02(void)
522 {
523 uint32 msr;
524 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
525
526 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId])
527 {
528 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
529 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
530 #else
531 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
532 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
533 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
534 {
535 OsIf_SuspendAllInterrupts();
536 #ifdef _ARM_DS5_C_S32ZE_
537 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
538 #endif
539 }
540 msr_ICU_EXCLUSIVE_AREA_02[u32CoreId] = msr;
541 }
542 reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId]++;
543 }
544
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_02(void)545 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_02(void)
546 {
547 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
548
549 reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId]--;
550 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
551 {
552 OsIf_ResumeAllInterrupts();
553 #ifdef _ARM_DS5_C_S32ZE_
554 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
555 #endif
556 }
557 }
558
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_03(void)559 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_03(void)
560 {
561 uint32 msr;
562 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
563
564 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId])
565 {
566 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
567 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
568 #else
569 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
570 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
571 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
572 {
573 OsIf_SuspendAllInterrupts();
574 #ifdef _ARM_DS5_C_S32ZE_
575 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
576 #endif
577 }
578 msr_ICU_EXCLUSIVE_AREA_03[u32CoreId] = msr;
579 }
580 reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId]++;
581 }
582
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_03(void)583 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_03(void)
584 {
585 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
586
587 reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId]--;
588 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
589 {
590 OsIf_ResumeAllInterrupts();
591 #ifdef _ARM_DS5_C_S32ZE_
592 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
593 #endif
594 }
595 }
596
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_04(void)597 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_04(void)
598 {
599 uint32 msr;
600 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
601
602 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId])
603 {
604 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
605 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
606 #else
607 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
608 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
609 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
610 {
611 OsIf_SuspendAllInterrupts();
612 #ifdef _ARM_DS5_C_S32ZE_
613 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
614 #endif
615 }
616 msr_ICU_EXCLUSIVE_AREA_04[u32CoreId] = msr;
617 }
618 reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId]++;
619 }
620
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_04(void)621 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_04(void)
622 {
623 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
624
625 reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId]--;
626 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
627 {
628 OsIf_ResumeAllInterrupts();
629 #ifdef _ARM_DS5_C_S32ZE_
630 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
631 #endif
632 }
633 }
634
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_05(void)635 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_05(void)
636 {
637 uint32 msr;
638 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
639
640 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId])
641 {
642 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
643 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
644 #else
645 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
646 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
647 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
648 {
649 OsIf_SuspendAllInterrupts();
650 #ifdef _ARM_DS5_C_S32ZE_
651 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
652 #endif
653 }
654 msr_ICU_EXCLUSIVE_AREA_05[u32CoreId] = msr;
655 }
656 reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId]++;
657 }
658
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_05(void)659 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_05(void)
660 {
661 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
662
663 reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId]--;
664 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
665 {
666 OsIf_ResumeAllInterrupts();
667 #ifdef _ARM_DS5_C_S32ZE_
668 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
669 #endif
670 }
671 }
672
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_06(void)673 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_06(void)
674 {
675 uint32 msr;
676 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
677
678 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId])
679 {
680 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
681 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
682 #else
683 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
684 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
685 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
686 {
687 OsIf_SuspendAllInterrupts();
688 #ifdef _ARM_DS5_C_S32ZE_
689 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
690 #endif
691 }
692 msr_ICU_EXCLUSIVE_AREA_06[u32CoreId] = msr;
693 }
694 reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId]++;
695 }
696
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_06(void)697 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_06(void)
698 {
699 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
700
701 reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId]--;
702 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
703 {
704 OsIf_ResumeAllInterrupts();
705 #ifdef _ARM_DS5_C_S32ZE_
706 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
707 #endif
708 }
709 }
710
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_07(void)711 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_07(void)
712 {
713 uint32 msr;
714 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
715
716 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId])
717 {
718 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
719 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
720 #else
721 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
722 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
723 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
724 {
725 OsIf_SuspendAllInterrupts();
726 #ifdef _ARM_DS5_C_S32ZE_
727 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
728 #endif
729 }
730 msr_ICU_EXCLUSIVE_AREA_07[u32CoreId] = msr;
731 }
732 reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId]++;
733 }
734
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_07(void)735 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_07(void)
736 {
737 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
738
739 reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId]--;
740 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
741 {
742 OsIf_ResumeAllInterrupts();
743 #ifdef _ARM_DS5_C_S32ZE_
744 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
745 #endif
746 }
747 }
748
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_08(void)749 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_08(void)
750 {
751 uint32 msr;
752 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
753
754 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId])
755 {
756 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
757 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
758 #else
759 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
760 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
761 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
762 {
763 OsIf_SuspendAllInterrupts();
764 #ifdef _ARM_DS5_C_S32ZE_
765 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
766 #endif
767 }
768 msr_ICU_EXCLUSIVE_AREA_08[u32CoreId] = msr;
769 }
770 reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId]++;
771 }
772
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_08(void)773 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_08(void)
774 {
775 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
776
777 reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId]--;
778 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
779 {
780 OsIf_ResumeAllInterrupts();
781 #ifdef _ARM_DS5_C_S32ZE_
782 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
783 #endif
784 }
785 }
786
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_09(void)787 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_09(void)
788 {
789 uint32 msr;
790 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
791
792 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId])
793 {
794 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
795 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
796 #else
797 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
798 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
799 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
800 {
801 OsIf_SuspendAllInterrupts();
802 #ifdef _ARM_DS5_C_S32ZE_
803 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
804 #endif
805 }
806 msr_ICU_EXCLUSIVE_AREA_09[u32CoreId] = msr;
807 }
808 reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId]++;
809 }
810
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_09(void)811 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_09(void)
812 {
813 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
814
815 reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId]--;
816 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
817 {
818 OsIf_ResumeAllInterrupts();
819 #ifdef _ARM_DS5_C_S32ZE_
820 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
821 #endif
822 }
823 }
824
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_11(void)825 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_11(void)
826 {
827 uint32 msr;
828 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
829
830 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId])
831 {
832 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
833 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
834 #else
835 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
836 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
837 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
838 {
839 OsIf_SuspendAllInterrupts();
840 #ifdef _ARM_DS5_C_S32ZE_
841 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
842 #endif
843 }
844 msr_ICU_EXCLUSIVE_AREA_11[u32CoreId] = msr;
845 }
846 reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId]++;
847 }
848
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_11(void)849 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_11(void)
850 {
851 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
852
853 reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId]--;
854 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
855 {
856 OsIf_ResumeAllInterrupts();
857 #ifdef _ARM_DS5_C_S32ZE_
858 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
859 #endif
860 }
861 }
862
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_15(void)863 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_15(void)
864 {
865 uint32 msr;
866 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
867
868 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId])
869 {
870 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
871 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
872 #else
873 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
874 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
875 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
876 {
877 OsIf_SuspendAllInterrupts();
878 #ifdef _ARM_DS5_C_S32ZE_
879 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
880 #endif
881 }
882 msr_ICU_EXCLUSIVE_AREA_15[u32CoreId] = msr;
883 }
884 reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId]++;
885 }
886
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_15(void)887 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_15(void)
888 {
889 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
890
891 reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId]--;
892 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
893 {
894 OsIf_ResumeAllInterrupts();
895 #ifdef _ARM_DS5_C_S32ZE_
896 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
897 #endif
898 }
899 }
900
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_16(void)901 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_16(void)
902 {
903 uint32 msr;
904 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
905
906 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId])
907 {
908 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
909 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
910 #else
911 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
912 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
913 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
914 {
915 OsIf_SuspendAllInterrupts();
916 #ifdef _ARM_DS5_C_S32ZE_
917 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
918 #endif
919 }
920 msr_ICU_EXCLUSIVE_AREA_16[u32CoreId] = msr;
921 }
922 reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId]++;
923 }
924
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_16(void)925 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_16(void)
926 {
927 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
928
929 reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId]--;
930 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
931 {
932 OsIf_ResumeAllInterrupts();
933 #ifdef _ARM_DS5_C_S32ZE_
934 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
935 #endif
936 }
937 }
938
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_17(void)939 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_17(void)
940 {
941 uint32 msr;
942 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
943
944 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId])
945 {
946 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
947 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
948 #else
949 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
950 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
951 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
952 {
953 OsIf_SuspendAllInterrupts();
954 #ifdef _ARM_DS5_C_S32ZE_
955 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
956 #endif
957 }
958 msr_ICU_EXCLUSIVE_AREA_17[u32CoreId] = msr;
959 }
960 reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId]++;
961 }
962
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_17(void)963 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_17(void)
964 {
965 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
966
967 reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId]--;
968 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
969 {
970 OsIf_ResumeAllInterrupts();
971 #ifdef _ARM_DS5_C_S32ZE_
972 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
973 #endif
974 }
975 }
976
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_18(void)977 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_18(void)
978 {
979 uint32 msr;
980 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
981
982 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId])
983 {
984 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
985 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
986 #else
987 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
988 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
989 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
990 {
991 OsIf_SuspendAllInterrupts();
992 #ifdef _ARM_DS5_C_S32ZE_
993 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
994 #endif
995 }
996 msr_ICU_EXCLUSIVE_AREA_18[u32CoreId] = msr;
997 }
998 reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId]++;
999 }
1000
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_18(void)1001 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_18(void)
1002 {
1003 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1004
1005 reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId]--;
1006 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1007 {
1008 OsIf_ResumeAllInterrupts();
1009 #ifdef _ARM_DS5_C_S32ZE_
1010 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1011 #endif
1012 }
1013 }
1014
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_19(void)1015 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_19(void)
1016 {
1017 uint32 msr;
1018 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1019
1020 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId])
1021 {
1022 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1023 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1024 #else
1025 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1026 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1027 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1028 {
1029 OsIf_SuspendAllInterrupts();
1030 #ifdef _ARM_DS5_C_S32ZE_
1031 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1032 #endif
1033 }
1034 msr_ICU_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1035 }
1036 reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId]++;
1037 }
1038
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_19(void)1039 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_19(void)
1040 {
1041 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1042
1043 reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId]--;
1044 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1045 {
1046 OsIf_ResumeAllInterrupts();
1047 #ifdef _ARM_DS5_C_S32ZE_
1048 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1049 #endif
1050 }
1051 }
1052
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_20(void)1053 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_20(void)
1054 {
1055 uint32 msr;
1056 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1057
1058 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId])
1059 {
1060 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1061 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1062 #else
1063 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1064 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1065 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1066 {
1067 OsIf_SuspendAllInterrupts();
1068 #ifdef _ARM_DS5_C_S32ZE_
1069 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1070 #endif
1071 }
1072 msr_ICU_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1073 }
1074 reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId]++;
1075 }
1076
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_20(void)1077 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_20(void)
1078 {
1079 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1080
1081 reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId]--;
1082 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1083 {
1084 OsIf_ResumeAllInterrupts();
1085 #ifdef _ARM_DS5_C_S32ZE_
1086 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1087 #endif
1088 }
1089 }
1090
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_21(void)1091 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_21(void)
1092 {
1093 uint32 msr;
1094 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1095
1096 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId])
1097 {
1098 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1099 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1100 #else
1101 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1102 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1103 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1104 {
1105 OsIf_SuspendAllInterrupts();
1106 #ifdef _ARM_DS5_C_S32ZE_
1107 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1108 #endif
1109 }
1110 msr_ICU_EXCLUSIVE_AREA_21[u32CoreId] = msr;
1111 }
1112 reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId]++;
1113 }
1114
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_21(void)1115 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_21(void)
1116 {
1117 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1118
1119 reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId]--;
1120 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
1121 {
1122 OsIf_ResumeAllInterrupts();
1123 #ifdef _ARM_DS5_C_S32ZE_
1124 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1125 #endif
1126 }
1127 }
1128
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_22(void)1129 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_22(void)
1130 {
1131 uint32 msr;
1132 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1133
1134 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId])
1135 {
1136 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1137 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1138 #else
1139 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1140 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1141 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1142 {
1143 OsIf_SuspendAllInterrupts();
1144 #ifdef _ARM_DS5_C_S32ZE_
1145 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1146 #endif
1147 }
1148 msr_ICU_EXCLUSIVE_AREA_22[u32CoreId] = msr;
1149 }
1150 reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId]++;
1151 }
1152
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_22(void)1153 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_22(void)
1154 {
1155 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1156
1157 reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId]--;
1158 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
1159 {
1160 OsIf_ResumeAllInterrupts();
1161 #ifdef _ARM_DS5_C_S32ZE_
1162 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1163 #endif
1164 }
1165 }
1166
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_23(void)1167 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_23(void)
1168 {
1169 uint32 msr;
1170 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1171
1172 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId])
1173 {
1174 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1175 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1176 #else
1177 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1178 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1179 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1180 {
1181 OsIf_SuspendAllInterrupts();
1182 #ifdef _ARM_DS5_C_S32ZE_
1183 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1184 #endif
1185 }
1186 msr_ICU_EXCLUSIVE_AREA_23[u32CoreId] = msr;
1187 }
1188 reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId]++;
1189 }
1190
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_23(void)1191 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_23(void)
1192 {
1193 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1194
1195 reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId]--;
1196 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
1197 {
1198 OsIf_ResumeAllInterrupts();
1199 #ifdef _ARM_DS5_C_S32ZE_
1200 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1201 #endif
1202 }
1203 }
1204
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_24(void)1205 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_24(void)
1206 {
1207 uint32 msr;
1208 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1209
1210 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId])
1211 {
1212 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1213 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1214 #else
1215 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1216 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1217 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1218 {
1219 OsIf_SuspendAllInterrupts();
1220 #ifdef _ARM_DS5_C_S32ZE_
1221 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1222 #endif
1223 }
1224 msr_ICU_EXCLUSIVE_AREA_24[u32CoreId] = msr;
1225 }
1226 reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId]++;
1227 }
1228
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_24(void)1229 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_24(void)
1230 {
1231 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1232
1233 reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId]--;
1234 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId])) /*if interrupts were enabled*/
1235 {
1236 OsIf_ResumeAllInterrupts();
1237 #ifdef _ARM_DS5_C_S32ZE_
1238 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1239 #endif
1240 }
1241 }
1242
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_25(void)1243 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_25(void)
1244 {
1245 uint32 msr;
1246 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1247
1248 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId])
1249 {
1250 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1251 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1252 #else
1253 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1254 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1255 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1256 {
1257 OsIf_SuspendAllInterrupts();
1258 #ifdef _ARM_DS5_C_S32ZE_
1259 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1260 #endif
1261 }
1262 msr_ICU_EXCLUSIVE_AREA_25[u32CoreId] = msr;
1263 }
1264 reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId]++;
1265 }
1266
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_25(void)1267 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_25(void)
1268 {
1269 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1270
1271 reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId]--;
1272 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId])) /*if interrupts were enabled*/
1273 {
1274 OsIf_ResumeAllInterrupts();
1275 #ifdef _ARM_DS5_C_S32ZE_
1276 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1277 #endif
1278 }
1279 }
1280
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_26(void)1281 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_26(void)
1282 {
1283 uint32 msr;
1284 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1285
1286 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId])
1287 {
1288 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1289 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1290 #else
1291 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1292 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1293 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1294 {
1295 OsIf_SuspendAllInterrupts();
1296 #ifdef _ARM_DS5_C_S32ZE_
1297 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1298 #endif
1299 }
1300 msr_ICU_EXCLUSIVE_AREA_26[u32CoreId] = msr;
1301 }
1302 reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId]++;
1303 }
1304
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_26(void)1305 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_26(void)
1306 {
1307 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1308
1309 reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId]--;
1310 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId])) /*if interrupts were enabled*/
1311 {
1312 OsIf_ResumeAllInterrupts();
1313 #ifdef _ARM_DS5_C_S32ZE_
1314 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1315 #endif
1316 }
1317 }
1318
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_27(void)1319 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_27(void)
1320 {
1321 uint32 msr;
1322 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1323
1324 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId])
1325 {
1326 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1327 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1328 #else
1329 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1330 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1331 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1332 {
1333 OsIf_SuspendAllInterrupts();
1334 #ifdef _ARM_DS5_C_S32ZE_
1335 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1336 #endif
1337 }
1338 msr_ICU_EXCLUSIVE_AREA_27[u32CoreId] = msr;
1339 }
1340 reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId]++;
1341 }
1342
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_27(void)1343 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_27(void)
1344 {
1345 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1346
1347 reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId]--;
1348 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId])) /*if interrupts were enabled*/
1349 {
1350 OsIf_ResumeAllInterrupts();
1351 #ifdef _ARM_DS5_C_S32ZE_
1352 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1353 #endif
1354 }
1355 }
1356
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_28(void)1357 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_28(void)
1358 {
1359 uint32 msr;
1360 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1361
1362 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId])
1363 {
1364 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1365 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1366 #else
1367 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1368 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1369 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1370 {
1371 OsIf_SuspendAllInterrupts();
1372 #ifdef _ARM_DS5_C_S32ZE_
1373 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1374 #endif
1375 }
1376 msr_ICU_EXCLUSIVE_AREA_28[u32CoreId] = msr;
1377 }
1378 reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId]++;
1379 }
1380
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_28(void)1381 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_28(void)
1382 {
1383 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1384
1385 reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId]--;
1386 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_28[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId])) /*if interrupts were enabled*/
1387 {
1388 OsIf_ResumeAllInterrupts();
1389 #ifdef _ARM_DS5_C_S32ZE_
1390 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1391 #endif
1392 }
1393 }
1394
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_29(void)1395 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_29(void)
1396 {
1397 uint32 msr;
1398 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1399
1400 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId])
1401 {
1402 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1403 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1404 #else
1405 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1406 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1407 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1408 {
1409 OsIf_SuspendAllInterrupts();
1410 #ifdef _ARM_DS5_C_S32ZE_
1411 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1412 #endif
1413 }
1414 msr_ICU_EXCLUSIVE_AREA_29[u32CoreId] = msr;
1415 }
1416 reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId]++;
1417 }
1418
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_29(void)1419 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_29(void)
1420 {
1421 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1422
1423 reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId]--;
1424 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_29[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId])) /*if interrupts were enabled*/
1425 {
1426 OsIf_ResumeAllInterrupts();
1427 #ifdef _ARM_DS5_C_S32ZE_
1428 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1429 #endif
1430 }
1431 }
1432
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_30(void)1433 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_30(void)
1434 {
1435 uint32 msr;
1436 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1437
1438 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId])
1439 {
1440 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1441 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1442 #else
1443 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1444 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1445 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1446 {
1447 OsIf_SuspendAllInterrupts();
1448 #ifdef _ARM_DS5_C_S32ZE_
1449 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1450 #endif
1451 }
1452 msr_ICU_EXCLUSIVE_AREA_30[u32CoreId] = msr;
1453 }
1454 reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId]++;
1455 }
1456
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_30(void)1457 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_30(void)
1458 {
1459 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1460
1461 reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId]--;
1462 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_30[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId])) /*if interrupts were enabled*/
1463 {
1464 OsIf_ResumeAllInterrupts();
1465 #ifdef _ARM_DS5_C_S32ZE_
1466 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1467 #endif
1468 }
1469 }
1470
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_31(void)1471 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_31(void)
1472 {
1473 uint32 msr;
1474 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1475
1476 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId])
1477 {
1478 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1479 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1480 #else
1481 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1482 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1483 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1484 {
1485 OsIf_SuspendAllInterrupts();
1486 #ifdef _ARM_DS5_C_S32ZE_
1487 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1488 #endif
1489 }
1490 msr_ICU_EXCLUSIVE_AREA_31[u32CoreId] = msr;
1491 }
1492 reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId]++;
1493 }
1494
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_31(void)1495 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_31(void)
1496 {
1497 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1498
1499 reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId]--;
1500 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_31[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId])) /*if interrupts were enabled*/
1501 {
1502 OsIf_ResumeAllInterrupts();
1503 #ifdef _ARM_DS5_C_S32ZE_
1504 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1505 #endif
1506 }
1507 }
1508
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_32(void)1509 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_32(void)
1510 {
1511 uint32 msr;
1512 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1513
1514 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId])
1515 {
1516 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1517 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1518 #else
1519 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1520 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1521 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1522 {
1523 OsIf_SuspendAllInterrupts();
1524 #ifdef _ARM_DS5_C_S32ZE_
1525 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1526 #endif
1527 }
1528 msr_ICU_EXCLUSIVE_AREA_32[u32CoreId] = msr;
1529 }
1530 reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId]++;
1531 }
1532
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_32(void)1533 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_32(void)
1534 {
1535 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1536
1537 reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId]--;
1538 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_32[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId])) /*if interrupts were enabled*/
1539 {
1540 OsIf_ResumeAllInterrupts();
1541 #ifdef _ARM_DS5_C_S32ZE_
1542 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1543 #endif
1544 }
1545 }
1546
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_33(void)1547 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_33(void)
1548 {
1549 uint32 msr;
1550 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1551
1552 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId])
1553 {
1554 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1555 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1556 #else
1557 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1558 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1559 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1560 {
1561 OsIf_SuspendAllInterrupts();
1562 #ifdef _ARM_DS5_C_S32ZE_
1563 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1564 #endif
1565 }
1566 msr_ICU_EXCLUSIVE_AREA_33[u32CoreId] = msr;
1567 }
1568 reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId]++;
1569 }
1570
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_33(void)1571 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_33(void)
1572 {
1573 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1574
1575 reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId]--;
1576 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_33[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId])) /*if interrupts were enabled*/
1577 {
1578 OsIf_ResumeAllInterrupts();
1579 #ifdef _ARM_DS5_C_S32ZE_
1580 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1581 #endif
1582 }
1583 }
1584
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_44(void)1585 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_44(void)
1586 {
1587 uint32 msr;
1588 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1589
1590 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId])
1591 {
1592 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1593 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1594 #else
1595 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1596 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1597 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1598 {
1599 OsIf_SuspendAllInterrupts();
1600 #ifdef _ARM_DS5_C_S32ZE_
1601 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1602 #endif
1603 }
1604 msr_ICU_EXCLUSIVE_AREA_44[u32CoreId] = msr;
1605 }
1606 reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId]++;
1607 }
1608
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_44(void)1609 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_44(void)
1610 {
1611 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1612
1613 reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId]--;
1614 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_44[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId])) /*if interrupts were enabled*/
1615 {
1616 OsIf_ResumeAllInterrupts();
1617 #ifdef _ARM_DS5_C_S32ZE_
1618 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1619 #endif
1620 }
1621 }
1622
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_45(void)1623 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_45(void)
1624 {
1625 uint32 msr;
1626 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1627
1628 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId])
1629 {
1630 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1631 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1632 #else
1633 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1634 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1635 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1636 {
1637 OsIf_SuspendAllInterrupts();
1638 #ifdef _ARM_DS5_C_S32ZE_
1639 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1640 #endif
1641 }
1642 msr_ICU_EXCLUSIVE_AREA_45[u32CoreId] = msr;
1643 }
1644 reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId]++;
1645 }
1646
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_45(void)1647 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_45(void)
1648 {
1649 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1650
1651 reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId]--;
1652 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_45[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId])) /*if interrupts were enabled*/
1653 {
1654 OsIf_ResumeAllInterrupts();
1655 #ifdef _ARM_DS5_C_S32ZE_
1656 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1657 #endif
1658 }
1659 }
1660
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_46(void)1661 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_46(void)
1662 {
1663 uint32 msr;
1664 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1665
1666 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId])
1667 {
1668 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1669 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1670 #else
1671 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1672 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1673 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1674 {
1675 OsIf_SuspendAllInterrupts();
1676 #ifdef _ARM_DS5_C_S32ZE_
1677 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1678 #endif
1679 }
1680 msr_ICU_EXCLUSIVE_AREA_46[u32CoreId] = msr;
1681 }
1682 reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId]++;
1683 }
1684
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_46(void)1685 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_46(void)
1686 {
1687 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1688
1689 reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId]--;
1690 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_46[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId])) /*if interrupts were enabled*/
1691 {
1692 OsIf_ResumeAllInterrupts();
1693 #ifdef _ARM_DS5_C_S32ZE_
1694 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1695 #endif
1696 }
1697 }
1698
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_47(void)1699 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_47(void)
1700 {
1701 uint32 msr;
1702 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1703
1704 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId])
1705 {
1706 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1707 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1708 #else
1709 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1710 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1711 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1712 {
1713 OsIf_SuspendAllInterrupts();
1714 #ifdef _ARM_DS5_C_S32ZE_
1715 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1716 #endif
1717 }
1718 msr_ICU_EXCLUSIVE_AREA_47[u32CoreId] = msr;
1719 }
1720 reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId]++;
1721 }
1722
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_47(void)1723 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_47(void)
1724 {
1725 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1726
1727 reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId]--;
1728 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_47[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId])) /*if interrupts were enabled*/
1729 {
1730 OsIf_ResumeAllInterrupts();
1731 #ifdef _ARM_DS5_C_S32ZE_
1732 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1733 #endif
1734 }
1735 }
1736
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_48(void)1737 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_48(void)
1738 {
1739 uint32 msr;
1740 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1741
1742 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId])
1743 {
1744 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1745 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1746 #else
1747 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1748 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1749 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1750 {
1751 OsIf_SuspendAllInterrupts();
1752 #ifdef _ARM_DS5_C_S32ZE_
1753 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1754 #endif
1755 }
1756 msr_ICU_EXCLUSIVE_AREA_48[u32CoreId] = msr;
1757 }
1758 reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId]++;
1759 }
1760
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_48(void)1761 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_48(void)
1762 {
1763 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1764
1765 reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId]--;
1766 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_48[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId])) /*if interrupts were enabled*/
1767 {
1768 OsIf_ResumeAllInterrupts();
1769 #ifdef _ARM_DS5_C_S32ZE_
1770 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1771 #endif
1772 }
1773 }
1774
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_49(void)1775 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_49(void)
1776 {
1777 uint32 msr;
1778 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1779
1780 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId])
1781 {
1782 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1783 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1784 #else
1785 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1786 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1787 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1788 {
1789 OsIf_SuspendAllInterrupts();
1790 #ifdef _ARM_DS5_C_S32ZE_
1791 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1792 #endif
1793 }
1794 msr_ICU_EXCLUSIVE_AREA_49[u32CoreId] = msr;
1795 }
1796 reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId]++;
1797 }
1798
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_49(void)1799 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_49(void)
1800 {
1801 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1802
1803 reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId]--;
1804 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_49[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId])) /*if interrupts were enabled*/
1805 {
1806 OsIf_ResumeAllInterrupts();
1807 #ifdef _ARM_DS5_C_S32ZE_
1808 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1809 #endif
1810 }
1811 }
1812
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_50(void)1813 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_50(void)
1814 {
1815 uint32 msr;
1816 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1817
1818 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId])
1819 {
1820 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1821 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1822 #else
1823 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1824 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1825 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1826 {
1827 OsIf_SuspendAllInterrupts();
1828 #ifdef _ARM_DS5_C_S32ZE_
1829 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1830 #endif
1831 }
1832 msr_ICU_EXCLUSIVE_AREA_50[u32CoreId] = msr;
1833 }
1834 reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId]++;
1835 }
1836
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_50(void)1837 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_50(void)
1838 {
1839 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1840
1841 reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId]--;
1842 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_50[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId])) /*if interrupts were enabled*/
1843 {
1844 OsIf_ResumeAllInterrupts();
1845 #ifdef _ARM_DS5_C_S32ZE_
1846 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1847 #endif
1848 }
1849 }
1850
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_51(void)1851 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_51(void)
1852 {
1853 uint32 msr;
1854 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1855
1856 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId])
1857 {
1858 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1859 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1860 #else
1861 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1862 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1863 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1864 {
1865 OsIf_SuspendAllInterrupts();
1866 #ifdef _ARM_DS5_C_S32ZE_
1867 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1868 #endif
1869 }
1870 msr_ICU_EXCLUSIVE_AREA_51[u32CoreId] = msr;
1871 }
1872 reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId]++;
1873 }
1874
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_51(void)1875 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_51(void)
1876 {
1877 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1878
1879 reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId]--;
1880 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_51[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId])) /*if interrupts were enabled*/
1881 {
1882 OsIf_ResumeAllInterrupts();
1883 #ifdef _ARM_DS5_C_S32ZE_
1884 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1885 #endif
1886 }
1887 }
1888
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_52(void)1889 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_52(void)
1890 {
1891 uint32 msr;
1892 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1893
1894 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId])
1895 {
1896 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1897 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1898 #else
1899 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1900 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1901 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1902 {
1903 OsIf_SuspendAllInterrupts();
1904 #ifdef _ARM_DS5_C_S32ZE_
1905 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1906 #endif
1907 }
1908 msr_ICU_EXCLUSIVE_AREA_52[u32CoreId] = msr;
1909 }
1910 reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId]++;
1911 }
1912
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_52(void)1913 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_52(void)
1914 {
1915 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1916
1917 reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId]--;
1918 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_52[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId])) /*if interrupts were enabled*/
1919 {
1920 OsIf_ResumeAllInterrupts();
1921 #ifdef _ARM_DS5_C_S32ZE_
1922 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1923 #endif
1924 }
1925 }
1926
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_53(void)1927 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_53(void)
1928 {
1929 uint32 msr;
1930 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1931
1932 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId])
1933 {
1934 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1935 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1936 #else
1937 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1938 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1939 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1940 {
1941 OsIf_SuspendAllInterrupts();
1942 #ifdef _ARM_DS5_C_S32ZE_
1943 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1944 #endif
1945 }
1946 msr_ICU_EXCLUSIVE_AREA_53[u32CoreId] = msr;
1947 }
1948 reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId]++;
1949 }
1950
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_53(void)1951 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_53(void)
1952 {
1953 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1954
1955 reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId]--;
1956 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_53[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId])) /*if interrupts were enabled*/
1957 {
1958 OsIf_ResumeAllInterrupts();
1959 #ifdef _ARM_DS5_C_S32ZE_
1960 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1961 #endif
1962 }
1963 }
1964
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_57(void)1965 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_57(void)
1966 {
1967 uint32 msr;
1968 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1969
1970 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId])
1971 {
1972 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1973 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1974 #else
1975 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1976 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1977 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1978 {
1979 OsIf_SuspendAllInterrupts();
1980 #ifdef _ARM_DS5_C_S32ZE_
1981 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1982 #endif
1983 }
1984 msr_ICU_EXCLUSIVE_AREA_57[u32CoreId] = msr;
1985 }
1986 reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId]++;
1987 }
1988
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_57(void)1989 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_57(void)
1990 {
1991 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1992
1993 reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId]--;
1994 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_57[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId])) /*if interrupts were enabled*/
1995 {
1996 OsIf_ResumeAllInterrupts();
1997 #ifdef _ARM_DS5_C_S32ZE_
1998 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1999 #endif
2000 }
2001 }
2002
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_58(void)2003 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_58(void)
2004 {
2005 uint32 msr;
2006 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2007
2008 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId])
2009 {
2010 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2011 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
2012 #else
2013 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
2014 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2015 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2016 {
2017 OsIf_SuspendAllInterrupts();
2018 #ifdef _ARM_DS5_C_S32ZE_
2019 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2020 #endif
2021 }
2022 msr_ICU_EXCLUSIVE_AREA_58[u32CoreId] = msr;
2023 }
2024 reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId]++;
2025 }
2026
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_58(void)2027 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_58(void)
2028 {
2029 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2030
2031 reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId]--;
2032 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_58[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId])) /*if interrupts were enabled*/
2033 {
2034 OsIf_ResumeAllInterrupts();
2035 #ifdef _ARM_DS5_C_S32ZE_
2036 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2037 #endif
2038 }
2039 }
2040
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_59(void)2041 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_59(void)
2042 {
2043 uint32 msr;
2044 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2045
2046 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId])
2047 {
2048 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2049 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
2050 #else
2051 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
2052 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2053 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2054 {
2055 OsIf_SuspendAllInterrupts();
2056 #ifdef _ARM_DS5_C_S32ZE_
2057 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2058 #endif
2059 }
2060 msr_ICU_EXCLUSIVE_AREA_59[u32CoreId] = msr;
2061 }
2062 reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId]++;
2063 }
2064
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_59(void)2065 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_59(void)
2066 {
2067 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2068
2069 reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId]--;
2070 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_59[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId])) /*if interrupts were enabled*/
2071 {
2072 OsIf_ResumeAllInterrupts();
2073 #ifdef _ARM_DS5_C_S32ZE_
2074 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2075 #endif
2076 }
2077 }
2078
2079
2080 #ifdef MCAL_TESTING_ENVIRONMENT
2081 /**
2082 @brief This function checks that all entered exclusive areas were also exited.
2083 @details This function checks that all entered exclusive areas were also exited. The check
2084 is done by verifying that all reentry_guard_* static variables are back to the
2085 zero value.
2086
2087 @param[in] void No input parameters
2088 @return void This function does not return a value. Test asserts are used instead.
2089
2090 @pre None
2091 @post None
2092
2093 @remarks Covers
2094 @remarks Implements
2095 */
SchM_Check_icu(void)2096 void SchM_Check_icu(void)
2097 {
2098 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2099
2100 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId]);
2101 reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_00 for the next test in the suite*/
2102
2103 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId]);
2104 reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_01 for the next test in the suite*/
2105
2106 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId]);
2107 reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_02 for the next test in the suite*/
2108
2109 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId]);
2110 reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_03 for the next test in the suite*/
2111
2112 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId]);
2113 reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_04 for the next test in the suite*/
2114
2115 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId]);
2116 reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_05 for the next test in the suite*/
2117
2118 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId]);
2119 reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_06 for the next test in the suite*/
2120
2121 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId]);
2122 reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_07 for the next test in the suite*/
2123
2124 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId]);
2125 reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_08 for the next test in the suite*/
2126
2127 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId]);
2128 reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_09 for the next test in the suite*/
2129
2130 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId]);
2131 reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_11 for the next test in the suite*/
2132
2133 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId]);
2134 reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_15 for the next test in the suite*/
2135
2136 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId]);
2137 reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_16 for the next test in the suite*/
2138
2139 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId]);
2140 reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_17 for the next test in the suite*/
2141
2142 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId]);
2143 reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_18 for the next test in the suite*/
2144
2145 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId]);
2146 reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_19 for the next test in the suite*/
2147
2148 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId]);
2149 reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_20 for the next test in the suite*/
2150
2151 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId]);
2152 reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_21 for the next test in the suite*/
2153
2154 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId]);
2155 reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_22 for the next test in the suite*/
2156
2157 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId]);
2158 reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_23 for the next test in the suite*/
2159
2160 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId]);
2161 reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_24 for the next test in the suite*/
2162
2163 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId]);
2164 reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_25 for the next test in the suite*/
2165
2166 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId]);
2167 reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_26 for the next test in the suite*/
2168
2169 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId]);
2170 reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_27 for the next test in the suite*/
2171
2172 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId]);
2173 reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_28 for the next test in the suite*/
2174
2175 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId]);
2176 reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_29 for the next test in the suite*/
2177
2178 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId]);
2179 reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_30 for the next test in the suite*/
2180
2181 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId]);
2182 reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_31 for the next test in the suite*/
2183
2184 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId]);
2185 reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_32 for the next test in the suite*/
2186
2187 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId]);
2188 reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_33 for the next test in the suite*/
2189
2190 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId]);
2191 reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_44 for the next test in the suite*/
2192
2193 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId]);
2194 reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_45 for the next test in the suite*/
2195
2196 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId]);
2197 reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_46 for the next test in the suite*/
2198
2199 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId]);
2200 reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_47 for the next test in the suite*/
2201
2202 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId]);
2203 reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_48 for the next test in the suite*/
2204
2205 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId]);
2206 reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_49 for the next test in the suite*/
2207
2208 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId]);
2209 reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_50 for the next test in the suite*/
2210
2211 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId]);
2212 reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_51 for the next test in the suite*/
2213
2214 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId]);
2215 reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_52 for the next test in the suite*/
2216
2217 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId]);
2218 reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_53 for the next test in the suite*/
2219
2220 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId]);
2221 reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_57 for the next test in the suite*/
2222
2223 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId]);
2224 reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_58 for the next test in the suite*/
2225
2226 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId]);
2227 reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_59 for the next test in the suite*/
2228
2229
2230 }
2231 #endif /*MCAL_TESTING_ENVIRONMENT*/
2232
2233 #define RTE_STOP_SEC_CODE
2234 #include "Rte_MemMap.h"
2235
2236 #ifdef __cplusplus
2237 }
2238 #endif
2239
2240 /** @} */
2241
