1 /*
2 * Copyright 2021-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 /**
7 * @file Clock_Ip_Frequency.c
8 * @version 0.9.0
9 *
10 * @brief CLOCK driver implementations.
11 * @details CLOCK driver implementations.
12 *
13 * @addtogroup CLOCK_DRIVER Clock Ip Driver
14 * @{
15 */
16
17
18 #ifdef __cplusplus
19 extern "C"{
20 #endif
21
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Clock_Ip_Private.h"
30
31 #if defined(CLOCK_IP_PLATFORM_SPECIFIC)
32
33
34 #if (defined(CLOCK_IP_GET_FREQUENCY_API) && (CLOCK_IP_GET_FREQUENCY_API == STD_ON))
35
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define CLOCK_IP_FREQUENCY_VENDOR_ID_C 43
41 #define CLOCK_IP_FREQUENCY_AR_RELEASE_MAJOR_VERSION_C 4
42 #define CLOCK_IP_FREQUENCY_AR_RELEASE_MINOR_VERSION_C 7
43 #define CLOCK_IP_FREQUENCY_AR_RELEASE_REVISION_VERSION_C 0
44 #define CLOCK_IP_FREQUENCY_SW_MAJOR_VERSION_C 0
45 #define CLOCK_IP_FREQUENCY_SW_MINOR_VERSION_C 9
46 #define CLOCK_IP_FREQUENCY_SW_PATCH_VERSION_C 0
47
48 /*==================================================================================================
49 * FILE VERSION CHECKS
50 ==================================================================================================*/
51 /* Check if Clock_Ip_Frequency.c file and Clock_Ip_Private.h file are of the same vendor */
52 #if (CLOCK_IP_FREQUENCY_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
53 #error "Clock_Ip_Frequency.c and Clock_Ip_Private.h have different vendor ids"
54 #endif
55
56 /* Check if Clock_Ip_Frequency.c file and Clock_Ip_Private.h file are of the same Autosar version */
57 #if ((CLOCK_IP_FREQUENCY_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
58 (CLOCK_IP_FREQUENCY_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
59 (CLOCK_IP_FREQUENCY_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
60 )
61 #error "AutoSar Version Numbers of Clock_Ip_Frequency.c and Clock_Ip_Private.h are different"
62 #endif
63
64 /* Check if Clock_Ip_Frequency.c file and Clock_Ip_Private.h file are of the same Software version */
65 #if ((CLOCK_IP_FREQUENCY_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
66 (CLOCK_IP_FREQUENCY_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
67 (CLOCK_IP_FREQUENCY_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
68 )
69 #error "Software Version Numbers of Clock_Ip_Frequency.c and Clock_Ip_Private.h are different"
70 #endif
71 /*==================================================================================================
72 LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
73 ==================================================================================================*/
74
75 typedef struct{
76
77 Clock_Ip_NameType Name;
78 uint32 Frequency;
79
80 }extSignalFreq;
81
82 /*==================================================================================================
83 * LOCAL MACROS
84 ==================================================================================================*/
85
86 #define CLOCK_IP_SELECTOR_SOURCE_NO 64U
87 #define CLOCK_IP_EXT_SIGNALS_NO 8U
88 #define CLOCK_IP_DFS_MASK_0_CHANNEL 1U
89 #define CLOCK_IP_DFS_MASK_1_CHANNEL 2U
90 #define CLOCK_IP_DFS_MASK_2_CHANNEL 4U
91 #define CLOCK_IP_DFS_MASK_3_CHANNEL 8U
92 #define CLOCK_IP_DFS_MASK_4_CHANNEL 16U
93 #define CLOCK_IP_DFS_MASK_5_CHANNEL 32U
94 #define CLOCK_IP_MUL_BY_16384 14U
95 #define CLOCK_IP_MUL_BY_2048 11U
96 #define CLOCK_IP_MUL_BY_32 5U
97 #define CLOCK_IP_MUL_BY_16 4U
98 #define CLOCK_IP_MUL_BY_4 2U
99 #define CLOCK_IP_MUL_BY_2 1U
100 #define CLOCK_IP_DISABLED 0U
101 #define CLOCK_IP_ENABLED 0xFFFFFFFFU
102
103 #define CLOCK_IP_ETH_RGMII_REF_CLK_INDEX_ENTRY 0U
104 #define CLOCK_IP_ETH_EXT_TS_CLK_INDEX_ENTRY 1U
105 #define CLOCK_IP_ETH0_EXT_RX_CLK_INDEX_ENTRY 2U
106 #define CLOCK_IP_ETH0_EXT_TX_CLK_INDEX_ENTRY 3U
107 #define CLOCK_IP_ETH1_EXT_RX_CLK_INDEX_ENTRY 4U
108 #define CLOCK_IP_ETH1_EXT_TX_CLK_INDEX_ENTRY 5U
109 #define CLOCK_IP_LFAST0_EXT_REF_CLK_INDEX_ENTRY 6U
110 #define CLOCK_IP_LFAST1_EXT_REF_CLK_INDEX_ENTRY 7U
111
112
113 #define CLOCK_IP_CLKOUT_INDEX0 0U
114 #define CLOCK_IP_CLKOUT_INDEX1 1U
115 #define CLOCK_IP_CLKOUT_INDEX2 2U
116 #define CLOCK_IP_CLKOUT_INDEX3 3U
117 #define CLOCK_IP_CLKOUT_INDEX4 4U
118 #define CLOCK_IP_CLKOUT_NO 5U
119
120
121 #define CLOCK_IP_CLKPSI5_S_UTIL_INDEX0 0U
122 #define CLOCK_IP_CLKPSI5_S_UTIL_INDEX1 1U
123 #define CLOCK_IP_CLKPSI5_S_UTIL_NO 2U
124
125
126 #define CLOCK_IP_COREPLL_FREQ 2000000000U
127 #define CLOCK_IP_COREPLL_CHECKSUM 4147U
128 #define CLOCK_IP_PERIPHPLL_FREQ 2000000000U
129 #define CLOCK_IP_PERIPHPLL_CHECKSUM 4147U
130 #define CLOCK_IP_DDRPLL_FREQ 1600000000U
131 #define CLOCK_IP_DDRPLL_CHECKSUM 4137U
132 #define CLOCK_IP_COREDFS1_FREQ 800000000U
133 #define CLOCK_IP_COREDFS1_CHECKSUM 5694U
134 #define CLOCK_IP_COREDFS2_FREQ 800000000U
135 #define CLOCK_IP_COREDFS2_CHECKSUM 5694U
136 #define CLOCK_IP_COREDFS3_FREQ 0U
137 #define CLOCK_IP_COREDFS3_CHECKSUM 5943U
138 #define CLOCK_IP_COREDFS4_FREQ 0U
139 #define CLOCK_IP_COREDFS4_CHECKSUM 5943U
140 #define CLOCK_IP_COREDFS5_FREQ 0U
141 #define CLOCK_IP_COREDFS5_CHECKSUM 5943U
142 #define CLOCK_IP_COREDFS6_FREQ 0U
143 #define CLOCK_IP_COREDFS6_CHECKSUM 5943U
144 #define CLOCK_IP_PERIPHDFS1_FREQ 800000000U
145 #define CLOCK_IP_PERIPHDFS1_CHECKSUM 5694U
146 #define CLOCK_IP_PERIPHDFS2_FREQ 631578947U
147 #define CLOCK_IP_PERIPHDFS2_CHECKSUM 5666U
148 #define CLOCK_IP_PERIPHDFS3_FREQ 0U
149 #define CLOCK_IP_PERIPHDFS3_CHECKSUM 5943U
150 #define CLOCK_IP_PERIPHDFS4_FREQ 1000000000U
151 #define CLOCK_IP_PERIPHDFS4_CHECKSUM 5687U
152 #define CLOCK_IP_PERIPHDFS5_FREQ 1000000000U
153 #define CLOCK_IP_PERIPHDFS5_CHECKSUM 5687U
154 #define CLOCK_IP_PERIPHDFS6_FREQ 1000000000U
155 #define CLOCK_IP_PERIPHDFS6_CHECKSUM 5687U
156
157 /*==================================================================================================
158 GLOBAL FUNCTION PROTOTYPES
159 ==================================================================================================*/
160
161 /*==================================================================================================
162 LOCAL FUNCTION PROTOTYPES
163 ==================================================================================================*/
164 /* Clock start section code */
165 #define MCU_START_SEC_CODE
166 #include "Mcu_MemMap.h"
167
168 static uint32 PLL_VCO(const PLLDIG_Type *Base);
169 static uint32 LFAST_PLL_VCO(const LFAST_Type *Base);
170 static uint32 DFS_OUTPUT(const DFS_Type *Base, uint32 Channel, uint32 Fin);
171 static uint32 Clock_Ip_Get_Zero_Frequency(void);
172 static uint32 Clock_Ip_Get_FIRC_CLK_Frequency(void);
173 static uint32 Clock_Ip_Get_FXOSC_CLK_Frequency(void);
174 static uint32 Clock_Ip_Get_SIRC_CLK_Frequency(void);
175 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK)
176 static uint32 Clock_Ip_Get_FIRC_AE_CLK_Frequency(void);
177 #endif
178 static uint32 Clock_Ip_Get_COREPLL_CLK_Frequency(void);
179 static uint32 Clock_Ip_Get_PERIPHPLL_CLK_Frequency(void);
180 static uint32 Clock_Ip_Get_DDRPLL_CLK_Frequency(void);
181 static uint32 Clock_Ip_Get_LFAST0_PLL_CLK_Frequency(void);
182 static uint32 Clock_Ip_Get_LFAST1_PLL_CLK_Frequency(void);
183 static uint32 Clock_Ip_Get_COREPLL_PHI0_Frequency(void);
184 static uint32 Clock_Ip_Get_COREPLL_DFS0_Frequency(void);
185 static uint32 Clock_Ip_Get_COREPLL_DFS1_Frequency(void);
186 static uint32 Clock_Ip_Get_COREPLL_DFS2_Frequency(void);
187 static uint32 Clock_Ip_Get_COREPLL_DFS3_Frequency(void);
188 static uint32 Clock_Ip_Get_COREPLL_DFS4_Frequency(void);
189 static uint32 Clock_Ip_Get_COREPLL_DFS5_Frequency(void);
190 static uint32 Clock_Ip_Get_PERIPHPLL_PHI0_Frequency(void);
191 static uint32 Clock_Ip_Get_PERIPHPLL_PHI1_Frequency(void);
192 static uint32 Clock_Ip_Get_PERIPHPLL_PHI2_Frequency(void);
193 static uint32 Clock_Ip_Get_PERIPHPLL_PHI3_Frequency(void);
194 static uint32 Clock_Ip_Get_PERIPHPLL_PHI4_Frequency(void);
195 static uint32 Clock_Ip_Get_PERIPHPLL_PHI5_Frequency(void);
196 static uint32 Clock_Ip_Get_PERIPHPLL_PHI6_Frequency(void);
197 static uint32 Clock_Ip_Get_PERIPHPLL_DFS0_Frequency(void);
198 static uint32 Clock_Ip_Get_PERIPHPLL_DFS1_Frequency(void);
199 static uint32 Clock_Ip_Get_PERIPHPLL_DFS2_Frequency(void);
200 static uint32 Clock_Ip_Get_PERIPHPLL_DFS3_Frequency(void);
201 static uint32 Clock_Ip_Get_PERIPHPLL_DFS4_Frequency(void);
202 static uint32 Clock_Ip_Get_PERIPHPLL_DFS5_Frequency(void);
203 static uint32 Clock_Ip_Get_DDRPLL_PHI0_Frequency(void);
204 static uint32 Clock_Ip_Get_eth_rgmii_ref_Frequency(void);
205 static uint32 Clock_Ip_Get_eth_ext_ts_Frequency(void);
206 static uint32 Clock_Ip_Get_eth0_ext_rx_Frequency(void);
207 static uint32 Clock_Ip_Get_eth0_ext_tx_Frequency(void);
208 static uint32 Clock_Ip_Get_eth1_ext_rx_Frequency(void);
209 static uint32 Clock_Ip_Get_eth1_ext_tx_Frequency(void);
210 static uint32 Clock_Ip_Get_lfast0_ext_ref_Frequency(void);
211 static uint32 Clock_Ip_Get_lfast1_ext_ref_Frequency(void);
212 static uint32 Clock_Ip_Get_DDR_CLK_Frequency(void);
213 static uint32 Clock_Ip_Get_P0_SYS_CLK_Frequency(void);
214 static uint32 Clock_Ip_Get_P1_SYS_CLK_Frequency(void);
215 static uint32 Clock_Ip_Get_P1_SYS_DIV2_CLK_Frequency(void);
216 static uint32 Clock_Ip_Get_P1_SYS_DIV4_CLK_Frequency(void);
217 static uint32 Clock_Ip_Get_P2_SYS_CLK_Frequency(void);
218 static uint32 Clock_Ip_Get_P2_SYS_DIV2_CLK_Frequency(void);
219 static uint32 Clock_Ip_Get_P2_SYS_DIV4_CLK_Frequency(void);
220 static uint32 Clock_Ip_Get_P3_SYS_CLK_Frequency(void);
221 static uint32 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency(void);
222 static uint32 Clock_Ip_Get_P3_SYS_DIV2_NOC_CLK_Frequency(void);
223 static uint32 Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency(void);
224 static uint32 Clock_Ip_Get_P4_SYS_CLK_Frequency(void);
225 static uint32 Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency(void);
226 static uint32 Clock_Ip_Get_HSE_SYS_DIV2_CLK_Frequency(void);
227 static uint32 Clock_Ip_Get_P5_SYS_CLK_Frequency(void);
228 static uint32 Clock_Ip_Get_P5_SYS_DIV2_CLK_Frequency(void);
229 static uint32 Clock_Ip_Get_P5_SYS_DIV4_CLK_Frequency(void);
230 static uint32 Clock_Ip_Get_P2_MATH_CLK_Frequency(void);
231 static uint32 Clock_Ip_Get_P2_MATH_DIV3_CLK_Frequency(void);
232 static uint32 Clock_Ip_Get_GLB_LBIST_CLK_Frequency(void);
233 static uint32 Clock_Ip_Get_RTU0_CORE_CLK_Frequency(void);
234 static uint32 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency(void);
235 static uint32 Clock_Ip_Get_RTU1_CORE_CLK_Frequency(void);
236 static uint32 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency(void);
237 static uint32 Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency(void);
238 static uint32 Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency(void);
239 #if defined(CLOCK_IP_HAS_SYSTEM_CLK)
240 static uint32 Clock_Ip_Get_SYSTEM_CLK_Frequency(void);
241 #endif
242 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK)
243 static uint32 Clock_Ip_Get_SYSTEM_DIV2_CLK_Frequency(void);
244 #endif
245 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK)
246 static uint32 Clock_Ip_Get_SYSTEM_DIV4_CLK_Frequency(void);
247 #endif
248 static uint32 Clock_Ip_Get_ADC0_CLK_Frequency(void);
249 static uint32 Clock_Ip_Get_ADC1_CLK_Frequency(void);
250 static uint32 Clock_Ip_Get_CE_EDMA_CLK_Frequency(void);
251 static uint32 Clock_Ip_Get_CE_PIT0_CLK_Frequency(void);
252 static uint32 Clock_Ip_Get_CE_PIT1_CLK_Frequency(void);
253 static uint32 Clock_Ip_Get_CE_PIT2_CLK_Frequency(void);
254 static uint32 Clock_Ip_Get_CE_PIT3_CLK_Frequency(void);
255 static uint32 Clock_Ip_Get_CE_PIT4_CLK_Frequency(void);
256 static uint32 Clock_Ip_Get_CE_PIT5_CLK_Frequency(void);
257 static uint32 Clock_Ip_Get_CTU_CLK_Frequency(void);
258 static uint32 Clock_Ip_Get_DMACRC0_CLK_Frequency(void);
259 static uint32 Clock_Ip_Get_DMACRC1_CLK_Frequency(void);
260 static uint32 Clock_Ip_Get_DMACRC4_CLK_Frequency(void);
261 static uint32 Clock_Ip_Get_DMACRC5_CLK_Frequency(void);
262 static uint32 Clock_Ip_Get_DMAMUX0_CLK_Frequency(void);
263 static uint32 Clock_Ip_Get_DMAMUX1_CLK_Frequency(void);
264 static uint32 Clock_Ip_Get_DMAMUX4_CLK_Frequency(void);
265 static uint32 Clock_Ip_Get_DMAMUX5_CLK_Frequency(void);
266 static uint32 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency(void);
267 static uint32 Clock_Ip_Get_CLKOUT0_CLK_Frequency(void);
268 static uint32 Clock_Ip_Get_CLKOUT1_CLK_Frequency(void);
269 static uint32 Clock_Ip_Get_CLKOUT2_CLK_Frequency(void);
270 static uint32 Clock_Ip_Get_CLKOUT3_CLK_Frequency(void);
271 static uint32 Clock_Ip_Get_CLKOUT4_CLK_Frequency(void);
272 static uint32 Clock_Ip_Get_EDMA0_CLK_Frequency(void);
273 static uint32 Clock_Ip_Get_EDMA1_CLK_Frequency(void);
274 static uint32 Clock_Ip_Get_EDMA3_CLK_Frequency(void);
275 static uint32 Clock_Ip_Get_EDMA4_CLK_Frequency(void);
276 static uint32 Clock_Ip_Get_EDMA5_CLK_Frequency(void);
277 static uint32 Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency(void);
278 static uint32 Clock_Ip_Get_ENET0_CLK_Frequency(void);
279 static uint32 Clock_Ip_Get_P3_CAN_PE_CLK_Frequency(void);
280 static uint32 Clock_Ip_Get_FLEXCAN0_CLK_Frequency(void);
281 static uint32 Clock_Ip_Get_FLEXCAN1_CLK_Frequency(void);
282 static uint32 Clock_Ip_Get_FLEXCAN2_CLK_Frequency(void);
283 static uint32 Clock_Ip_Get_FLEXCAN3_CLK_Frequency(void);
284 static uint32 Clock_Ip_Get_FLEXCAN4_CLK_Frequency(void);
285 static uint32 Clock_Ip_Get_FLEXCAN5_CLK_Frequency(void);
286 static uint32 Clock_Ip_Get_FLEXCAN6_CLK_Frequency(void);
287 static uint32 Clock_Ip_Get_FLEXCAN7_CLK_Frequency(void);
288 static uint32 Clock_Ip_Get_FLEXCAN8_CLK_Frequency(void);
289 static uint32 Clock_Ip_Get_FLEXCAN9_CLK_Frequency(void);
290 static uint32 Clock_Ip_Get_FLEXCAN10_CLK_Frequency(void);
291 static uint32 Clock_Ip_Get_FLEXCAN11_CLK_Frequency(void);
292 static uint32 Clock_Ip_Get_FLEXCAN12_CLK_Frequency(void);
293 static uint32 Clock_Ip_Get_FLEXCAN13_CLK_Frequency(void);
294 static uint32 Clock_Ip_Get_FLEXCAN14_CLK_Frequency(void);
295 static uint32 Clock_Ip_Get_FLEXCAN15_CLK_Frequency(void);
296 static uint32 Clock_Ip_Get_FLEXCAN16_CLK_Frequency(void);
297 static uint32 Clock_Ip_Get_FLEXCAN17_CLK_Frequency(void);
298 static uint32 Clock_Ip_Get_FLEXCAN18_CLK_Frequency(void);
299 static uint32 Clock_Ip_Get_FLEXCAN19_CLK_Frequency(void);
300 static uint32 Clock_Ip_Get_FLEXCAN20_CLK_Frequency(void);
301 static uint32 Clock_Ip_Get_FLEXCAN21_CLK_Frequency(void);
302 static uint32 Clock_Ip_Get_FLEXCAN22_CLK_Frequency(void);
303 static uint32 Clock_Ip_Get_FLEXCAN23_CLK_Frequency(void);
304 static uint32 Clock_Ip_Get_P0_FR_PE_CLK_Frequency(void);
305 static uint32 Clock_Ip_Get_FRAY0_CLK_Frequency(void);
306 static uint32 Clock_Ip_Get_FRAY1_CLK_Frequency(void);
307 static uint32 Clock_Ip_Get_GTM_CLK_Frequency(void);
308 static uint32 Clock_Ip_Get_IIIC0_CLK_Frequency(void);
309 static uint32 Clock_Ip_Get_IIIC1_CLK_Frequency(void);
310 static uint32 Clock_Ip_Get_IIIC2_CLK_Frequency(void);
311 static uint32 Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency(void);
312 static uint32 Clock_Ip_Get_LIN0_CLK_Frequency(void);
313 static uint32 Clock_Ip_Get_LIN1_CLK_Frequency(void);
314 static uint32 Clock_Ip_Get_LIN2_CLK_Frequency(void);
315 static uint32 Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency(void);
316 static uint32 Clock_Ip_Get_LIN3_CLK_Frequency(void);
317 static uint32 Clock_Ip_Get_LIN4_CLK_Frequency(void);
318 static uint32 Clock_Ip_Get_LIN5_CLK_Frequency(void);
319 static uint32 Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency(void);
320 static uint32 Clock_Ip_Get_LIN6_CLK_Frequency(void);
321 static uint32 Clock_Ip_Get_LIN7_CLK_Frequency(void);
322 static uint32 Clock_Ip_Get_LIN8_CLK_Frequency(void);
323 static uint32 Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency(void);
324 static uint32 Clock_Ip_Get_LIN9_CLK_Frequency(void);
325 static uint32 Clock_Ip_Get_LIN10_CLK_Frequency(void);
326 static uint32 Clock_Ip_Get_LIN11_CLK_Frequency(void);
327 static uint32 Clock_Ip_Get_MSCDSPI_CLK_Frequency(void);
328 static uint32 Clock_Ip_Get_MSCLIN_CLK_Frequency(void);
329 static uint32 Clock_Ip_Get_NANO_CLK_Frequency(void);
330 static uint32 Clock_Ip_Get_P0_CLKOUT_SRC_CLK_Frequency(void);
331 static uint32 Clock_Ip_Get_P0_CTU_PER_CLK_Frequency(void);
332 static uint32 Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency(void);
333 static uint32 Clock_Ip_Get_P0_EMIOS_LCU_CLK_Frequency(void);
334 static uint32 Clock_Ip_Get_P0_GTM_CLK_Frequency(void);
335 static uint32 Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency(void);
336 static uint32 Clock_Ip_Get_P0_GTM_TS_CLK_Frequency(void);
337 static uint32 Clock_Ip_Get_P0_LIN_CLK_Frequency(void);
338 static uint32 Clock_Ip_Get_P0_NANO_CLK_Frequency(void);
339 static uint32 Clock_Ip_Get_P0_PSI5_125K_CLK_Frequency(void);
340 static uint32 Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency(void);
341 static uint32 Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency(void);
342 static uint32 Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency(void);
343 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG0_CLK_Frequency(void);
344 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG1_CLK_Frequency(void);
345 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG2_CLK_Frequency(void);
346 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG3_CLK_Frequency(void);
347 static uint32 Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency(void);
348 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG0_CLK_Frequency(void);
349 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG1_CLK_Frequency(void);
350 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG2_CLK_Frequency(void);
351 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG3_CLK_Frequency(void);
352 static uint32 Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency(void);
353 static uint32 Clock_Ip_Get_P0_REG_INTF_CLK_Frequency(void);
354 static uint32 Clock_Ip_Get_P1_CLKOUT_SRC_CLK_Frequency(void);
355 static uint32 Clock_Ip_Get_P1_DSPI60_CLK_Frequency(void);
356 static uint32 Clock_Ip_Get_ETH_TS_CLK_Frequency(void);
357 static uint32 Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency(void);
358 static uint32 Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency(void);
359 static uint32 Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency(void);
360 static uint32 Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency(void);
361 static uint32 Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency(void);
362 static uint32 Clock_Ip_Get_ETH0_TX_RGMII_LPBK_CLK_Frequency(void);
363 static uint32 Clock_Ip_Get_ETH1_REF_RMII_CLK_Frequency(void);
364 static uint32 Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency(void);
365 static uint32 Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency(void);
366 static uint32 Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency(void);
367 static uint32 Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency(void);
368 static uint32 Clock_Ip_Get_ETH1_TX_RGMII_LPBK_CLK_Frequency(void);
369 static uint32 Clock_Ip_Get_P1_LFAST0_REF_CLK_Frequency(void);
370 static uint32 Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency(void);
371 static uint32 Clock_Ip_Get_P1_LFAST_DFT_CLK_Frequency(void);
372 static uint32 Clock_Ip_Get_P1_NETC_AXI_CLK_Frequency(void);
373 static uint32 Clock_Ip_Get_P1_LIN_CLK_Frequency(void);
374 static uint32 Clock_Ip_Get_P1_REG_INTF_CLK_Frequency(void);
375 static uint32 Clock_Ip_Get_P2_DBG_ATB_CLK_Frequency(void);
376 static uint32 Clock_Ip_Get_P2_REG_INTF_CLK_Frequency(void);
377 static uint32 Clock_Ip_Get_P3_AES_CLK_Frequency(void);
378 static uint32 Clock_Ip_Get_P3_CLKOUT_SRC_CLK_Frequency(void);
379 static uint32 Clock_Ip_Get_P3_DBG_TS_CLK_Frequency(void);
380 static uint32 Clock_Ip_Get_P3_REG_INTF_CLK_Frequency(void);
381 static uint32 Clock_Ip_Get_P4_CLKOUT_SRC_CLK_Frequency(void);
382 static uint32 Clock_Ip_Get_P4_DSPI60_CLK_Frequency(void);
383 static uint32 Clock_Ip_Get_P4_EMIOS_LCU_CLK_Frequency(void);
384 static uint32 Clock_Ip_Get_P4_LIN_CLK_Frequency(void);
385 static uint32 Clock_Ip_Get_P4_PSI5_125K_CLK_Frequency(void);
386 static uint32 Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency(void);
387 static uint32 Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency(void);
388 static uint32 Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency(void);
389 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG0_CLK_Frequency(void);
390 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG1_CLK_Frequency(void);
391 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG2_CLK_Frequency(void);
392 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG3_CLK_Frequency(void);
393 static uint32 Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency(void);
394 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG0_CLK_Frequency(void);
395 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG1_CLK_Frequency(void);
396 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG2_CLK_Frequency(void);
397 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG3_CLK_Frequency(void);
398 static uint32 Clock_Ip_Get_P4_QSPI0_2X_CLK_Frequency(void);
399 static uint32 Clock_Ip_Get_P4_QSPI0_1X_CLK_Frequency(void);
400 static uint32 Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency(void);
401 static uint32 Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency(void);
402 static uint32 Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency(void);
403 static uint32 Clock_Ip_Get_P4_REG_INTF_CLK_Frequency(void);
404 static uint32 Clock_Ip_Get_P4_SDHC_IP_CLK_Frequency(void);
405 static uint32 Clock_Ip_Get_P4_SDHC_IP_DIV2_CLK_Frequency(void);
406 static uint32 Clock_Ip_Get_P5_CANXL_PE_CLK_Frequency(void);
407 static uint32 Clock_Ip_Get_P5_CANXL_CHI_CLK_Frequency(void);
408 static uint32 Clock_Ip_Get_P5_DIPORT_CLK_Frequency(void);
409 static uint32 Clock_Ip_Get_P5_AE_CLK_Frequency(void);
410 static uint32 Clock_Ip_Get_P5_CLKOUT_SRC_CLK_Frequency(void);
411 static uint32 Clock_Ip_Get_P5_LIN_CLK_Frequency(void);
412 static uint32 Clock_Ip_Get_P5_REG_INTF_CLK_Frequency(void);
413 static uint32 Clock_Ip_Get_P6_REG_INTF_CLK_Frequency(void);
414 static uint32 Clock_Ip_Get_PIT0_CLK_Frequency(void);
415 static uint32 Clock_Ip_Get_PIT1_CLK_Frequency(void);
416 static uint32 Clock_Ip_Get_PIT4_CLK_Frequency(void);
417 static uint32 Clock_Ip_Get_PIT5_CLK_Frequency(void);
418 static uint32 Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency(void);
419 static uint32 Clock_Ip_Get_PSI5_0_CLK_Frequency(void);
420 static uint32 Clock_Ip_Get_P4_PSI5_1US_CLK_Frequency(void);
421 static uint32 Clock_Ip_Get_PSI5_1_CLK_Frequency(void);
422 static uint32 Clock_Ip_Get_PSI5S_0_CLK_Frequency(void);
423 static uint32 Clock_Ip_Get_PSI5S_1_CLK_Frequency(void);
424 static uint32 Clock_Ip_Get_QSPI0_CLK_Frequency(void);
425 static uint32 Clock_Ip_Get_QSPI1_CLK_Frequency(void);
426 static uint32 Clock_Ip_Get_RTU0_REG_INTF_CLK_Frequency(void);
427 static uint32 Clock_Ip_Get_RTU1_REG_INTF_CLK_Frequency(void);
428 static uint32 Clock_Ip_Get_RXLUT_CLK_Frequency(void);
429 static uint32 Clock_Ip_Get_P4_SDHC_CLK_Frequency(void);
430 static uint32 Clock_Ip_Get_SDHC0_CLK_Frequency(void);
431 static uint32 Clock_Ip_Get_SINC_CLK_Frequency(void);
432 static uint32 Clock_Ip_Get_SIPI0_CLK_Frequency(void);
433 static uint32 Clock_Ip_Get_SIPI1_CLK_Frequency(void);
434 static uint32 Clock_Ip_Get_SIUL2_0_CLK_Frequency(void);
435 static uint32 Clock_Ip_Get_SIUL2_1_CLK_Frequency(void);
436 static uint32 Clock_Ip_Get_SIUL2_4_CLK_Frequency(void);
437 static uint32 Clock_Ip_Get_SIUL2_5_CLK_Frequency(void);
438 static uint32 Clock_Ip_Get_P0_DSPI_CLK_Frequency(void);
439 static uint32 Clock_Ip_Get_SPI0_CLK_Frequency(void);
440 static uint32 Clock_Ip_Get_SPI1_CLK_Frequency(void);
441 static uint32 Clock_Ip_Get_P1_DSPI_CLK_Frequency(void);
442 static uint32 Clock_Ip_Get_SPI2_CLK_Frequency(void);
443 static uint32 Clock_Ip_Get_SPI3_CLK_Frequency(void);
444 static uint32 Clock_Ip_Get_SPI4_CLK_Frequency(void);
445 static uint32 Clock_Ip_Get_P4_DSPI_CLK_Frequency(void);
446 static uint32 Clock_Ip_Get_SPI5_CLK_Frequency(void);
447 static uint32 Clock_Ip_Get_SPI6_CLK_Frequency(void);
448 static uint32 Clock_Ip_Get_SPI7_CLK_Frequency(void);
449 static uint32 Clock_Ip_Get_P5_DSPI_CLK_Frequency(void);
450 static uint32 Clock_Ip_Get_SPI8_CLK_Frequency(void);
451 static uint32 Clock_Ip_Get_SPI9_CLK_Frequency(void);
452 static uint32 Clock_Ip_Get_SRX0_CLK_Frequency(void);
453 static uint32 Clock_Ip_Get_SRX1_CLK_Frequency(void);
454 static uint32 Clock_Ip_Get_CORE_PLL_REFCLKOUT_Frequency(void);
455 static uint32 Clock_Ip_Get_PERIPH_PLL_REFCLKOUT_Frequency(void);
456 static uint32 Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency(void);
457 static uint32 Clock_Ip_Get_Px_PSI5_S_UTIL_CLK_Frequency(void);
458
459 /* Clock stop section code */
460 #define MCU_STOP_SEC_CODE
461 #include "Mcu_MemMap.h"
462
463 /*==================================================================================================
464 LOCAL CONSTANTS
465 ==================================================================================================*/
466
467 /* Clock start constant section data */
468 #define MCU_START_SEC_CONST_UNSPECIFIED
469 #include "Mcu_MemMap.h"
470
471 static const uint32 Clock_Ip_au32EnableDivider[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED};
472 static const uint32 Clock_Ip_u32EnableGate[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED};
473
474
475
476 typedef uint32 (*getFreqType)(void);
477
478 static const getFreqType Clock_Ip_apfFreqTableClkSrc[CLOCK_IP_SELECTOR_SOURCE_NO] = {
479 Clock_Ip_Get_FIRC_CLK_Frequency, /* clock name for 0 hardware value */
480 Clock_Ip_Get_Zero_Frequency, /* clock name for 1 hardware value */
481 Clock_Ip_Get_FXOSC_CLK_Frequency, /* clock name for 2 hardware value */
482 Clock_Ip_Get_Zero_Frequency, /* clock name for 3 hardware value */
483 Clock_Ip_Get_Zero_Frequency, /* clock name for 4 hardware value */
484 Clock_Ip_Get_Zero_Frequency, /* clock name for 5 hardware value */
485 Clock_Ip_Get_Zero_Frequency, /* clock name for 6 hardware value */
486 Clock_Ip_Get_Zero_Frequency, /* clock name for 7 hardware value */
487 Clock_Ip_Get_Zero_Frequency, /* clock name for 8 hardware value */
488 Clock_Ip_Get_Zero_Frequency, /* clock name for 9 hardware value */
489 Clock_Ip_Get_COREPLL_PHI0_Frequency, /* clock name for 10 hardware value */
490 Clock_Ip_Get_COREPLL_DFS0_Frequency, /* clock name for 11 hardware value */
491 Clock_Ip_Get_COREPLL_DFS1_Frequency, /* clock name for 12 hardware value */
492 Clock_Ip_Get_COREPLL_DFS2_Frequency, /* clock name for 13 hardware value */
493 Clock_Ip_Get_COREPLL_DFS3_Frequency, /* clock name for 14 hardware value */
494 Clock_Ip_Get_COREPLL_DFS4_Frequency, /* clock name for 15 hardware value */
495 Clock_Ip_Get_COREPLL_DFS5_Frequency, /* clock name for 16 hardware value */
496 Clock_Ip_Get_Zero_Frequency, /* clock name for 17 hardware value */
497 Clock_Ip_Get_Zero_Frequency, /* clock name for 18 hardware value */
498 Clock_Ip_Get_Zero_Frequency, /* clock name for 19 hardware value */
499 Clock_Ip_Get_PERIPHPLL_PHI0_Frequency, /* clock name for 20 hardware value */
500 Clock_Ip_Get_PERIPHPLL_PHI1_Frequency, /* clock name for 21 hardware value */
501 Clock_Ip_Get_PERIPHPLL_PHI2_Frequency, /* clock name for 22 hardware value */
502 Clock_Ip_Get_PERIPHPLL_PHI3_Frequency, /* clock name for 23 hardware value */
503 Clock_Ip_Get_PERIPHPLL_PHI4_Frequency, /* clock name for 24 hardware value */
504 Clock_Ip_Get_PERIPHPLL_PHI5_Frequency, /* clock name for 25 hardware value */
505 Clock_Ip_Get_PERIPHPLL_PHI6_Frequency, /* clock name for 26 hardware value */
506 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
507 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
508 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
509 Clock_Ip_Get_PERIPHPLL_DFS0_Frequency, /* clock name for 30 hardware value */
510 Clock_Ip_Get_PERIPHPLL_DFS1_Frequency, /* clock name for 31 hardware value */
511 Clock_Ip_Get_PERIPHPLL_DFS2_Frequency, /* clock name for 32 hardware value */
512 Clock_Ip_Get_PERIPHPLL_DFS3_Frequency, /* clock name for 33 hardware value */
513 Clock_Ip_Get_PERIPHPLL_DFS4_Frequency, /* clock name for 34 hardware value */
514 Clock_Ip_Get_PERIPHPLL_DFS5_Frequency, /* clock name for 35 hardware value */
515 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
516 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
517 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
518 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
519 Clock_Ip_Get_DDRPLL_PHI0_Frequency, /* clock name for 40 hardware value */
520 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
521 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
522 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
523 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
524 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
525 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
526 Clock_Ip_Get_eth_rgmii_ref_Frequency, /* clock name for 47 hardware value */
527 Clock_Ip_Get_eth_ext_ts_Frequency, /* clock name for 48 hardware value */
528 Clock_Ip_Get_eth0_ext_rx_Frequency, /* clock name for 49 hardware value */
529 Clock_Ip_Get_eth0_ext_tx_Frequency, /* clock name for 50 hardware value */
530 Clock_Ip_Get_eth1_ext_rx_Frequency, /* clock name for 51 hardware value */
531 Clock_Ip_Get_eth1_ext_tx_Frequency, /* clock name for 52 hardware value */
532 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
533 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
534 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
535 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
536 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
537 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
538 Clock_Ip_Get_lfast0_ext_ref_Frequency, /* clock name for 59 hardware value */
539 Clock_Ip_Get_lfast1_ext_ref_Frequency, /* clock name for 60 hardware value */
540 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
541 Clock_Ip_Get_Px_PSI5_S_UTIL_CLK_Frequency, /* clock name for 62 hardware value */
542 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
543 };
544
545 static const getFreqType Clock_Ip_apfFreqTableCLKOUT0SEL[CLOCK_IP_SELECTOR_SOURCE_NO] = {
546 Clock_Ip_Get_SIRC_CLK_Frequency, /* clock name for 0 hardware value SIRC_CLK */
547 Clock_Ip_Get_FIRC_CLK_Frequency, /* clock name for 1 hardware value FIRC_CLK */
548 Clock_Ip_Get_FXOSC_CLK_Frequency, /* clock name for 2 hardware value FXOSC_CLK */
549 Clock_Ip_Get_COREPLL_PHI0_Frequency, /* clock name for 3 hardware value COREPLL_PHI0_CLK */
550 Clock_Ip_Get_COREPLL_DFS0_Frequency, /* clock name for 4 hardware value COREDFS0_CLK */
551 Clock_Ip_Get_COREPLL_DFS1_Frequency, /* clock name for 5 hardware value COREDFS1_CLK */
552 Clock_Ip_Get_COREPLL_DFS2_Frequency, /* clock name for 6 hardware value COREDFS2_CLK */
553 Clock_Ip_Get_COREPLL_DFS3_Frequency, /* clock name for 7 hardware value COREDFS3_CLK */
554 Clock_Ip_Get_COREPLL_DFS4_Frequency, /* clock name for 8 hardware value COREDFS4_CLK */
555 Clock_Ip_Get_COREPLL_DFS5_Frequency, /* clock name for 9 hardware value COREDFS5_CLK */
556 Clock_Ip_Get_PERIPHPLL_PHI0_Frequency, /* clock name for 10 hardware value PERIPHPLL_PHI0_CLK */
557 Clock_Ip_Get_PERIPHPLL_PHI1_Frequency, /* clock name for 11 hardware value PERIPHPLL_PHI1_CLK */
558 Clock_Ip_Get_PERIPHPLL_PHI2_Frequency, /* clock name for 12 hardware value PERIPHPLL_PHI2_CLK */
559 Clock_Ip_Get_PERIPHPLL_PHI3_Frequency, /* clock name for 13 hardware value PERIPHPLL_PHI3_CLK */
560 Clock_Ip_Get_PERIPHPLL_PHI4_Frequency, /* clock name for 14 hardware value PERIPHPLL_PHI4_CLK */
561 Clock_Ip_Get_PERIPHPLL_PHI5_Frequency, /* clock name for 15 hardware value PERIPHPLL_PHI5_CLK */
562 Clock_Ip_Get_PERIPHPLL_PHI6_Frequency, /* clock name for 16 hardware value PERIPHPLL_PHI6_CLK */
563 Clock_Ip_Get_PERIPHPLL_DFS0_Frequency, /* clock name for 17 hardware value PERIPHDFS0_CLK */
564 Clock_Ip_Get_PERIPHPLL_DFS1_Frequency, /* clock name for 18 hardware value PERIPHDFS1_CLK */
565 Clock_Ip_Get_PERIPHPLL_DFS2_Frequency, /* clock name for 19 hardware value PERIPHDFS2_CLK */
566 Clock_Ip_Get_PERIPHPLL_DFS3_Frequency, /* clock name for 20 hardware value PERIPHDFS3_CLK */
567 Clock_Ip_Get_PERIPHPLL_DFS4_Frequency, /* clock name for 21 hardware value PERIPHDFS4_CLK */
568 Clock_Ip_Get_PERIPHPLL_DFS5_Frequency, /* clock name for 22 hardware value PERIPHDFS5_CLK */
569 Clock_Ip_Get_DDRPLL_PHI0_Frequency, /* clock name for 23 hardware value DDRPLL_PHI0_CLK */
570 Clock_Ip_Get_P0_SYS_CLK_Frequency, /* clock name for 24 hardware value P0_SYS_CLK */
571 Clock_Ip_Get_P0_REG_INTF_CLK_Frequency, /* clock name for 25 hardware value P0_REG_INTF_CLK */
572 Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency, /* clock name for 26 hardware value P0_REG_INTF_2X_CLK */
573 Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency, /* clock name for 27 hardware value P0_PSI5_1US_CLK */
574 Clock_Ip_Get_P0_PSI5_125K_CLK_Frequency, /* clock name for 28 hardware value P0_PSI5_125K_CLK */
575 Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency, /* clock name for 29 hardware value P0_PSI5_189K_CLK */
576 Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency, /* clock name for 30 hardware value P0_PSI5_S_UTIL_CLK */
577 Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency, /* clock name for 31 hardware value P0_PSI5_S_UART_CLK */
578 Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency, /* clock name for 32 hardware value P0_PSI5_S_BAUD_CLK */
579 Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency, /* clock name for 33 hardware value P0_PSI5_S_CORE_CLK */
580 Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency, /* clock name for 34 hardware value P0_LIN_BAUD_CLK */
581 Clock_Ip_Get_P0_LIN_CLK_Frequency, /* clock name for 35 hardware value P0_LIN_CLK */
582 Clock_Ip_Get_P0_DSPI_CLK_Frequency, /* clock name for 36 hardware value P0_DSPI_CLK */
583 Clock_Ip_Get_P0_FR_PE_CLK_Frequency, /* clock name for 37 hardware value P0_FR_PE_CLK */
584 Clock_Ip_Get_P0_NANO_CLK_Frequency, /* clock name for 38 hardware value P0_NANO_CLK */
585 Clock_Ip_Get_P0_GTM_CLK_Frequency, /* clock name for 39 hardware value P0_GTM_CLK */
586 Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency, /* clock name for 40 hardware value P0_GTM_NOC_CLK */
587 Clock_Ip_Get_P0_GTM_TS_CLK_Frequency, /* clock name for 41 hardware value P0_GTM_TS_CLK */
588 Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency, /* clock name for 42 hardware value P0_DSPI_MSC_CLK */
589 Clock_Ip_Get_P0_CTU_PER_CLK_Frequency, /* clock name for 43 hardware value P0_CTU_PER_CLK */
590 Clock_Ip_Get_P0_EMIOS_LCU_CLK_Frequency, /* clock name for 44 hardware value P0_EMIOS_LCU_CLK */
591 Clock_Ip_Get_CORE_PLL_REFCLKOUT_Frequency, /* clock name for 45 hardware value CORE_PLL_REFCLKOUT */
592 Clock_Ip_Get_COREPLL_CLK_Frequency, /* clock name for 46 hardware value CORE_PLL_FBCLKOUT */
593 Clock_Ip_Get_PERIPH_PLL_REFCLKOUT_Frequency, /* clock name for 47 hardware value PERIPH_PLL_REFCLKOUT */
594 Clock_Ip_Get_PERIPHPLL_CLK_Frequency, /* clock name for 48 hardware value PERIPH_PLL_FBCLKOUT */
595 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
596 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
597 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
598 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
599 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
600 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
601 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
602 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
603 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
604 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
605 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
606 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
607 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
608 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
609 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
610 };
611
612 static const getFreqType Clock_Ip_apfFreqTableCLKOUT1SEL[CLOCK_IP_SELECTOR_SOURCE_NO] = {
613 Clock_Ip_Get_LFAST0_PLL_CLK_Frequency, /* clock name for 0 hardware value LFAST0_PLL_PH0_CLK */
614 Clock_Ip_Get_LFAST1_PLL_CLK_Frequency, /* clock name for 1 hardware value LFAST1_PLL_PH0_CLK */
615 Clock_Ip_Get_P1_SYS_CLK_Frequency, /* clock name for 2 hardware value P1_SYS_CLK */
616 Clock_Ip_Get_P1_SYS_DIV2_CLK_Frequency, /* clock name for 3 hardware value P1_SYS_DIV2_CLK */
617 Clock_Ip_Get_P1_SYS_DIV4_CLK_Frequency, /* clock name for 4 hardware value P1_SYS_DIV4_CLK */
618 Clock_Ip_Get_P1_REG_INTF_CLK_Frequency, /* clock name for 5 hardware value P1_REG_INTF_CLK */
619 Clock_Ip_Get_P1_DSPI_CLK_Frequency, /* clock name for 6 hardware value P1_DSPI_CLK */
620 Clock_Ip_Get_P1_DSPI60_CLK_Frequency, /* clock name for 7 hardware value P1_DSPI60_CLK */
621 Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency, /* clock name for 8 hardware value P1_LIN_BAUD_CLK */
622 Clock_Ip_Get_P1_LIN_CLK_Frequency, /* clock name for 9 hardware value P1_LIN_CLK */
623 Clock_Ip_Get_ETH_TS_CLK_Frequency, /* clock name for 10 hardware value ETH_TS_CLK */
624 Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency, /* clock name for 11 hardware value ETH_TS_DIV4_CLK */
625 Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency, /* clock name for 12 hardware value ETH0_TX_MII_CLK */
626 Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency, /* clock name for 13 hardware value ETH0_TX_RGMII_CLK */
627 Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency, /* clock name for 14 hardware value ETH0_RX_MII_CLK */
628 Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency, /* clock name for 15 hardware value ETH0_RX_RGMII_CLK */
629 Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency, /* clock name for 16 hardware value ETH0_REF_RMII_CLK */
630 Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency, /* clock name for 17 hardware value ETH1_TX_MII_CLK */
631 Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency, /* clock name for 18 hardware value ETH1_TX_RGMII_CLK */
632 Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency, /* clock name for 19 hardware value ETH1_RX_MII_CLK */
633 Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency, /* clock name for 20 hardware value ETH1_RX_RGMII_CLK */
634 Clock_Ip_Get_ETH1_REF_RMII_CLK_Frequency, /* clock name for 21 hardware value ETH1_REF_RMII_CLK */
635 Clock_Ip_Get_Zero_Frequency, /* clock name for 22 hardware value ETH_AXI_CLK */
636 Clock_Ip_Get_Zero_Frequency, /* clock name for 23 hardware value */
637 Clock_Ip_Get_Zero_Frequency, /* clock name for 24 hardware value */
638 Clock_Ip_Get_Zero_Frequency, /* clock name for 25 hardware value */
639 Clock_Ip_Get_Zero_Frequency, /* clock name for 26 hardware value */
640 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
641 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
642 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
643 Clock_Ip_Get_Zero_Frequency, /* clock name for 30 hardware value */
644 Clock_Ip_Get_Zero_Frequency, /* clock name for 31 hardware value */
645 Clock_Ip_Get_Zero_Frequency, /* clock name for 32 hardware value */
646 Clock_Ip_Get_Zero_Frequency, /* clock name for 33 hardware value */
647 Clock_Ip_Get_Zero_Frequency, /* clock name for 34 hardware value */
648 Clock_Ip_Get_Zero_Frequency, /* clock name for 35 hardware value */
649 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
650 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
651 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
652 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
653 Clock_Ip_Get_Zero_Frequency, /* clock name for 40 hardware value */
654 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
655 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
656 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
657 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
658 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
659 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
660 Clock_Ip_Get_Zero_Frequency, /* clock name for 47 hardware value */
661 Clock_Ip_Get_Zero_Frequency, /* clock name for 48 hardware value */
662 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
663 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
664 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
665 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
666 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
667 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
668 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
669 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
670 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
671 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
672 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
673 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
674 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
675 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
676 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
677 };
678
679 static const getFreqType Clock_Ip_apfFreqTableCLKOUT2SEL[CLOCK_IP_SELECTOR_SOURCE_NO] = {
680 Clock_Ip_Get_P4_SYS_CLK_Frequency, /* clock name for 0 hardware value P4_SYS_CLK */
681 Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency, /* clock name for 1 hardware value P4_SYS_DIV2_CLK */
682 Clock_Ip_Get_HSE_SYS_DIV2_CLK_Frequency, /* clock name for 2 hardware value HSE_SYS_DIV2_CLK */
683 Clock_Ip_Get_P4_REG_INTF_CLK_Frequency, /* clock name for 3 hardware value P4_REG_INTF_CLK */
684 Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency, /* clock name for 4 hardware value P4_REG_INTF_2X_CLK */
685 Clock_Ip_Get_P4_PSI5_1US_CLK_Frequency, /* clock name for 5 hardware value P4_PSI5_1US_CLK */
686 Clock_Ip_Get_P4_PSI5_125K_CLK_Frequency, /* clock name for 6 hardware value P4_PSI5_125K_CLK */
687 Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency, /* clock name for 7 hardware value P4_PSI5_189K_CLK */
688 Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency, /* clock name for 8 hardware value P4_PSI5_S_UTIL_CLK */
689 Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency, /* clock name for 9 hardware value P4_PSI5_S_UART_CLK */
690 Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency, /* clock name for 10 hardware value P4_PSI5_S_BAUD_CLK */
691 Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency, /* clock name for 11 hardware value P4_PSI5_S_CORE_CLK */
692 Clock_Ip_Get_P4_DSPI_CLK_Frequency, /* clock name for 12 hardware value P4_DSPI_CLK */
693 Clock_Ip_Get_P4_DSPI60_CLK_Frequency, /* clock name for 13 hardware value P4_DSPI60_CLK */
694 Clock_Ip_Get_P4_QSPI0_2X_CLK_Frequency, /* clock name for 14 hardware value P4_QSPI0_2X_CLK */
695 Clock_Ip_Get_P4_QSPI0_1X_CLK_Frequency, /* clock name for 15 hardware value P4_QSPI0_1X_CLK */
696 Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency, /* clock name for 16 hardware value P4_LIN_BAUD_CLK */
697 Clock_Ip_Get_P4_LIN_CLK_Frequency, /* clock name for 17 hardware value P4_LIN_CLK */
698 Clock_Ip_Get_P4_SDHC_CLK_Frequency, /* clock name for 18 hardware value P4_SDHC_CLK */
699 Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency, /* clock name for 19 hardware value P4_QSPI1_2X_CLK */
700 Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency, /* clock name for 20 hardware value P4_QSPI1_1X_CLK */
701 Clock_Ip_Get_P4_SDHC_IP_CLK_Frequency, /* clock name for 21 hardware value P4_SDHC_IP_CLK */
702 Clock_Ip_Get_P4_SDHC_IP_DIV2_CLK_Frequency, /* clock name for 22 hardware value P4_SDHC_IP_DIV2_CLK */
703 Clock_Ip_Get_P4_EMIOS_LCU_CLK_Frequency, /* clock name for 23 hardware value P4_EMIOS_LCU_CLK */
704 Clock_Ip_Get_Zero_Frequency, /* clock name for 24 hardware value */
705 Clock_Ip_Get_Zero_Frequency, /* clock name for 25 hardware value */
706 Clock_Ip_Get_Zero_Frequency, /* clock name for 26 hardware value */
707 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
708 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
709 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
710 Clock_Ip_Get_Zero_Frequency, /* clock name for 30 hardware value */
711 Clock_Ip_Get_Zero_Frequency, /* clock name for 31 hardware value */
712 Clock_Ip_Get_Zero_Frequency, /* clock name for 32 hardware value */
713 Clock_Ip_Get_Zero_Frequency, /* clock name for 33 hardware value */
714 Clock_Ip_Get_Zero_Frequency, /* clock name for 34 hardware value */
715 Clock_Ip_Get_Zero_Frequency, /* clock name for 35 hardware value */
716 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
717 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
718 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
719 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
720 Clock_Ip_Get_Zero_Frequency, /* clock name for 40 hardware value */
721 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
722 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
723 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
724 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
725 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
726 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
727 Clock_Ip_Get_Zero_Frequency, /* clock name for 47 hardware value */
728 Clock_Ip_Get_Zero_Frequency, /* clock name for 48 hardware value */
729 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
730 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
731 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
732 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
733 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
734 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
735 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
736 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
737 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
738 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
739 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
740 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
741 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
742 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
743 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
744 };
745
746 static const getFreqType Clock_Ip_apfFreqTableCLKOUT3SEL[CLOCK_IP_SELECTOR_SOURCE_NO] = {
747 Clock_Ip_Get_P5_SYS_CLK_Frequency, /* clock name for 0 hardware value P5_SYS_CLK */
748 Clock_Ip_Get_P5_SYS_DIV2_CLK_Frequency, /* clock name for 1 hardware value P5_SYS_DIV2_CLK */
749 Clock_Ip_Get_P5_SYS_DIV4_CLK_Frequency, /* clock name for 2 hardware value P5_SYS_DIV4_CLK */
750 Clock_Ip_Get_P5_REG_INTF_CLK_Frequency, /* clock name for 3 hardware value P5_REG_INTF_CLK */
751 Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency, /* clock name for 4 hardware value P5_LIN_BAUD_CLK */
752 Clock_Ip_Get_P5_LIN_CLK_Frequency, /* clock name for 5 hardware value P5_LIN_CLK */
753 Clock_Ip_Get_P5_DSPI_CLK_Frequency, /* clock name for 6 hardware value P5_DSPI_CLK */
754 Clock_Ip_Get_Zero_Frequency, /* clock name for 7 hardware value P5_DIPORT_CLK */
755 Clock_Ip_Get_Zero_Frequency, /* clock name for 8 hardware value P5_AE_CLK */
756 Clock_Ip_Get_Zero_Frequency, /* clock name for 9 hardware value P5_CANXL_PE_CLK */
757 Clock_Ip_Get_Zero_Frequency, /* clock name for 10 hardware value P5_CANXL_CHI_CLK */
758 Clock_Ip_Get_Zero_Frequency, /* clock name for 11 hardware value */
759 Clock_Ip_Get_Zero_Frequency, /* clock name for 12 hardware value */
760 Clock_Ip_Get_Zero_Frequency, /* clock name for 13 hardware value */
761 Clock_Ip_Get_Zero_Frequency, /* clock name for 14 hardware value */
762 Clock_Ip_Get_Zero_Frequency, /* clock name for 15 hardware value */
763 Clock_Ip_Get_Zero_Frequency, /* clock name for 16 hardware value */
764 Clock_Ip_Get_Zero_Frequency, /* clock name for 17 hardware value */
765 Clock_Ip_Get_Zero_Frequency, /* clock name for 18 hardware value */
766 Clock_Ip_Get_Zero_Frequency, /* clock name for 19 hardware value */
767 Clock_Ip_Get_Zero_Frequency, /* clock name for 20 hardware value */
768 Clock_Ip_Get_Zero_Frequency, /* clock name for 21 hardware value */
769 Clock_Ip_Get_Zero_Frequency, /* clock name for 22 hardware value */
770 Clock_Ip_Get_Zero_Frequency, /* clock name for 23 hardware value */
771 Clock_Ip_Get_Zero_Frequency, /* clock name for 24 hardware value */
772 Clock_Ip_Get_Zero_Frequency, /* clock name for 25 hardware value */
773 Clock_Ip_Get_Zero_Frequency, /* clock name for 26 hardware value */
774 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
775 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
776 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
777 Clock_Ip_Get_Zero_Frequency, /* clock name for 30 hardware value */
778 Clock_Ip_Get_Zero_Frequency, /* clock name for 31 hardware value */
779 Clock_Ip_Get_Zero_Frequency, /* clock name for 32 hardware value */
780 Clock_Ip_Get_Zero_Frequency, /* clock name for 33 hardware value */
781 Clock_Ip_Get_Zero_Frequency, /* clock name for 34 hardware value */
782 Clock_Ip_Get_Zero_Frequency, /* clock name for 35 hardware value */
783 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
784 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
785 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
786 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
787 Clock_Ip_Get_Zero_Frequency, /* clock name for 40 hardware value */
788 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
789 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
790 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
791 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
792 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
793 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
794 Clock_Ip_Get_Zero_Frequency, /* clock name for 47 hardware value */
795 Clock_Ip_Get_Zero_Frequency, /* clock name for 48 hardware value */
796 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
797 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
798 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
799 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
800 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
801 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
802 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
803 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
804 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
805 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
806 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
807 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
808 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
809 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
810 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
811 };
812
813 static const getFreqType Clock_Ip_apfFreqTableCLKOUT4SEL[CLOCK_IP_SELECTOR_SOURCE_NO] = {
814 Clock_Ip_Get_P3_SYS_CLK_Frequency, /* clock name for 0 hardware value P3_SYS_CLK */
815 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency, /* clock name for 1 hardware value CE_SYS_DIV2_CLK */
816 Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency, /* clock name for 2 hardware value CE_SYS_DIV4_CLK */
817 Clock_Ip_Get_P3_REG_INTF_CLK_Frequency, /* clock name for 3 hardware value P3_REG_INTF_CLK */
818 Clock_Ip_Get_P3_DBG_TS_CLK_Frequency, /* clock name for 4 hardware value P3_DBG_TS_CLK */
819 Clock_Ip_Get_P3_AES_CLK_Frequency, /* clock name for 5 hardware value P3_AES_CLK */
820 Clock_Ip_Get_P3_CAN_PE_CLK_Frequency, /* clock name for 6 hardware value P3_CAN_PE_CLK */
821 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency, /* clock name for 7 hardware value RTU0_CORE_DIV2_CLK */
822 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency, /* clock name for 8 hardware value RTU1_CORE_DIV2_CLK */
823 Clock_Ip_Get_DDR_CLK_Frequency, /* clock name for 9 hardware value DDR_CLK */
824 Clock_Ip_Get_P3_SYS_DIV2_NOC_CLK_Frequency, /* clock name for 10 hardware value P3_SYS_DIV2_NOC_CLK */
825 Clock_Ip_Get_Zero_Frequency, /* clock name for 11 hardware value */
826 Clock_Ip_Get_Zero_Frequency, /* clock name for 12 hardware value */
827 Clock_Ip_Get_Zero_Frequency, /* clock name for 13 hardware value */
828 Clock_Ip_Get_Zero_Frequency, /* clock name for 14 hardware value */
829 Clock_Ip_Get_Zero_Frequency, /* clock name for 15 hardware value */
830 Clock_Ip_Get_Zero_Frequency, /* clock name for 16 hardware value */
831 Clock_Ip_Get_Zero_Frequency, /* clock name for 17 hardware value */
832 Clock_Ip_Get_Zero_Frequency, /* clock name for 18 hardware value */
833 Clock_Ip_Get_Zero_Frequency, /* clock name for 19 hardware value */
834 Clock_Ip_Get_Zero_Frequency, /* clock name for 20 hardware value */
835 Clock_Ip_Get_Zero_Frequency, /* clock name for 21 hardware value */
836 Clock_Ip_Get_Zero_Frequency, /* clock name for 22 hardware value */
837 Clock_Ip_Get_Zero_Frequency, /* clock name for 23 hardware value */
838 Clock_Ip_Get_Zero_Frequency, /* clock name for 24 hardware value */
839 Clock_Ip_Get_Zero_Frequency, /* clock name for 25 hardware value */
840 Clock_Ip_Get_Zero_Frequency, /* clock name for 26 hardware value */
841 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
842 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
843 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
844 Clock_Ip_Get_Zero_Frequency, /* clock name for 30 hardware value */
845 Clock_Ip_Get_Zero_Frequency, /* clock name for 31 hardware value */
846 Clock_Ip_Get_Zero_Frequency, /* clock name for 32 hardware value */
847 Clock_Ip_Get_Zero_Frequency, /* clock name for 33 hardware value */
848 Clock_Ip_Get_Zero_Frequency, /* clock name for 34 hardware value */
849 Clock_Ip_Get_Zero_Frequency, /* clock name for 35 hardware value */
850 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
851 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
852 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
853 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
854 Clock_Ip_Get_Zero_Frequency, /* clock name for 40 hardware value */
855 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
856 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
857 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
858 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
859 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
860 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
861 Clock_Ip_Get_Zero_Frequency, /* clock name for 47 hardware value */
862 Clock_Ip_Get_Zero_Frequency, /* clock name for 48 hardware value */
863 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
864 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
865 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
866 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
867 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
868 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
869 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
870 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
871 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
872 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
873 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
874 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
875 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
876 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
877 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
878 };
879
880 static const getFreqType Clock_Ip_apfFreqTableCLKOUT_MULTIPLEX[CLOCK_IP_CLKOUT_NO] = {
881 Clock_Ip_Get_P0_CLKOUT_SRC_CLK_Frequency, /* clock name for 0 hardware value CLKOUT0_CLK */
882 Clock_Ip_Get_P1_CLKOUT_SRC_CLK_Frequency, /* clock name for 1 hardware value CLKOUT1_CLK */
883 Clock_Ip_Get_P4_CLKOUT_SRC_CLK_Frequency, /* clock name for 2 hardware value CLKOUT2_CLK */
884 Clock_Ip_Get_P5_CLKOUT_SRC_CLK_Frequency, /* clock name for 3 hardware value CLKOUT3_CLK */
885 Clock_Ip_Get_P3_CLKOUT_SRC_CLK_Frequency, /* clock name for 4 hardware value CLKOUT4_CLK */
886 };
887
888 static const getFreqType Clock_Ip_apfFreqTablePSI5_S_UTIL_MULTIPLEX[CLOCK_IP_CLKPSI5_S_UTIL_NO] = {
889 Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency, /* clock name for 0 hardware value P0_PSI5_S_UTIL_CLK */
890 Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency, /* clock name for 1 hardware value P4_PSI5_S_UTIL_CLK */
891 };
892
893 static const getFreqType Clock_Ip_apfFreqTable[CLOCK_IP_NAMES_NO] =
894 {
895 Clock_Ip_Get_Zero_Frequency, /* CLOCK_IS_OFF */
896 Clock_Ip_Get_FIRC_CLK_Frequency, /* FIRC_CLK clock */
897 Clock_Ip_Get_FXOSC_CLK_Frequency, /* FXOSC_CLK clock */
898 Clock_Ip_Get_SIRC_CLK_Frequency, /* SIRC_CLK clock */
899 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK)
900 Clock_Ip_Get_FIRC_AE_CLK_Frequency, /* FIRC_AE_CLK clock */
901 #endif
902 Clock_Ip_Get_COREPLL_CLK_Frequency, /* COREPLL_CLK clock */
903 Clock_Ip_Get_PERIPHPLL_CLK_Frequency, /* PERIPHPLL_CLK clock */
904 Clock_Ip_Get_DDRPLL_CLK_Frequency, /* DDRPLL_CLK clock */
905 Clock_Ip_Get_LFAST0_PLL_CLK_Frequency, /* LFAST0_PLL_CLK clock */
906 Clock_Ip_Get_LFAST1_PLL_CLK_Frequency, /* LFAST1_PLL_CLK clock */
907 Clock_Ip_Get_COREPLL_PHI0_Frequency, /* COREPLL_PHI0 clock */
908 Clock_Ip_Get_COREPLL_DFS0_Frequency, /* COREPLL_DFS0 clock */
909 Clock_Ip_Get_COREPLL_DFS1_Frequency, /* COREPLL_DFS1 clock */
910 Clock_Ip_Get_COREPLL_DFS2_Frequency, /* COREPLL_DFS2 clock */
911 Clock_Ip_Get_COREPLL_DFS3_Frequency, /* COREPLL_DFS3 clock */
912 Clock_Ip_Get_COREPLL_DFS4_Frequency, /* COREPLL_DFS4 clock */
913 Clock_Ip_Get_COREPLL_DFS5_Frequency, /* COREPLL_DFS5 clock */
914 Clock_Ip_Get_PERIPHPLL_PHI0_Frequency, /* PERIPHPLL_PHI0 clock */
915 Clock_Ip_Get_PERIPHPLL_PHI1_Frequency, /* PERIPHPLL_PHI1 clock */
916 Clock_Ip_Get_PERIPHPLL_PHI2_Frequency, /* PERIPHPLL_PHI2 clock */
917 Clock_Ip_Get_PERIPHPLL_PHI3_Frequency, /* PERIPHPLL_PHI3 clock */
918 Clock_Ip_Get_PERIPHPLL_PHI4_Frequency, /* PERIPHPLL_PHI4 clock */
919 Clock_Ip_Get_PERIPHPLL_PHI5_Frequency, /* PERIPHPLL_PHI5 clock */
920 Clock_Ip_Get_PERIPHPLL_PHI6_Frequency, /* PERIPHPLL_PHI6 clock */
921 Clock_Ip_Get_PERIPHPLL_DFS0_Frequency, /* PERIPHPLL_DFS0 clock */
922 Clock_Ip_Get_PERIPHPLL_DFS1_Frequency, /* PERIPHPLL_DFS1 clock */
923 Clock_Ip_Get_PERIPHPLL_DFS2_Frequency, /* PERIPHPLL_DFS2 clock */
924 Clock_Ip_Get_PERIPHPLL_DFS3_Frequency, /* PERIPHPLL_DFS3 clock */
925 Clock_Ip_Get_PERIPHPLL_DFS4_Frequency, /* PERIPHPLL_DFS4 clock */
926 Clock_Ip_Get_PERIPHPLL_DFS5_Frequency, /* PERIPHPLL_DFS5 clock */
927 Clock_Ip_Get_DDRPLL_PHI0_Frequency, /* DDRPLL_PHI0 clock */
928 Clock_Ip_Get_LFAST0_PLL_CLK_Frequency, /* LFAST0_PLL_PH0_CLK clock */
929 Clock_Ip_Get_LFAST1_PLL_CLK_Frequency, /* LFAST1_PLL_PH0_CLK clock */
930 Clock_Ip_Get_eth_rgmii_ref_Frequency, /* eth_rgmii_ref clock */
931 Clock_Ip_Get_eth_ext_ts_Frequency, /* eth_ext_ts clock */
932 Clock_Ip_Get_eth0_ext_rx_Frequency, /* eth0_ext_rx clock */
933 Clock_Ip_Get_eth0_ext_tx_Frequency, /* eth0_ext_tx clock */
934 Clock_Ip_Get_eth1_ext_rx_Frequency, /* eth1_ext_rx clock */
935 Clock_Ip_Get_eth1_ext_tx_Frequency, /* eth1_ext_tx clock */
936 Clock_Ip_Get_lfast0_ext_ref_Frequency, /* lfast0_ext_ref clock */
937 Clock_Ip_Get_lfast1_ext_ref_Frequency, /* lfast1_ext_ref clock */
938 Clock_Ip_Get_DDR_CLK_Frequency, /* DDR_CLK clock */
939 Clock_Ip_Get_P0_SYS_CLK_Frequency, /* P0_SYS_CLK clock */
940 Clock_Ip_Get_P1_SYS_CLK_Frequency, /* P1_SYS_CLK clock */
941 Clock_Ip_Get_P1_SYS_DIV2_CLK_Frequency, /* P1_SYS_DIV2_CLK clock */
942 Clock_Ip_Get_P1_SYS_DIV4_CLK_Frequency, /* P1_SYS_DIV4_CLK clock */
943 Clock_Ip_Get_P2_SYS_CLK_Frequency, /* P2_SYS_CLK clock */
944 Clock_Ip_Get_P2_SYS_CLK_Frequency, /* CORE_M33_CLK clock */
945 Clock_Ip_Get_P2_SYS_DIV2_CLK_Frequency, /* P2_SYS_DIV2_CLK clock */
946 Clock_Ip_Get_P2_SYS_DIV4_CLK_Frequency, /* P2_SYS_DIV4_CLK clock */
947 Clock_Ip_Get_P3_SYS_CLK_Frequency, /* P3_SYS_CLK clock */
948 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency, /* CE_SYS_DIV2_CLK clock */
949 Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency, /* CE_SYS_DIV4_CLK clock */
950 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency, /* P3_SYS_DIV2_NOC_CLK clock */
951 Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency, /* P3_SYS_DIV4_CLK clock */
952 Clock_Ip_Get_P4_SYS_CLK_Frequency, /* P4_SYS_CLK clock */
953 Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency, /* P4_SYS_DIV2_CLK clock */
954 Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency, /* HSE_SYS_DIV2_CLK clock */
955 Clock_Ip_Get_P5_SYS_CLK_Frequency, /* P5_SYS_CLK clock */
956 Clock_Ip_Get_P5_SYS_DIV2_CLK_Frequency, /* P5_SYS_DIV2_CLK clock */
957 Clock_Ip_Get_P5_SYS_DIV4_CLK_Frequency, /* P5_SYS_DIV4_CLK clock */
958 Clock_Ip_Get_P2_MATH_CLK_Frequency, /* P2_MATH_CLK clock */
959 Clock_Ip_Get_P2_MATH_DIV3_CLK_Frequency, /* P2_MATH_DIV3_CLK clock */
960 Clock_Ip_Get_GLB_LBIST_CLK_Frequency, /* GLB_LBIST_CLK clock */
961 Clock_Ip_Get_RTU0_CORE_CLK_Frequency, /* RTU0_CORE_CLK clock */
962 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency, /* RTU0_CORE_DIV2_CLK clock */
963 Clock_Ip_Get_RTU1_CORE_CLK_Frequency, /* RTU1_CORE_CLK clock */
964 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency, /* RTU1_CORE_DIV2_CLK clock */
965 Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency, /* P0_PSI5_S_UTIL_CLK clock */
966 Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency, /* P4_PSI5_S_UTIL_CLK clock */
967 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK)
968 Clock_Ip_Get_Zero_Frequency, /* SYSTEM_DRUN_CLK clock */
969 #endif
970 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK)
971 Clock_Ip_Get_Zero_Frequency, /* SYSTEM_RUN0_CLK clock */
972 #endif
973 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK)
974 Clock_Ip_Get_Zero_Frequency, /* SYSTEM_SAFE_CLK clock */
975 #endif
976 #if defined(CLOCK_IP_HAS_SYSTEM_CLK)
977 Clock_Ip_Get_SYSTEM_CLK_Frequency, /* SYSTEM_CLK clock */
978 #endif
979 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK)
980 Clock_Ip_Get_SYSTEM_DIV2_CLK_Frequency, /* SYSTEM_DIV2_CLK clock */
981 #endif
982 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK)
983 Clock_Ip_Get_SYSTEM_DIV4_CLK_Frequency, /* SYSTEM_DIV4_CLK clock */
984 #endif
985 NULL_PTR, /* THE_LAST_PRODUCER_CLK*/
986 Clock_Ip_Get_ADC0_CLK_Frequency, /* ADC0_CLK clock */
987 Clock_Ip_Get_ADC1_CLK_Frequency, /* ADC1_CLK clock */
988 Clock_Ip_Get_CE_EDMA_CLK_Frequency, /* CE_EDMA_CLK clock */
989 Clock_Ip_Get_CE_PIT0_CLK_Frequency, /* CE_PIT0_CLK clock */
990 Clock_Ip_Get_CE_PIT1_CLK_Frequency, /* CE_PIT1_CLK clock */
991 Clock_Ip_Get_CE_PIT2_CLK_Frequency, /* CE_PIT2_CLK clock */
992 Clock_Ip_Get_CE_PIT3_CLK_Frequency, /* CE_PIT3_CLK clock */
993 Clock_Ip_Get_CE_PIT4_CLK_Frequency, /* CE_PIT4_CLK clock */
994 Clock_Ip_Get_CE_PIT5_CLK_Frequency, /* CE_PIT5_CLK clock */
995 Clock_Ip_Get_CLKOUT0_CLK_Frequency, /* CLKOUT0_CLK clock */
996 Clock_Ip_Get_CLKOUT1_CLK_Frequency, /* CLKOUT1_CLK clock */
997 Clock_Ip_Get_CLKOUT2_CLK_Frequency, /* CLKOUT2_CLK clock */
998 Clock_Ip_Get_CLKOUT3_CLK_Frequency, /* CLKOUT3_CLK clock */
999 Clock_Ip_Get_CLKOUT4_CLK_Frequency, /* CLKOUT4_CLK clock */
1000 Clock_Ip_Get_CTU_CLK_Frequency, /* CTU_CLK clock */
1001 Clock_Ip_Get_DMACRC0_CLK_Frequency, /* DMACRC0_CLK clock */
1002 Clock_Ip_Get_DMACRC1_CLK_Frequency, /* DMACRC1_CLK clock */
1003 Clock_Ip_Get_DMACRC4_CLK_Frequency, /* DMACRC4_CLK clock */
1004 Clock_Ip_Get_DMACRC5_CLK_Frequency, /* DMACRC5_CLK clock */
1005 Clock_Ip_Get_DMAMUX0_CLK_Frequency, /* DMAMUX0_CLK clock */
1006 Clock_Ip_Get_DMAMUX1_CLK_Frequency, /* DMAMUX1_CLK clock */
1007 Clock_Ip_Get_DMAMUX4_CLK_Frequency, /* DMAMUX4_CLK clock */
1008 Clock_Ip_Get_DMAMUX5_CLK_Frequency, /* DMAMUX5_CLK clock */
1009 Clock_Ip_Get_EDMA0_CLK_Frequency, /* EDMA0_CLK clock */
1010 Clock_Ip_Get_EDMA1_CLK_Frequency, /* EDMA1_CLK clock */
1011 Clock_Ip_Get_EDMA3_CLK_Frequency, /* EDMA3_CLK clock */
1012 Clock_Ip_Get_EDMA4_CLK_Frequency, /* EDMA4_CLK clock */
1013 Clock_Ip_Get_EDMA5_CLK_Frequency, /* EDMA5_CLK clock */
1014 Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency, /* ETH0_TX_MII_CLK clock */
1015 Clock_Ip_Get_ENET0_CLK_Frequency, /* ENET0_CLK clock */
1016 Clock_Ip_Get_P3_CAN_PE_CLK_Frequency, /* P3_CAN_PE_CLK clock */
1017 Clock_Ip_Get_FLEXCAN0_CLK_Frequency, /* FLEXCAN0_CLK clock */
1018 Clock_Ip_Get_FLEXCAN1_CLK_Frequency, /* FLEXCAN1_CLK clock */
1019 Clock_Ip_Get_FLEXCAN2_CLK_Frequency, /* FLEXCAN2_CLK clock */
1020 Clock_Ip_Get_FLEXCAN3_CLK_Frequency, /* FLEXCAN3_CLK clock */
1021 Clock_Ip_Get_FLEXCAN4_CLK_Frequency, /* FLEXCAN4_CLK clock */
1022 Clock_Ip_Get_FLEXCAN5_CLK_Frequency, /* FLEXCAN5_CLK clock */
1023 Clock_Ip_Get_FLEXCAN6_CLK_Frequency, /* FLEXCAN6_CLK clock */
1024 Clock_Ip_Get_FLEXCAN7_CLK_Frequency, /* FLEXCAN7_CLK clock */
1025 Clock_Ip_Get_FLEXCAN8_CLK_Frequency, /* FLEXCAN8_CLK clock */
1026 Clock_Ip_Get_FLEXCAN9_CLK_Frequency, /* FLEXCAN9_CLK clock */
1027 Clock_Ip_Get_FLEXCAN10_CLK_Frequency, /* FLEXCAN10_CLK clock */
1028 Clock_Ip_Get_FLEXCAN11_CLK_Frequency, /* FLEXCAN11_CLK clock */
1029 Clock_Ip_Get_FLEXCAN12_CLK_Frequency, /* FLEXCAN12_CLK clock */
1030 Clock_Ip_Get_FLEXCAN13_CLK_Frequency, /* FLEXCAN13_CLK clock */
1031 Clock_Ip_Get_FLEXCAN14_CLK_Frequency, /* FLEXCAN14_CLK clock */
1032 Clock_Ip_Get_FLEXCAN15_CLK_Frequency, /* FLEXCAN15_CLK clock */
1033 Clock_Ip_Get_FLEXCAN16_CLK_Frequency, /* FLEXCAN16_CLK clock */
1034 Clock_Ip_Get_FLEXCAN17_CLK_Frequency, /* FLEXCAN17_CLK clock */
1035 Clock_Ip_Get_FLEXCAN18_CLK_Frequency, /* FLEXCAN18_CLK clock */
1036 Clock_Ip_Get_FLEXCAN19_CLK_Frequency, /* FLEXCAN19_CLK clock */
1037 Clock_Ip_Get_FLEXCAN20_CLK_Frequency, /* FLEXCAN20_CLK clock */
1038 Clock_Ip_Get_FLEXCAN21_CLK_Frequency, /* FLEXCAN21_CLK clock */
1039 Clock_Ip_Get_FLEXCAN22_CLK_Frequency, /* FLEXCAN22_CLK clock */
1040 Clock_Ip_Get_FLEXCAN23_CLK_Frequency, /* FLEXCAN23_CLK clock */
1041 Clock_Ip_Get_P0_FR_PE_CLK_Frequency, /* P0_FR_PE_CLK clock */
1042 Clock_Ip_Get_FRAY0_CLK_Frequency, /* FRAY0_CLK clock */
1043 Clock_Ip_Get_FRAY1_CLK_Frequency, /* FRAY1_CLK clock */
1044 Clock_Ip_Get_GTM_CLK_Frequency, /* GTM_CLK clock */
1045 Clock_Ip_Get_IIIC0_CLK_Frequency, /* IIIC0_CLK clock */
1046 Clock_Ip_Get_IIIC1_CLK_Frequency, /* IIIC1_CLK clock */
1047 Clock_Ip_Get_IIIC2_CLK_Frequency, /* IIIC2_CLK clock */
1048 Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency, /* P0_LIN_BAUD_CLK clock */
1049 Clock_Ip_Get_LIN0_CLK_Frequency, /* LIN0_CLK clock */
1050 Clock_Ip_Get_LIN1_CLK_Frequency, /* LIN1_CLK clock */
1051 Clock_Ip_Get_LIN2_CLK_Frequency, /* LIN2_CLK clock */
1052 Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency, /* P1_LIN_BAUD_CLK clock */
1053 Clock_Ip_Get_LIN3_CLK_Frequency, /* LIN3_CLK clock */
1054 Clock_Ip_Get_LIN4_CLK_Frequency, /* LIN4_CLK clock */
1055 Clock_Ip_Get_LIN5_CLK_Frequency, /* LIN5_CLK clock */
1056 Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency, /* P4_LIN_BAUD_CLK clock */
1057 Clock_Ip_Get_LIN6_CLK_Frequency, /* LIN6_CLK clock */
1058 Clock_Ip_Get_LIN7_CLK_Frequency, /* LIN7_CLK clock */
1059 Clock_Ip_Get_LIN8_CLK_Frequency, /* LIN8_CLK clock */
1060 Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency, /* P5_LIN_BAUD_CLK clock */
1061 Clock_Ip_Get_LIN9_CLK_Frequency, /* LIN9_CLK clock */
1062 Clock_Ip_Get_LIN10_CLK_Frequency, /* LIN10_CLK clock */
1063 Clock_Ip_Get_LIN11_CLK_Frequency, /* LIN11_CLK clock */
1064 Clock_Ip_Get_MSCDSPI_CLK_Frequency, /* MSCDSPI_CLK clock */
1065 Clock_Ip_Get_MSCLIN_CLK_Frequency, /* MSCLIN_CLK clock */
1066 Clock_Ip_Get_NANO_CLK_Frequency, /* NANO_CLK clock */
1067 Clock_Ip_Get_P0_CLKOUT_SRC_CLK_Frequency, /* P0_CLKOUT_SRC_CLK clock */
1068 Clock_Ip_Get_P0_CTU_PER_CLK_Frequency, /* P0_CTU_PER_CLK clock */
1069 Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency, /* P0_DSPI_MSC_CLK clock */
1070 Clock_Ip_Get_P0_EMIOS_LCU_CLK_Frequency, /* P0_EMIOS_LCU_CLK clock */
1071 Clock_Ip_Get_P0_GTM_CLK_Frequency, /* P0_GTM_CLK clock */
1072 Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency, /* P0_GTM_NOC_CLK clock */
1073 Clock_Ip_Get_P0_GTM_TS_CLK_Frequency, /* P0_GTM_TS_CLK clock */
1074 Clock_Ip_Get_P0_LIN_CLK_Frequency, /* P0_LIN_CLK clock */
1075 Clock_Ip_Get_P0_NANO_CLK_Frequency, /* P0_NANO_CLK clock */
1076 Clock_Ip_Get_P0_PSI5_125K_CLK_Frequency, /* P0_PSI5_125K_CLK clock */
1077 Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency, /* P0_PSI5_189K_CLK clock */
1078 Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency, /* P0_PSI5_S_BAUD_CLK clock */
1079 Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency, /* P0_PSI5_S_CORE_CLK clock */
1080 Clock_Ip_Get_P0_PSI5_S_TRIG0_CLK_Frequency, /* P0_PSI5_S_TRIG0_CLK clock */
1081 Clock_Ip_Get_P0_PSI5_S_TRIG1_CLK_Frequency, /* P0_PSI5_S_TRIG1_CLK clock */
1082 Clock_Ip_Get_P0_PSI5_S_TRIG2_CLK_Frequency, /* P0_PSI5_S_TRIG2_CLK clock */
1083 Clock_Ip_Get_P0_PSI5_S_TRIG3_CLK_Frequency, /* P0_PSI5_S_TRIG3_CLK clock */
1084 Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency, /* P0_PSI5_S_UART_CLK clock */
1085 Clock_Ip_Get_P0_PSI5_S_WDOG0_CLK_Frequency, /* P0_PSI5_S_WDOG0_CLK clock */
1086 Clock_Ip_Get_P0_PSI5_S_WDOG1_CLK_Frequency, /* P0_PSI5_S_WDOG1_CLK clock */
1087 Clock_Ip_Get_P0_PSI5_S_WDOG2_CLK_Frequency, /* P0_PSI5_S_WDOG2_CLK clock */
1088 Clock_Ip_Get_P0_PSI5_S_WDOG3_CLK_Frequency, /* P0_PSI5_S_WDOG3_CLK clock */
1089 Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency, /* P0_REG_INTF_2X_CLK clock */
1090 Clock_Ip_Get_P0_REG_INTF_CLK_Frequency, /* P0_REG_INTF_CLK clock */
1091 Clock_Ip_Get_P1_CLKOUT_SRC_CLK_Frequency, /* P1_CLKOUT_SRC_CLK clock */
1092 Clock_Ip_Get_P1_DSPI60_CLK_Frequency, /* P1_DSPI60_CLK clock */
1093 Clock_Ip_Get_ETH_TS_CLK_Frequency, /* ETH_TS_CLK clock */
1094 Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency, /* ETH_TS_DIV4_CLK clock */
1095 Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency, /* ETH0_REF_RMII_CLK clock */
1096 Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency, /* ETH0_RX_MII_CLK clock */
1097 Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency, /* ETH0_RX_RGMII_CLK clock */
1098 Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency, /* ETH0_TX_RGMII_CLK clock */
1099 Clock_Ip_Get_ETH0_TX_RGMII_LPBK_CLK_Frequency, /* ETH0_TX_RGMII_LPBK_CLK clock */
1100 Clock_Ip_Get_ETH1_REF_RMII_CLK_Frequency, /* ETH1_REF_RMII_CLK clock */
1101 Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency, /* ETH1_RX_MII_CLK clock */
1102 Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency, /* ETH1_RX_RGMII_CLK clock */
1103 Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency, /* ETH1_TX_MII_CLK clock */
1104 Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency, /* ETH1_TX_RGMII_CLK clock */
1105 Clock_Ip_Get_ETH1_TX_RGMII_LPBK_CLK_Frequency, /* ETH1_TX_RGMII_LPBK_CLK clock */
1106 Clock_Ip_Get_P1_LFAST0_REF_CLK_Frequency, /* P1_LFAST0_REF_CLK clock */
1107 Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency, /* P1_LFAST1_REF_CLK clock */
1108 Clock_Ip_Get_P1_LFAST_DFT_CLK_Frequency, /* P1_LFAST_DFT_CLK clock */
1109 Clock_Ip_Get_P1_NETC_AXI_CLK_Frequency, /* P1_NETC_AXI_CLK clock */
1110 Clock_Ip_Get_P1_LIN_CLK_Frequency, /* P1_LIN_CLK clock */
1111 Clock_Ip_Get_P1_REG_INTF_CLK_Frequency, /* P1_REG_INTF_CLK clock */
1112 Clock_Ip_Get_P2_DBG_ATB_CLK_Frequency, /* P2_DBG_ATB_CLK clock */
1113 Clock_Ip_Get_P2_REG_INTF_CLK_Frequency, /* P2_REG_INTF_CLK clock */
1114 Clock_Ip_Get_P3_AES_CLK_Frequency, /* P3_AES_CLK clock */
1115 Clock_Ip_Get_P3_CLKOUT_SRC_CLK_Frequency, /* P3_CLKOUT_SRC_CLK clock */
1116 Clock_Ip_Get_P3_DBG_TS_CLK_Frequency, /* P3_DBG_TS_CLK clock */
1117 Clock_Ip_Get_P3_REG_INTF_CLK_Frequency, /* P3_REG_INTF_CLK clock */
1118 Clock_Ip_Get_P3_SYS_CLK_Frequency, /* P3_SYS_MON1_CLK clock */
1119 Clock_Ip_Get_P3_SYS_CLK_Frequency, /* P3_SYS_MON2_CLK clock */
1120 Clock_Ip_Get_P3_SYS_CLK_Frequency, /* P3_SYS_MON3_CLK clock */
1121 Clock_Ip_Get_P4_CLKOUT_SRC_CLK_Frequency, /* P4_CLKOUT_SRC_CLK clock */
1122 Clock_Ip_Get_P4_DSPI60_CLK_Frequency, /* P4_DSPI60_CLK clock */
1123 Clock_Ip_Get_P4_EMIOS_LCU_CLK_Frequency, /* P4_EMIOS_LCU_CLK clock */
1124 Clock_Ip_Get_P4_LIN_CLK_Frequency, /* P4_LIN_CLK clock */
1125 Clock_Ip_Get_P4_PSI5_125K_CLK_Frequency, /* P4_PSI5_125K_CLK clock */
1126 Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency, /* P4_PSI5_189K_CLK clock */
1127 Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency, /* P4_PSI5_S_BAUD_CLK clock */
1128 Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency, /* P4_PSI5_S_CORE_CLK clock */
1129 Clock_Ip_Get_P4_PSI5_S_TRIG0_CLK_Frequency, /* P4_PSI5_S_TRIG0_CLK clock */
1130 Clock_Ip_Get_P4_PSI5_S_TRIG1_CLK_Frequency, /* P4_PSI5_S_TRIG1_CLK clock */
1131 Clock_Ip_Get_P4_PSI5_S_TRIG2_CLK_Frequency, /* P4_PSI5_S_TRIG2_CLK clock */
1132 Clock_Ip_Get_P4_PSI5_S_TRIG3_CLK_Frequency, /* P4_PSI5_S_TRIG3_CLK clock */
1133 Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency, /* P4_PSI5_S_UART_CLK clock */
1134 Clock_Ip_Get_P4_PSI5_S_WDOG0_CLK_Frequency, /* P4_PSI5_S_WDOG0_CLK clock */
1135 Clock_Ip_Get_P4_PSI5_S_WDOG1_CLK_Frequency, /* P4_PSI5_S_WDOG1_CLK clock */
1136 Clock_Ip_Get_P4_PSI5_S_WDOG2_CLK_Frequency, /* P4_PSI5_S_WDOG2_CLK clock */
1137 Clock_Ip_Get_P4_PSI5_S_WDOG3_CLK_Frequency, /* P4_PSI5_S_WDOG3_CLK clock */
1138 Clock_Ip_Get_P4_QSPI0_2X_CLK_Frequency, /* P4_QSPI0_2X_CLK clock */
1139 Clock_Ip_Get_P4_QSPI0_1X_CLK_Frequency, /* P4_QSPI0_1X_CLK clock */
1140 Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency, /* P4_QSPI1_2X_CLK clock */
1141 Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency, /* P4_QSPI1_1X_CLK clock */
1142 Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency, /* P4_REG_INTF_2X_CLK clock */
1143 Clock_Ip_Get_P4_REG_INTF_CLK_Frequency, /* P4_REG_INTF_CLK clock */
1144 Clock_Ip_Get_P4_SDHC_IP_CLK_Frequency, /* P4_SDHC_IP_CLK clock */
1145 Clock_Ip_Get_P4_SDHC_IP_DIV2_CLK_Frequency, /* P4_SDHC_IP_DIV2_CLK clock */
1146 Clock_Ip_Get_P5_DIPORT_CLK_Frequency, /* P5_DIPORT_CLK clock */
1147 Clock_Ip_Get_P5_AE_CLK_Frequency, /* P5_AE_CLK clock */
1148 Clock_Ip_Get_P5_CANXL_PE_CLK_Frequency, /* P5_CANXL_PE_CLK clock */
1149 Clock_Ip_Get_P5_CANXL_CHI_CLK_Frequency, /* P5_CANXL_CHI_CLK clock */
1150 Clock_Ip_Get_P5_CLKOUT_SRC_CLK_Frequency, /* P5_CLKOUT_SRC_CLK clock */
1151 Clock_Ip_Get_P5_LIN_CLK_Frequency, /* P5_LIN_CLK clock */
1152 Clock_Ip_Get_P5_REG_INTF_CLK_Frequency, /* P5_REG_INTF_CLK clock */
1153 Clock_Ip_Get_P6_REG_INTF_CLK_Frequency, /* P6_REG_INTF_CLK clock */
1154 Clock_Ip_Get_PIT0_CLK_Frequency, /* PIT0_CLK clock */
1155 Clock_Ip_Get_PIT1_CLK_Frequency, /* PIT1_CLK clock */
1156 Clock_Ip_Get_PIT4_CLK_Frequency, /* PIT4_CLK clock */
1157 Clock_Ip_Get_PIT5_CLK_Frequency, /* PIT5_CLK clock */
1158 Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency, /* P0_PSI5_1US_CLK clock */
1159 Clock_Ip_Get_PSI5_0_CLK_Frequency, /* PSI5_0_CLK clock */
1160 Clock_Ip_Get_P4_PSI5_1US_CLK_Frequency, /* P4_PSI5_1US_CLK clock */
1161 Clock_Ip_Get_PSI5_1_CLK_Frequency, /* PSI5_1_CLK clock */
1162 Clock_Ip_Get_PSI5S_0_CLK_Frequency, /* PSI5S_0_CLK clock */
1163 Clock_Ip_Get_PSI5S_1_CLK_Frequency, /* PSI5S_1_CLK clock */
1164 Clock_Ip_Get_QSPI0_CLK_Frequency, /* QSPI0_CLK clock */
1165 Clock_Ip_Get_QSPI1_CLK_Frequency, /* QSPI1_CLK clock */
1166 Clock_Ip_Get_RTU0_CORE_CLK_Frequency, /* RTU0_CORE_MON1_CLK clock */
1167 Clock_Ip_Get_RTU0_CORE_CLK_Frequency, /* RTU0_CORE_MON2_CLK clock */
1168 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency, /* RTU0_CORE_DIV2_MON1_CLK clock */
1169 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency, /* RTU0_CORE_DIV2_MON2_CLK clock */
1170 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency, /* RTU0_CORE_DIV2_MON3_CLK clock */
1171 Clock_Ip_Get_RTU0_REG_INTF_CLK_Frequency, /* RTU0_REG_INTF_CLK clock */
1172 Clock_Ip_Get_RTU1_CORE_CLK_Frequency, /* RTU1_CORE_MON1_CLK clock */
1173 Clock_Ip_Get_RTU1_CORE_CLK_Frequency, /* RTU1_CORE_MON2_CLK clock */
1174 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency, /* RTU1_CORE_DIV2_MON1_CLK clock */
1175 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency, /* RTU1_CORE_DIV2_MON2_CLK clock */
1176 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency, /* RTU1_CORE_DIV2_MON3_CLK clock */
1177 Clock_Ip_Get_RTU1_REG_INTF_CLK_Frequency, /* RTU1_REG_INTF_CLK clock */
1178 Clock_Ip_Get_P4_SDHC_CLK_Frequency, /* P4_SDHC_CLK clock */
1179 Clock_Ip_Get_RXLUT_CLK_Frequency, /* RXLUT_CLK clock */
1180 Clock_Ip_Get_SDHC0_CLK_Frequency, /* SDHC0_CLK clock */
1181 Clock_Ip_Get_SINC_CLK_Frequency, /* SINC_CLK clock */
1182 Clock_Ip_Get_SIPI0_CLK_Frequency, /* SIPI0_CLK clock */
1183 Clock_Ip_Get_SIPI1_CLK_Frequency, /* SIPI1_CLK clock */
1184 Clock_Ip_Get_SIUL2_0_CLK_Frequency, /* SIUL2_0_CLK clock */
1185 Clock_Ip_Get_SIUL2_1_CLK_Frequency, /* SIUL2_1_CLK clock */
1186 Clock_Ip_Get_SIUL2_4_CLK_Frequency, /* SIUL2_4_CLK clock */
1187 Clock_Ip_Get_SIUL2_5_CLK_Frequency, /* SIUL2_5_CLK clock */
1188 Clock_Ip_Get_P0_DSPI_CLK_Frequency, /* P0_DSPI_CLK clock */
1189 Clock_Ip_Get_SPI0_CLK_Frequency, /* SPI0_CLK clock */
1190 Clock_Ip_Get_SPI1_CLK_Frequency, /* SPI1_CLK clock */
1191 Clock_Ip_Get_P1_DSPI_CLK_Frequency, /* P1_DSPI_CLK clock */
1192 Clock_Ip_Get_SPI2_CLK_Frequency, /* SPI2_CLK clock */
1193 Clock_Ip_Get_SPI3_CLK_Frequency, /* SPI3_CLK clock */
1194 Clock_Ip_Get_SPI4_CLK_Frequency, /* SPI4_CLK clock */
1195 Clock_Ip_Get_P4_DSPI_CLK_Frequency, /* P4_DSPI_CLK clock */
1196 Clock_Ip_Get_SPI5_CLK_Frequency, /* SPI5_CLK clock */
1197 Clock_Ip_Get_SPI6_CLK_Frequency, /* SPI6_CLK clock */
1198 Clock_Ip_Get_SPI7_CLK_Frequency, /* SPI7_CLK clock */
1199 Clock_Ip_Get_P5_DSPI_CLK_Frequency, /* P5_DSPI_CLK clock */
1200 Clock_Ip_Get_SPI8_CLK_Frequency, /* SPI8_CLK clock */
1201 Clock_Ip_Get_SPI9_CLK_Frequency, /* SPI9_CLK clock */
1202 Clock_Ip_Get_SRX0_CLK_Frequency, /* SRX0_CLK clock */
1203 Clock_Ip_Get_SRX1_CLK_Frequency, /* SRX1_CLK clock */
1204 Clock_Ip_Get_CORE_PLL_REFCLKOUT_Frequency, /* CORE_PLL_REFCLKOUT clock */
1205 Clock_Ip_Get_COREPLL_CLK_Frequency, /* CORE_PLL_FBCLKOUT clock */
1206 Clock_Ip_Get_PERIPH_PLL_REFCLKOUT_Frequency, /* PERIPH_PLL_REFCLKOUT clock */
1207 Clock_Ip_Get_PERIPHPLL_CLK_Frequency, /* PERIPH_PLL_FBCLKOUT clock */
1208 };
1209
1210 #if defined(CLOCK_IP_HAS_SYSTEM_CLK)
1211 static const getFreqType Clock_Ip_apfFreqTableAeClkSrc[CLOCK_IP_SELECTOR_SOURCE_NO] =
1212 {
1213 Clock_Ip_Get_FIRC_AE_CLK_Frequency, /* clock name for 0 hardware value */
1214 Clock_Ip_Get_P5_AE_CLK_Frequency, /* clock name for 1 hardware value */
1215 Clock_Ip_Get_Zero_Frequency, /* clock name for 2 hardware value */
1216 Clock_Ip_Get_Zero_Frequency, /* clock name for 3 hardware value */
1217 Clock_Ip_Get_Zero_Frequency, /* clock name for 4 hardware value */
1218 Clock_Ip_Get_Zero_Frequency, /* clock name for 5 hardware value */
1219 Clock_Ip_Get_Zero_Frequency, /* clock name for 6 hardware value */
1220 Clock_Ip_Get_Zero_Frequency, /* clock name for 7 hardware value */
1221 Clock_Ip_Get_Zero_Frequency, /* clock name for 8 hardware value */
1222 Clock_Ip_Get_Zero_Frequency, /* clock name for 9 hardware value */
1223 Clock_Ip_Get_Zero_Frequency, /* clock name for 10 hardware value */
1224 Clock_Ip_Get_Zero_Frequency, /* clock name for 11 hardware value */
1225 Clock_Ip_Get_Zero_Frequency, /* clock name for 12 hardware value */
1226 Clock_Ip_Get_Zero_Frequency, /* clock name for 13 hardware value */
1227 Clock_Ip_Get_Zero_Frequency, /* clock name for 14 hardware value */
1228 Clock_Ip_Get_Zero_Frequency, /* clock name for 15 hardware value */
1229 Clock_Ip_Get_Zero_Frequency, /* clock name for 16 hardware value */
1230 Clock_Ip_Get_Zero_Frequency, /* clock name for 17 hardware value */
1231 Clock_Ip_Get_Zero_Frequency, /* clock name for 18 hardware value */
1232 Clock_Ip_Get_Zero_Frequency, /* clock name for 19 hardware value */
1233 Clock_Ip_Get_Zero_Frequency, /* clock name for 20 hardware value */
1234 Clock_Ip_Get_Zero_Frequency, /* clock name for 21 hardware value */
1235 Clock_Ip_Get_Zero_Frequency, /* clock name for 22 hardware value */
1236 Clock_Ip_Get_Zero_Frequency, /* clock name for 23 hardware value */
1237 Clock_Ip_Get_Zero_Frequency, /* clock name for 24 hardware value */
1238 Clock_Ip_Get_Zero_Frequency, /* clock name for 25 hardware value */
1239 Clock_Ip_Get_Zero_Frequency, /* clock name for 26 hardware value */
1240 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
1241 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
1242 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
1243 Clock_Ip_Get_Zero_Frequency, /* clock name for 30 hardware value */
1244 Clock_Ip_Get_Zero_Frequency, /* clock name for 31 hardware value */
1245 Clock_Ip_Get_Zero_Frequency, /* clock name for 32 hardware value */
1246 Clock_Ip_Get_Zero_Frequency, /* clock name for 33 hardware value */
1247 Clock_Ip_Get_Zero_Frequency, /* clock name for 34 hardware value */
1248 Clock_Ip_Get_Zero_Frequency, /* clock name for 35 hardware value */
1249 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
1250 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
1251 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
1252 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
1253 Clock_Ip_Get_Zero_Frequency, /* clock name for 40 hardware value */
1254 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
1255 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
1256 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
1257 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
1258 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
1259 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
1260 Clock_Ip_Get_Zero_Frequency, /* clock name for 47 hardware value */
1261 Clock_Ip_Get_Zero_Frequency, /* clock name for 48 hardware value */
1262 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
1263 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
1264 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
1265 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
1266 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
1267 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
1268 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
1269 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
1270 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
1271 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
1272 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
1273 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
1274 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
1275 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
1276 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
1277 };
1278 #endif
1279
1280 /* Clock stop constant section data */
1281 #define MCU_STOP_SEC_CONST_UNSPECIFIED
1282 #include "Mcu_MemMap.h"
1283
1284 /*==================================================================================================
1285 LOCAL VARIABLES
1286 ==================================================================================================*/
1287
1288 /*==================================================================================================
1289 GLOBAL CONSTANTS
1290 ==================================================================================================*/
1291
1292 /*==================================================================================================
1293 GLOBAL VARIABLES
1294 ==================================================================================================*/
1295
1296 /* Clock start initialized section data */
1297 #define MCU_START_SEC_VAR_INIT_UNSPECIFIED
1298 #include "Mcu_MemMap.h"
1299
1300 /* External oscillators */
1301 static uint32 Clock_Ip_u32Fxosc = CLOCK_IP_DEFAULT_FXOSC_FREQUENCY;
1302 static extSignalFreq Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_EXT_SIGNALS_NO] = {{ETH_RGMII_REF_CLK,0U},{ETH_EXT_TS_CLK,0U},{ETH0_EXT_RX_CLK,0U},{ETH0_EXT_TX_CLK,0U},{ETH1_EXT_RX_CLK,0U},{ETH1_EXT_TX_CLK,0U},{LFAST0_EXT_REF_CLK,0U},{LFAST1_EXT_REF_CLK,0U}};
1303
1304 static uint32 Clock_Ip_u32CorePllFreq = CLOCK_IP_COREPLL_FREQ;
1305 static uint32 Clock_Ip_u32CorePllChecksum = CLOCK_IP_COREPLL_CHECKSUM;
1306 static uint32 Clock_Ip_u32PeriphPllFreq = CLOCK_IP_PERIPHPLL_FREQ;
1307 static uint32 Clock_Ip_u32PeriphPllChecksum = CLOCK_IP_PERIPHPLL_CHECKSUM;
1308 static uint32 Clock_Ip_u32DdrPllFreq = CLOCK_IP_DDRPLL_FREQ;
1309 static uint32 Clock_Ip_u32DdrPllChecksum = CLOCK_IP_DDRPLL_CHECKSUM;
1310 static uint32 Clock_Ip_u32CoreDfs1Freq = CLOCK_IP_COREDFS1_FREQ;
1311 static uint32 Clock_Ip_u32CoreDfs1Checksum = CLOCK_IP_COREDFS1_CHECKSUM;
1312 static uint32 Clock_Ip_u32CoreDfs2Freq = CLOCK_IP_COREDFS2_FREQ;
1313 static uint32 Clock_Ip_u32CoreDfs2Checksum = CLOCK_IP_COREDFS2_CHECKSUM;
1314 static uint32 Clock_Ip_u32CoreDfs3Freq = CLOCK_IP_COREDFS3_FREQ;
1315 static uint32 Clock_Ip_u32CoreDfs3Checksum = CLOCK_IP_COREDFS3_CHECKSUM;
1316 static uint32 Clock_Ip_u32CoreDfs4Freq = CLOCK_IP_COREDFS4_FREQ;
1317 static uint32 Clock_Ip_u32CoreDfs4Checksum = CLOCK_IP_COREDFS4_CHECKSUM;
1318 static uint32 Clock_Ip_u32CoreDfs5Freq = CLOCK_IP_COREDFS5_FREQ;
1319 static uint32 Clock_Ip_u32CoreDfs5Checksum = CLOCK_IP_COREDFS5_CHECKSUM;
1320 static uint32 Clock_Ip_u32CoreDfs6Freq = CLOCK_IP_COREDFS6_FREQ;
1321 static uint32 Clock_Ip_u32CoreDfs6Checksum = CLOCK_IP_COREDFS6_CHECKSUM;
1322 static uint32 Clock_Ip_u32PeriphDfs1Freq = CLOCK_IP_PERIPHDFS1_FREQ;
1323 static uint32 Clock_Ip_u32PeriphDfs1Checksum = CLOCK_IP_PERIPHDFS1_CHECKSUM;
1324 static uint32 Clock_Ip_u32PeriphDfs2Freq = CLOCK_IP_PERIPHDFS2_FREQ;
1325 static uint32 Clock_Ip_u32PeriphDfs2Checksum = CLOCK_IP_PERIPHDFS2_CHECKSUM;
1326 static uint32 Clock_Ip_u32PeriphDfs3Freq = CLOCK_IP_PERIPHDFS3_FREQ;
1327 static uint32 Clock_Ip_u32PeriphDfs3Checksum = CLOCK_IP_PERIPHDFS3_CHECKSUM;
1328 static uint32 Clock_Ip_u32PeriphDfs4Freq = CLOCK_IP_PERIPHDFS4_FREQ;
1329 static uint32 Clock_Ip_u32PeriphDfs4Checksum = CLOCK_IP_PERIPHDFS4_CHECKSUM;
1330 static uint32 Clock_Ip_u32PeriphDfs5Freq = CLOCK_IP_PERIPHDFS5_FREQ;
1331 static uint32 Clock_Ip_u32PeriphDfs5Checksum = CLOCK_IP_PERIPHDFS5_CHECKSUM;
1332 static uint32 Clock_Ip_u32PeriphDfs6Freq = CLOCK_IP_PERIPHDFS6_FREQ;
1333 static uint32 Clock_Ip_u32PeriphDfsChecksum = CLOCK_IP_PERIPHDFS6_CHECKSUM;
1334
1335 static uint32 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX0;
1336 static uint32 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
1337
1338 /* Clock stop initialized section data */
1339 #define MCU_STOP_SEC_VAR_INIT_UNSPECIFIED
1340 #include "Mcu_MemMap.h"
1341
1342
1343
1344 /*==================================================================================================
1345 LOCAL FUNCTIONS
1346 ==================================================================================================*/
1347 /* Clock start section code */
1348 #define MCU_START_SEC_CODE
1349 #include "Mcu_MemMap.h"
1350
1351 /* Return zero frequency */
Clock_Ip_Get_Zero_Frequency(void)1352 static uint32 Clock_Ip_Get_Zero_Frequency(void)
1353 {
1354 return 0U;
1355 }
1356 /* Return FIRC_CLK frequency */
Clock_Ip_Get_FIRC_CLK_Frequency(void)1357 static uint32 Clock_Ip_Get_FIRC_CLK_Frequency(void) {
1358
1359 return CLOCK_IP_FIRC_FREQUENCY;
1360 }
1361 /* Return FXOSC_CLK frequency */
Clock_Ip_Get_FXOSC_CLK_Frequency(void)1362 static uint32 Clock_Ip_Get_FXOSC_CLK_Frequency(void) {
1363
1364 return Clock_Ip_u32Fxosc;
1365 }
1366 /* Return SIRC_CLK frequency */
Clock_Ip_Get_SIRC_CLK_Frequency(void)1367 static uint32 Clock_Ip_Get_SIRC_CLK_Frequency(void) {
1368
1369 return CLOCK_IP_SIRC_FREQUENCY;
1370 }
1371
1372 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK)
1373 /* Return FIRC_AE_CLK frequency */
Clock_Ip_Get_FIRC_AE_CLK_Frequency(void)1374 static uint32 Clock_Ip_Get_FIRC_AE_CLK_Frequency(void){
1375
1376 return CLOCK_IP_FIRC_AE_FREQUENCY;
1377 }
1378 #endif
1379
1380 /* Return COREPLL_CLK frequency */
Clock_Ip_Get_COREPLL_CLK_Frequency(void)1381 static uint32 Clock_Ip_Get_COREPLL_CLK_Frequency(void) {
1382
1383 if (Clock_Ip_u32CorePllChecksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD))
1384 {
1385 Clock_Ip_u32CorePllChecksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD);
1386 Clock_Ip_u32CorePllFreq = PLL_VCO(IP_CORE_PLL);
1387 }
1388 return (((IP_CORE_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Clock_Ip_u32CorePllFreq : 0U;
1389 }
1390 /* Return PERIPHPLL_CLK frequency */
Clock_Ip_Get_PERIPHPLL_CLK_Frequency(void)1391 static uint32 Clock_Ip_Get_PERIPHPLL_CLK_Frequency(void) {
1392
1393 if (Clock_Ip_u32PeriphPllChecksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD))
1394 {
1395 Clock_Ip_u32PeriphPllChecksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD);
1396 Clock_Ip_u32PeriphPllFreq = PLL_VCO(IP_PERIPH_PLL);
1397 }
1398 return (((IP_PERIPH_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Clock_Ip_u32PeriphPllFreq : 0U;
1399 }
1400 /* Return DDRPLL_CLK frequency */
Clock_Ip_Get_DDRPLL_CLK_Frequency(void)1401 static uint32 Clock_Ip_Get_DDRPLL_CLK_Frequency(void) {
1402
1403 if (Clock_Ip_u32DdrPllChecksum != (IP_DDR_PLL->PLLCLKMUX ^ IP_DDR_PLL->PLLDV ^ IP_DDR_PLL->PLLFD))
1404 {
1405 Clock_Ip_u32DdrPllChecksum = (IP_DDR_PLL->PLLCLKMUX ^ IP_DDR_PLL->PLLDV ^ IP_DDR_PLL->PLLFD);
1406 Clock_Ip_u32DdrPllFreq = PLL_VCO(IP_DDR_PLL);
1407 }
1408 return (((IP_DDR_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Clock_Ip_u32DdrPllFreq : 0U;
1409 }
1410 /* Return COREPLL_PHI0 frequency */
Clock_Ip_Get_COREPLL_PHI0_Frequency(void)1411 static uint32 Clock_Ip_Get_COREPLL_PHI0_Frequency(void) {
1412
1413 uint32 Frequency = Clock_Ip_Get_COREPLL_CLK_Frequency();
1414 Frequency &= Clock_Ip_au32EnableDivider[((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1415 Frequency /= (((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1416 return Frequency;
1417 }
1418
1419 /* Return COREPLL_DFS0 frequency */
Clock_Ip_Get_COREPLL_DFS0_Frequency(void)1420 static uint32 Clock_Ip_Get_COREPLL_DFS0_Frequency(void) {
1421
1422 if (Clock_Ip_u32CoreDfs1Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[0U]))
1423 {
1424 Clock_Ip_u32CoreDfs1Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[0U]);
1425 Clock_Ip_u32CoreDfs1Freq = DFS_OUTPUT(IP_CORE_DFS,0U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1426 }
1427 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_0_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs1Freq : 0U;
1428 }
1429 /* Return COREPLL_DFS1 frequency */
Clock_Ip_Get_COREPLL_DFS1_Frequency(void)1430 static uint32 Clock_Ip_Get_COREPLL_DFS1_Frequency(void) {
1431
1432 if (Clock_Ip_u32CoreDfs2Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[1U]))
1433 {
1434 Clock_Ip_u32CoreDfs2Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[1U]);
1435 Clock_Ip_u32CoreDfs2Freq = DFS_OUTPUT(IP_CORE_DFS,1U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1436 }
1437 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_1_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs2Freq : 0U;
1438 }
1439 /* Return COREPLL_DFS2 frequency */
Clock_Ip_Get_COREPLL_DFS2_Frequency(void)1440 static uint32 Clock_Ip_Get_COREPLL_DFS2_Frequency(void) {
1441
1442 if (Clock_Ip_u32CoreDfs3Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[2U]))
1443 {
1444 Clock_Ip_u32CoreDfs3Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[2U]);
1445 Clock_Ip_u32CoreDfs3Freq = DFS_OUTPUT(IP_CORE_DFS,2U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1446 }
1447 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_2_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs3Freq : 0U;
1448 }
1449 /* Return COREPLL_DFS3 frequency */
Clock_Ip_Get_COREPLL_DFS3_Frequency(void)1450 static uint32 Clock_Ip_Get_COREPLL_DFS3_Frequency(void) {
1451
1452 if (Clock_Ip_u32CoreDfs4Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[3U]))
1453 {
1454 Clock_Ip_u32CoreDfs4Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[3U]);
1455 Clock_Ip_u32CoreDfs4Freq = DFS_OUTPUT(IP_CORE_DFS,3U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1456 }
1457 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_3_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs4Freq : 0U;
1458 }
1459 /* Return COREPLL_DFS4 frequency */
Clock_Ip_Get_COREPLL_DFS4_Frequency(void)1460 static uint32 Clock_Ip_Get_COREPLL_DFS4_Frequency(void) {
1461
1462 if (Clock_Ip_u32CoreDfs5Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[4U]))
1463 {
1464 Clock_Ip_u32CoreDfs5Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[4U]);
1465 Clock_Ip_u32CoreDfs5Freq = DFS_OUTPUT(IP_CORE_DFS,4U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1466 }
1467 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_4_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs5Freq : 0U;
1468 }
1469 /* Return COREPLL_DFS5 frequency */
Clock_Ip_Get_COREPLL_DFS5_Frequency(void)1470 static uint32 Clock_Ip_Get_COREPLL_DFS5_Frequency(void) {
1471
1472 if (Clock_Ip_u32CoreDfs6Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[5U]))
1473 {
1474 Clock_Ip_u32CoreDfs6Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[5U]);
1475 Clock_Ip_u32CoreDfs6Freq = DFS_OUTPUT(IP_CORE_DFS,5U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1476 }
1477 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_5_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs6Freq : 0U;
1478 }
1479 /* Return PERIPHPLL_PHI0 frequency */
Clock_Ip_Get_PERIPHPLL_PHI0_Frequency(void)1480 static uint32 Clock_Ip_Get_PERIPHPLL_PHI0_Frequency(void) {
1481
1482 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1483 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1484 Frequency /= (((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1485 return Frequency;
1486 }
1487
1488 /* Return PERIPHPLL_PHI1 frequency */
Clock_Ip_Get_PERIPHPLL_PHI1_Frequency(void)1489 static uint32 Clock_Ip_Get_PERIPHPLL_PHI1_Frequency(void) {
1490
1491 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1492 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1493 Frequency /= (((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1494 return Frequency;
1495 }
1496 /* Return PERIPHPLL_PHI2 frequency */
Clock_Ip_Get_PERIPHPLL_PHI2_Frequency(void)1497 static uint32 Clock_Ip_Get_PERIPHPLL_PHI2_Frequency(void) {
1498
1499 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1500 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1501 Frequency /= (((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1502 return Frequency;
1503 }
1504 /* Return PERIPHPLL_PHI3 frequency */
Clock_Ip_Get_PERIPHPLL_PHI3_Frequency(void)1505 static uint32 Clock_Ip_Get_PERIPHPLL_PHI3_Frequency(void) {
1506
1507 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1508 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[3U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1509 Frequency /= (((IP_PERIPH_PLL->PLLODIV[3U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1510 return Frequency;
1511 }
1512 /* Return PERIPHPLL_PHI4 frequency */
Clock_Ip_Get_PERIPHPLL_PHI4_Frequency(void)1513 static uint32 Clock_Ip_Get_PERIPHPLL_PHI4_Frequency(void) {
1514
1515 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1516 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[4U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1517 Frequency /= (((IP_PERIPH_PLL->PLLODIV[4U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1518 return Frequency;
1519 }
1520 /* Return PERIPHPLL_PHI5 frequency */
Clock_Ip_Get_PERIPHPLL_PHI5_Frequency(void)1521 static uint32 Clock_Ip_Get_PERIPHPLL_PHI5_Frequency(void) {
1522
1523 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1524 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[5U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1525 Frequency /= (((IP_PERIPH_PLL->PLLODIV[5U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1526 return Frequency;
1527 }
1528 /* Return PERIPHPLL_PHI6 frequency */
Clock_Ip_Get_PERIPHPLL_PHI6_Frequency(void)1529 static uint32 Clock_Ip_Get_PERIPHPLL_PHI6_Frequency(void) {
1530
1531 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1532 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[6U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1533 Frequency /= (((IP_PERIPH_PLL->PLLODIV[6U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1534 return Frequency;
1535 }
1536
1537 /* Return PERIPHPLL_DFS0 frequency */
Clock_Ip_Get_PERIPHPLL_DFS0_Frequency(void)1538 static uint32 Clock_Ip_Get_PERIPHPLL_DFS0_Frequency(void) {
1539
1540 if (Clock_Ip_u32PeriphDfs1Checksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[0U]))
1541 {
1542 Clock_Ip_u32PeriphDfs1Checksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[0U]);
1543 Clock_Ip_u32PeriphDfs1Freq = DFS_OUTPUT(IP_PERIPH_DFS,0U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1544 }
1545 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_0_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs1Freq : 0U;
1546 }
1547 /* Return PERIPHPLL_DFS1 frequency */
Clock_Ip_Get_PERIPHPLL_DFS1_Frequency(void)1548 static uint32 Clock_Ip_Get_PERIPHPLL_DFS1_Frequency(void) {
1549
1550 if (Clock_Ip_u32PeriphDfs2Checksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[1U]))
1551 {
1552 Clock_Ip_u32PeriphDfs2Checksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[1U]);
1553 Clock_Ip_u32PeriphDfs2Freq = DFS_OUTPUT(IP_PERIPH_DFS,1U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1554 }
1555 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_1_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs2Freq : 0U;
1556 }
1557 /* Return PERIPHPLL_DFS2 frequency */
Clock_Ip_Get_PERIPHPLL_DFS2_Frequency(void)1558 static uint32 Clock_Ip_Get_PERIPHPLL_DFS2_Frequency(void) {
1559
1560 if (Clock_Ip_u32PeriphDfs3Checksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[2U]))
1561 {
1562 Clock_Ip_u32PeriphDfs3Checksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[2U]);
1563 Clock_Ip_u32PeriphDfs3Freq = DFS_OUTPUT(IP_PERIPH_DFS,2U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1564 }
1565 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_2_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs3Freq : 0U;
1566 }
1567 /* Return PERIPHPLL_DFS3 frequency */
Clock_Ip_Get_PERIPHPLL_DFS3_Frequency(void)1568 static uint32 Clock_Ip_Get_PERIPHPLL_DFS3_Frequency(void) {
1569
1570 if (Clock_Ip_u32PeriphDfs4Checksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[3U]))
1571 {
1572 Clock_Ip_u32PeriphDfs4Checksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[3U]);
1573 Clock_Ip_u32PeriphDfs4Freq = DFS_OUTPUT(IP_PERIPH_DFS,3U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1574 }
1575 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_3_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs4Freq : 0U;
1576 }
1577 /* Return PERIPHPLL_DFS4 frequency */
Clock_Ip_Get_PERIPHPLL_DFS4_Frequency(void)1578 static uint32 Clock_Ip_Get_PERIPHPLL_DFS4_Frequency(void) {
1579
1580 if (Clock_Ip_u32PeriphDfs5Checksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[4U]))
1581 {
1582 Clock_Ip_u32PeriphDfs5Checksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[4U]);
1583 Clock_Ip_u32PeriphDfs5Freq = DFS_OUTPUT(IP_PERIPH_DFS,4U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1584 }
1585 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_4_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs5Freq : 0U;
1586 }
1587 /* Return PERIPHPLL_DFS5 frequency */
Clock_Ip_Get_PERIPHPLL_DFS5_Frequency(void)1588 static uint32 Clock_Ip_Get_PERIPHPLL_DFS5_Frequency(void) {
1589
1590 if (Clock_Ip_u32PeriphDfsChecksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[5U]))
1591 {
1592 Clock_Ip_u32PeriphDfsChecksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[5U]);
1593 Clock_Ip_u32PeriphDfs6Freq = DFS_OUTPUT(IP_PERIPH_DFS,5U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1594 }
1595 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_5_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs6Freq : 0U;
1596 }
1597 /* Return DDRPLL_PHI0 frequency */
Clock_Ip_Get_DDRPLL_PHI0_Frequency(void)1598 static uint32 Clock_Ip_Get_DDRPLL_PHI0_Frequency(void) {
1599
1600 uint32 Frequency = Clock_Ip_Get_DDRPLL_CLK_Frequency();
1601 Frequency &= Clock_Ip_au32EnableDivider[((IP_DDR_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1602 Frequency /= (((IP_DDR_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1603 return Frequency;
1604 }
1605
1606 /* Return eth_rgmii_ref frequency */
Clock_Ip_Get_eth_rgmii_ref_Frequency(void)1607 static uint32 Clock_Ip_Get_eth_rgmii_ref_Frequency(void) {
1608
1609 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_ETH_RGMII_REF_CLK_INDEX_ENTRY].Frequency;
1610 }
1611
1612 /* Return eth_ext_ts frequency */
Clock_Ip_Get_eth_ext_ts_Frequency(void)1613 static uint32 Clock_Ip_Get_eth_ext_ts_Frequency(void) {
1614
1615 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_ETH_EXT_TS_CLK_INDEX_ENTRY].Frequency;
1616 }
1617
1618 /* Return eth0_ext_rx frequency */
Clock_Ip_Get_eth0_ext_rx_Frequency(void)1619 static uint32 Clock_Ip_Get_eth0_ext_rx_Frequency(void) {
1620
1621 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_ETH0_EXT_RX_CLK_INDEX_ENTRY].Frequency;
1622 }
1623 /* Return eth0_ext_tx frequency */
Clock_Ip_Get_eth0_ext_tx_Frequency(void)1624 static uint32 Clock_Ip_Get_eth0_ext_tx_Frequency(void) {
1625
1626 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_ETH0_EXT_TX_CLK_INDEX_ENTRY].Frequency;
1627 }
1628
1629 /* Return eth1_ext_rx frequency */
Clock_Ip_Get_eth1_ext_rx_Frequency(void)1630 static uint32 Clock_Ip_Get_eth1_ext_rx_Frequency(void) {
1631
1632 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_ETH1_EXT_RX_CLK_INDEX_ENTRY].Frequency;
1633 }
1634 /* Return eth1_ext_tx frequency */
Clock_Ip_Get_eth1_ext_tx_Frequency(void)1635 static uint32 Clock_Ip_Get_eth1_ext_tx_Frequency(void) {
1636
1637 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_ETH1_EXT_TX_CLK_INDEX_ENTRY].Frequency;
1638 }
1639
1640 /* Return lfast0_ext_ref frequency */
Clock_Ip_Get_lfast0_ext_ref_Frequency(void)1641 static uint32 Clock_Ip_Get_lfast0_ext_ref_Frequency(void) {
1642
1643 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_LFAST0_EXT_REF_CLK_INDEX_ENTRY].Frequency;
1644 }
1645 /* Return lfast1_ext_ref frequency */
Clock_Ip_Get_lfast1_ext_ref_Frequency(void)1646 static uint32 Clock_Ip_Get_lfast1_ext_ref_Frequency(void) {
1647
1648 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_LFAST1_EXT_REF_CLK_INDEX_ENTRY].Frequency;
1649 }
1650
1651 /* Return P0_FR_PE_CLK frequency */
Clock_Ip_Get_P0_FR_PE_CLK_Frequency(void)1652 static uint32 Clock_Ip_Get_P0_FR_PE_CLK_Frequency(void) {
1653
1654 uint32 Frequency;
1655 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
1656 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> MC_CGM_MUX_6_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1657 Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1658 return Frequency;
1659 }
1660 /* Return FRAY0_CLK frequency */
Clock_Ip_Get_FRAY0_CLK_Frequency(void)1661 static uint32 Clock_Ip_Get_FRAY0_CLK_Frequency(void) {
1662
1663 uint32 Frequency;
1664 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
1665 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> MC_CGM_MUX_6_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1666 Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1667 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->FR0PCTL & GPR0_PCTL_FR0PCTL_PCTL_MASK) >> GPR0_PCTL_FR0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1668 return Frequency;
1669 }
1670 /* Return FRAY1_CLK frequency */
Clock_Ip_Get_FRAY1_CLK_Frequency(void)1671 static uint32 Clock_Ip_Get_FRAY1_CLK_Frequency(void) {
1672
1673 uint32 Frequency;
1674 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
1675 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> MC_CGM_MUX_6_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1676 Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1677 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->FR1PCTL & GPR0_PCTL_FR1PCTL_PCTL_MASK) >> GPR0_PCTL_FR1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1678 return Frequency;
1679 }
1680
1681 /* Return GTM_CLK frequency */
Clock_Ip_Get_GTM_CLK_Frequency(void)1682 static uint32 Clock_Ip_Get_GTM_CLK_Frequency(void) {
1683
1684 uint32 Frequency;
1685 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
1686 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1687 Frequency /= (((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1688 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->GTMNANOPCTL & GPR0_PCTL_GTMNANOPCTL_PCTL_GTM_MASK) >> GPR0_PCTL_GTMNANOPCTL_PCTL_GTM_SHIFT)]; /* Apply peripheral clock gate */
1689 return Frequency;
1690 }
1691
1692 /* Return P0_LIN_BAUD_CLK frequency */
Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency(void)1693 static uint32 Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency(void) {
1694
1695 uint32 Frequency;
1696 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1697 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1698 Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1699 return Frequency;
1700 }
1701 /* Return LIN0_CLK frequency */
Clock_Ip_Get_LIN0_CLK_Frequency(void)1702 static uint32 Clock_Ip_Get_LIN0_CLK_Frequency(void) {
1703
1704 uint32 Frequency;
1705 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1706 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1707 Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1708 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->LIN0PCTL & GPR0_PCTL_LIN0PCTL_PCTL_MASK) >> GPR0_PCTL_LIN0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1709 return Frequency;
1710 }
1711 /* Return LIN1_CLK frequency */
Clock_Ip_Get_LIN1_CLK_Frequency(void)1712 static uint32 Clock_Ip_Get_LIN1_CLK_Frequency(void) {
1713
1714 uint32 Frequency;
1715 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1716 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1717 Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1718 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->LIN1PCTL & GPR0_PCTL_LIN1PCTL_PCTL_MASK) >> GPR0_PCTL_LIN1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1719 return Frequency;
1720 }
1721 /* Return LIN2_CLK frequency */
Clock_Ip_Get_LIN2_CLK_Frequency(void)1722 static uint32 Clock_Ip_Get_LIN2_CLK_Frequency(void) {
1723
1724 uint32 Frequency;
1725 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1726 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1727 Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1728 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->LIN2PCTL & GPR0_PCTL_LIN2PCTL_PCTL_MASK) >> GPR0_PCTL_LIN2PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1729 return Frequency;
1730 }
1731 /* Return P1_LIN_BAUD_CLK frequency */
Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency(void)1732 static uint32 Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency(void) {
1733
1734 uint32 Frequency;
1735 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1736 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1737 Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1738 return Frequency;
1739 }
1740 /* Return LIN3_CLK frequency */
Clock_Ip_Get_LIN3_CLK_Frequency(void)1741 static uint32 Clock_Ip_Get_LIN3_CLK_Frequency(void) {
1742
1743 uint32 Frequency;
1744 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1745 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1746 Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1747 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->LIN3PCTL & GPR1_PCTL_LIN3PCTL_PCTL_MASK) >> GPR1_PCTL_LIN3PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1748 return Frequency;
1749 }
1750 /* Return LIN4_CLK frequency */
Clock_Ip_Get_LIN4_CLK_Frequency(void)1751 static uint32 Clock_Ip_Get_LIN4_CLK_Frequency(void) {
1752
1753 uint32 Frequency;
1754 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1755 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1756 Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1757 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->LIN4PCTL & GPR1_PCTL_LIN4PCTL_PCTL_MASK) >> GPR1_PCTL_LIN4PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1758 return Frequency;
1759 }
1760 /* Return LIN5_CLK frequency */
Clock_Ip_Get_LIN5_CLK_Frequency(void)1761 static uint32 Clock_Ip_Get_LIN5_CLK_Frequency(void) {
1762
1763 uint32 Frequency;
1764 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1765 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1766 Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1767 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->LIN5PCTL & GPR1_PCTL_LIN5PCTL_PCTL_MASK) >> GPR1_PCTL_LIN5PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1768 return Frequency;
1769 }
1770 /* Return LIN9_CLK frequency */
Clock_Ip_Get_LIN9_CLK_Frequency(void)1771 static uint32 Clock_Ip_Get_LIN9_CLK_Frequency(void) {
1772
1773 uint32 Frequency;
1774 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1775 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1776 Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1777 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->LIN9PCTL & GPR5_PCTL_LIN9PCTL_PCTL_MASK) >> GPR5_PCTL_LIN9PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1778 return Frequency;
1779 }
1780 /* Return LIN10_CLK frequency */
Clock_Ip_Get_LIN10_CLK_Frequency(void)1781 static uint32 Clock_Ip_Get_LIN10_CLK_Frequency(void) {
1782
1783 uint32 Frequency;
1784 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1785 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1786 Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1787 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->LIN10PCTL & GPR5_PCTL_LIN10PCTL_PCTL_MASK) >> GPR5_PCTL_LIN10PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1788 return Frequency;
1789 }
1790 /* Return LIN11_CLK frequency */
Clock_Ip_Get_LIN11_CLK_Frequency(void)1791 static uint32 Clock_Ip_Get_LIN11_CLK_Frequency(void) {
1792
1793 uint32 Frequency;
1794 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1795 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1796 Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1797 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->LIN11PCTL & GPR5_PCTL_LIN11PCTL_PCTL_MASK) >> GPR5_PCTL_LIN11PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1798 return Frequency;
1799 }
1800
1801 /* Return MSCDSPI_CLK frequency */
Clock_Ip_Get_MSCDSPI_CLK_Frequency(void)1802 static uint32 Clock_Ip_Get_MSCDSPI_CLK_Frequency(void) {
1803
1804 uint32 Frequency;
1805 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
1806 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> MC_CGM_MUX_7_DC_1_DE_SHIFT)]; /* Divider enable/disable */
1807 Frequency /= (((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DIV_MASK) >> MC_CGM_MUX_7_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */ Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->MSCDSPIPCTL & GPR0_PCTL_MSCDSPIPCTL_PCTL_MASK) >> GPR0_PCTL_MSCDSPIPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1808 return Frequency;
1809 }
1810
1811 /* Return MSCLIN_CLK frequency */
Clock_Ip_Get_MSCLIN_CLK_Frequency(void)1812 static uint32 Clock_Ip_Get_MSCLIN_CLK_Frequency(void) {
1813
1814 uint32 Frequency;
1815 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1816 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1817 Frequency /= ((((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
1818 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->MSCLINPCTL & GPR0_PCTL_MSCLINPCTL_PCTL_MASK) >> GPR0_PCTL_MSCLINPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1819 return Frequency;
1820 }
1821
1822 /* Return NANO_CLK frequency */
Clock_Ip_Get_NANO_CLK_Frequency(void)1823 static uint32 Clock_Ip_Get_NANO_CLK_Frequency(void) {
1824
1825 uint32 Frequency;
1826 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
1827 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->GTMNANOPCTL & GPR0_PCTL_GTMNANOPCTL_PCTL_NANO_MASK) >> GPR0_PCTL_GTMNANOPCTL_PCTL_NANO_SHIFT)]; /* Apply peripheral clock gate */
1828 return Frequency;
1829 }
1830
1831 /* Return P5_LIN_BAUD_CLK frequency */
Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency(void)1832 static uint32 Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency(void) {
1833
1834 uint32 Frequency;
1835 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1836 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1837 Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1838 return Frequency;
1839 }
1840 /* Return P0_DSPI_CLK frequency */
Clock_Ip_Get_P0_DSPI_CLK_Frequency(void)1841 static uint32 Clock_Ip_Get_P0_DSPI_CLK_Frequency(void) {
1842
1843 uint32 Frequency;
1844 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
1845 return Frequency;
1846 }
1847 /* Return SPI0_CLK frequency */
Clock_Ip_Get_SPI0_CLK_Frequency(void)1848 static uint32 Clock_Ip_Get_SPI0_CLK_Frequency(void) {
1849
1850 uint32 Frequency;
1851 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
1852 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->DSPI0PCTL & GPR0_PCTL_DSPI0PCTL_PCTL_MASK) >> GPR0_PCTL_DSPI0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1853 return Frequency;
1854 }
1855
1856 /* Return SPI1_CLK frequency */
Clock_Ip_Get_SPI1_CLK_Frequency(void)1857 static uint32 Clock_Ip_Get_SPI1_CLK_Frequency(void) {
1858
1859 uint32 Frequency;
1860 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
1861 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->DSPI1PCTL & GPR0_PCTL_DSPI1PCTL_PCTL_MASK) >> GPR0_PCTL_DSPI1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1862 return Frequency;
1863 }
1864
1865 /* Return P0_NANO_CLK frequency */
Clock_Ip_Get_P0_NANO_CLK_Frequency(void)1866 static uint32 Clock_Ip_Get_P0_NANO_CLK_Frequency(void) {
1867
1868 uint32 Frequency;
1869 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
1870 return Frequency;
1871 }
1872 /* Return P0_PSI5_1US_CLK frequency */
Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency(void)1873 static uint32 Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency(void) {
1874
1875 uint32 Frequency;
1876 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1877 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1878 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1879 return Frequency;
1880 }
1881 /* Return PSI5_0_CLK frequency */
Clock_Ip_Get_PSI5_0_CLK_Frequency(void)1882 static uint32 Clock_Ip_Get_PSI5_0_CLK_Frequency(void) {
1883
1884 uint32 Frequency;
1885 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1886 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1887 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1888 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->PSI50PCTL & GPR0_PCTL_PSI50PCTL_PCTL_MASK) >> GPR0_PCTL_PSI50PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1889 return Frequency;
1890 }
1891 /* Return P0_PSI5_S_TRIG0_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_TRIG0_CLK_Frequency(void)1892 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG0_CLK_Frequency(void) {
1893
1894 uint32 Frequency;
1895 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
1896 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1897 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DE_MASK) >> MC_CGM_MUX_3_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1898 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1899 return Frequency;
1900 }
1901 /* Return P0_REG_INTF_CLK frequency */
Clock_Ip_Get_P0_REG_INTF_CLK_Frequency(void)1902 static uint32 Clock_Ip_Get_P0_REG_INTF_CLK_Frequency(void) {
1903
1904 uint32 Frequency;
1905 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
1906 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1907 Frequency /= (((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1908 return Frequency;
1909 }
1910 /* Return P1_DSPI_CLK frequency */
Clock_Ip_Get_P1_DSPI_CLK_Frequency(void)1911 static uint32 Clock_Ip_Get_P1_DSPI_CLK_Frequency(void) {
1912
1913 uint32 Frequency;
1914 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1915 return Frequency;
1916 }
1917 /* Return SPI2_CLK frequency */
Clock_Ip_Get_SPI2_CLK_Frequency(void)1918 static uint32 Clock_Ip_Get_SPI2_CLK_Frequency(void) {
1919
1920 uint32 Frequency;
1921 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1922 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->DSPI2PCTL & GPR1_PCTL_DSPI2PCTL_PCTL_MASK) >> GPR1_PCTL_DSPI2PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1923 return Frequency;
1924 }
1925
1926 /* Return SPI3_CLK frequency */
Clock_Ip_Get_SPI3_CLK_Frequency(void)1927 static uint32 Clock_Ip_Get_SPI3_CLK_Frequency(void) {
1928
1929 uint32 Frequency;
1930 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1931 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->DSPI3PCTL & GPR1_PCTL_DSPI3PCTL_PCTL_MASK) >> GPR1_PCTL_DSPI3PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1932 return Frequency;
1933 }
1934
1935 /* Return SPI4_CLK frequency */
Clock_Ip_Get_SPI4_CLK_Frequency(void)1936 static uint32 Clock_Ip_Get_SPI4_CLK_Frequency(void) {
1937
1938 uint32 Frequency;
1939 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1940 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->DSPI4PCTL & GPR1_PCTL_DSPI4PCTL_PCTL_MASK) >> GPR1_PCTL_DSPI4PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1941 return Frequency;
1942 }
1943 /* Return P1_LFAST0_REF_CLK frequency */
Clock_Ip_Get_P1_LFAST0_REF_CLK_Frequency(void)1944 static uint32 Clock_Ip_Get_P1_LFAST0_REF_CLK_Frequency(void) {
1945
1946 uint32 Frequency;
1947 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_11_CSS & MC_CGM_MUX_11_CSS_SELSTAT_MASK) >> MC_CGM_MUX_11_CSS_SELSTAT_SHIFT)]();/* Selector value */
1948 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_11_DC_0 & MC_CGM_MUX_11_DC_0_DE_MASK) >> MC_CGM_MUX_11_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1949 Frequency /= (((IP_MC_CGM_1->MUX_11_DC_0 & MC_CGM_MUX_11_DC_0_DIV_MASK) >> MC_CGM_MUX_11_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1950 return Frequency;
1951 }
1952 /* Return P1_REG_INTF_CLK frequency */
Clock_Ip_Get_P1_REG_INTF_CLK_Frequency(void)1953 static uint32 Clock_Ip_Get_P1_REG_INTF_CLK_Frequency(void) {
1954
1955 uint32 Frequency;
1956 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
1957 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1958 Frequency /= (((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1959 return Frequency;
1960 }
1961 /* Return P2_DBG_ATB_CLK frequency */
Clock_Ip_Get_P2_DBG_ATB_CLK_Frequency(void)1962 static uint32 Clock_Ip_Get_P2_DBG_ATB_CLK_Frequency(void) {
1963
1964 uint32 Frequency;
1965 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1966 return Frequency;
1967 }
1968 /* Return P2_REG_INTF_CLK frequency */
Clock_Ip_Get_P2_REG_INTF_CLK_Frequency(void)1969 static uint32 Clock_Ip_Get_P2_REG_INTF_CLK_Frequency(void) {
1970
1971 uint32 Frequency;
1972 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
1973 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_2->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1974 Frequency /= (((IP_MC_CGM_2->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1975 return Frequency;
1976 }
1977 /* Return P5_DSPI_CLK frequency */
Clock_Ip_Get_P5_DSPI_CLK_Frequency(void)1978 static uint32 Clock_Ip_Get_P5_DSPI_CLK_Frequency(void) {
1979
1980 uint32 Frequency;
1981 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1982 return Frequency;
1983 }
1984 /* Return SPI8_CLK frequency */
Clock_Ip_Get_SPI8_CLK_Frequency(void)1985 static uint32 Clock_Ip_Get_SPI8_CLK_Frequency(void) {
1986
1987 uint32 Frequency;
1988 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1989 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->DSPI8PCTL & GPR5_PCTL_DSPI8PCTL_PCTL_MASK) >> GPR5_PCTL_DSPI8PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1990 return Frequency;
1991 }
1992
1993 /* Return SPI9_CLK frequency */
Clock_Ip_Get_SPI9_CLK_Frequency(void)1994 static uint32 Clock_Ip_Get_SPI9_CLK_Frequency(void) {
1995
1996 uint32 Frequency;
1997 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1998 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->DSPI9PCTL & GPR5_PCTL_DSPI9PCTL_PCTL_MASK) >> GPR5_PCTL_DSPI9PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1999 return Frequency;
2000 }
2001 /* Return P5_REG_INTF_CLK frequency */
Clock_Ip_Get_P5_REG_INTF_CLK_Frequency(void)2002 static uint32 Clock_Ip_Get_P5_REG_INTF_CLK_Frequency(void) {
2003
2004 uint32 Frequency;
2005 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2006 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2007 Frequency /= (((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2008 return Frequency;
2009 }
2010
2011 /* Return DDR_CLK frequency */
Clock_Ip_Get_DDR_CLK_Frequency(void)2012 static uint32 Clock_Ip_Get_DDR_CLK_Frequency(void) {
2013
2014 uint32 Frequency;
2015 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_6->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2016 Frequency /= (((IP_MC_CGM_6->MUX_0_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2017 return Frequency;
2018 }
2019
2020 /* Return P0_SYS_CLK frequency */
Clock_Ip_Get_P0_SYS_CLK_Frequency(void)2021 static uint32 Clock_Ip_Get_P0_SYS_CLK_Frequency(void) {
2022
2023 uint32 Frequency;
2024 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2025 return Frequency;
2026 }
2027
2028 /* Return P1_SYS_CLK frequency */
Clock_Ip_Get_P1_SYS_CLK_Frequency(void)2029 static uint32 Clock_Ip_Get_P1_SYS_CLK_Frequency(void) {
2030
2031 uint32 Frequency;
2032 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2033 return Frequency;
2034 }
2035
2036 /* Return P1_SYS_DIV2_CLK frequency */
Clock_Ip_Get_P1_SYS_DIV2_CLK_Frequency(void)2037 static uint32 Clock_Ip_Get_P1_SYS_DIV2_CLK_Frequency(void) {
2038
2039 uint32 Frequency;
2040 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2041 Frequency = Frequency >> 1U;
2042 return Frequency;
2043 }
2044
2045 /* Return P1_SYS_DIV4_CLK frequency */
Clock_Ip_Get_P1_SYS_DIV4_CLK_Frequency(void)2046 static uint32 Clock_Ip_Get_P1_SYS_DIV4_CLK_Frequency(void) {
2047
2048 uint32 Frequency;
2049 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2050 Frequency = Frequency >> 2U;
2051 return Frequency;
2052 }
2053
2054 /* Return P2_SYS_CLK frequency */
Clock_Ip_Get_P2_SYS_CLK_Frequency(void)2055 static uint32 Clock_Ip_Get_P2_SYS_CLK_Frequency(void) {
2056
2057 uint32 Frequency;
2058 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2059 return Frequency;
2060 }
2061
2062
2063 /* Return P2_SYS_DIV2_CLK frequency */
Clock_Ip_Get_P2_SYS_DIV2_CLK_Frequency(void)2064 static uint32 Clock_Ip_Get_P2_SYS_DIV2_CLK_Frequency(void) {
2065
2066 uint32 Frequency;
2067 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2068 Frequency = Frequency >> 1U;
2069 return Frequency;
2070 }
2071
2072 /* Return P2_SYS_DIV4_CLK frequency */
Clock_Ip_Get_P2_SYS_DIV4_CLK_Frequency(void)2073 static uint32 Clock_Ip_Get_P2_SYS_DIV4_CLK_Frequency(void) {
2074
2075 uint32 Frequency;
2076 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2077 Frequency = Frequency >> 2U;
2078 return Frequency;
2079 }
2080
2081 /* Return P3_SYS_CLK frequency */
Clock_Ip_Get_P3_SYS_CLK_Frequency(void)2082 static uint32 Clock_Ip_Get_P3_SYS_CLK_Frequency(void) {
2083
2084 uint32 Frequency;
2085 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2086 return Frequency;
2087 }
2088
2089 /* Return CE_SYS_DIV2_CLK frequency */
Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency(void)2090 static uint32 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency(void) {
2091
2092 uint32 Frequency;
2093 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2094 Frequency = Frequency >> 1U;
2095 return Frequency;
2096 }
2097
2098 /* Return P3_SYS_DIV2_NOC_CLK frequency */
Clock_Ip_Get_P3_SYS_DIV2_NOC_CLK_Frequency(void)2099 static uint32 Clock_Ip_Get_P3_SYS_DIV2_NOC_CLK_Frequency(void) {
2100
2101 uint32 Frequency;
2102 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2103 Frequency = Frequency >> 1U;
2104 return Frequency;
2105 }
2106
2107 /* Return P3_SYS_DIV4_CLK frequency */
Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency(void)2108 static uint32 Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency(void) {
2109
2110 uint32 Frequency;
2111 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2112 Frequency = Frequency >> 2U;
2113 return Frequency;
2114 }
2115
2116 /* Return P4_SYS_CLK frequency */
Clock_Ip_Get_P4_SYS_CLK_Frequency(void)2117 static uint32 Clock_Ip_Get_P4_SYS_CLK_Frequency(void) {
2118
2119 uint32 Frequency;
2120 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2121 return Frequency;
2122 }
2123
2124 /* Return P4_SYS_DIV2_CLK frequency */
Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency(void)2125 static uint32 Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency(void) {
2126
2127 uint32 Frequency;
2128 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2129 Frequency = Frequency >> 1U;
2130 return Frequency;
2131 }
2132
2133 /* Return HSE_SYS_DIV2_CLK frequency */
Clock_Ip_Get_HSE_SYS_DIV2_CLK_Frequency(void)2134 static uint32 Clock_Ip_Get_HSE_SYS_DIV2_CLK_Frequency(void) {
2135
2136 uint32 Frequency;
2137 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2138 Frequency = Frequency >> 1U;
2139 return Frequency;
2140 }
2141
2142 /* Return P5_SYS_CLK frequency */
Clock_Ip_Get_P5_SYS_CLK_Frequency(void)2143 static uint32 Clock_Ip_Get_P5_SYS_CLK_Frequency(void) {
2144
2145 uint32 Frequency;
2146 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2147 Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2148 return Frequency;
2149 }
2150
2151 /* Return P5_SYS_DIV2_CLK frequency */
Clock_Ip_Get_P5_SYS_DIV2_CLK_Frequency(void)2152 static uint32 Clock_Ip_Get_P5_SYS_DIV2_CLK_Frequency(void) {
2153
2154 uint32 Frequency;
2155 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2156 Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2157 Frequency = Frequency >> 1U;
2158 return Frequency;
2159 }
2160
2161 /* Return P5_SYS_DIV4_CLK frequency */
Clock_Ip_Get_P5_SYS_DIV4_CLK_Frequency(void)2162 static uint32 Clock_Ip_Get_P5_SYS_DIV4_CLK_Frequency(void) {
2163
2164 uint32 Frequency;
2165 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2166 Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2167 Frequency = Frequency >> 2U;
2168 return Frequency;
2169 }
2170
2171 /* Return P2_MATH_CLK frequency */
Clock_Ip_Get_P2_MATH_CLK_Frequency(void)2172 static uint32 Clock_Ip_Get_P2_MATH_CLK_Frequency(void) {
2173
2174 uint32 Frequency;
2175 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2176 return Frequency;
2177 }
2178
2179 /* Return P2_MATH_DIV3_CLK frequency */
Clock_Ip_Get_P2_MATH_DIV3_CLK_Frequency(void)2180 static uint32 Clock_Ip_Get_P2_MATH_DIV3_CLK_Frequency(void) {
2181
2182 uint32 Frequency;
2183 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2184 Frequency /= 3U;
2185 return Frequency;
2186 }
2187
2188 /* Return GLB_LBIST_CLK frequency */
Clock_Ip_Get_GLB_LBIST_CLK_Frequency(void)2189 static uint32 Clock_Ip_Get_GLB_LBIST_CLK_Frequency(void) {
2190
2191 uint32 Frequency;
2192 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
2193 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC_CGM_MUX_8_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2194 Frequency /= (((IP_MC_CGM_0->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2195 return Frequency;
2196 }
2197
2198 /* Return RTU0_CORE_CLK frequency */
Clock_Ip_Get_RTU0_CORE_CLK_Frequency(void)2199 static uint32 Clock_Ip_Get_RTU0_CORE_CLK_Frequency(void) {
2200
2201 uint32 Frequency;
2202 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_RTU0__MC_CGM->MUX_0_CSS & RTU_MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> RTU_MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2203 Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU0__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DE_MASK) >> RTU_MC_CGM_MUX_0_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2204 Frequency /= (((IP_RTU0__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2205 return Frequency;
2206 }
2207
2208 /* Return RTU0_CORE_DIV2_CLK frequency */
Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency(void)2209 static uint32 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency(void) {
2210
2211 uint32 Frequency;
2212 Frequency = Clock_Ip_Get_RTU0_CORE_CLK_Frequency();/* Selector value */
2213 Frequency = Frequency >> 1U;
2214 return Frequency;
2215 }
2216
2217 /* Return RTU1_CORE_CLK frequency */
Clock_Ip_Get_RTU1_CORE_CLK_Frequency(void)2218 static uint32 Clock_Ip_Get_RTU1_CORE_CLK_Frequency(void) {
2219
2220 uint32 Frequency;
2221 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_RTU1__MC_CGM->MUX_0_CSS & RTU_MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> RTU_MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2222 Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU1__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DE_MASK) >> RTU_MC_CGM_MUX_0_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2223 Frequency /= (((IP_RTU1__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2224 return Frequency;
2225 }
2226
2227 /* Return RTU1_CORE_DIV2_CLK frequency */
Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency(void)2228 static uint32 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency(void) {
2229
2230 uint32 Frequency;
2231 Frequency = Clock_Ip_Get_RTU1_CORE_CLK_Frequency();/* Selector value */
2232 Frequency = Frequency >> 1U;
2233 return Frequency;
2234 }
2235
2236 /* Return P0_PSI5_S_UTIL_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency(void)2237 static uint32 Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency(void) {
2238
2239 uint32 Frequency;
2240 if (0U == ((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT))
2241 {
2242 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2243 }
2244 else
2245 {
2246 Frequency = Clock_Ip_Get_PERIPHPLL_PHI4_Frequency();
2247 }
2248 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DE_MASK) >> MC_CGM_MUX_2_DC_3_DE_SHIFT)]; /* Divider enable/disable */
2249 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
2250 return Frequency;
2251 }
2252
2253 /* Return P4_PSI5_S_UTIL_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency(void)2254 static uint32 Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency(void) {
2255
2256 uint32 Frequency;
2257 if (0U == ((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT))
2258 {
2259 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2260 }
2261 else
2262 {
2263 Frequency = Clock_Ip_Get_PERIPHPLL_PHI4_Frequency();
2264 }
2265 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DE_MASK) >> MC_CGM_MUX_2_DC_3_DE_SHIFT)]; /* Divider enable/disable */
2266 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
2267 return Frequency;
2268 }
2269
2270 #if defined(CLOCK_IP_HAS_SYSTEM_CLK)
2271 /* Return SYSTEM_CLK frequency */
Clock_Ip_Get_SYSTEM_CLK_Frequency(void)2272 static uint32 Clock_Ip_Get_SYSTEM_CLK_Frequency(void) {
2273
2274 uint32 Frequency;
2275 Frequency = Clock_Ip_apfFreqTableAeClkSrc[((IP_MC_ME_AE->GS & MC_ME_AE_GS_S_SYSCLK_MASK) >> MC_ME_AE_GS_S_SYSCLK_SHIFT)]();/* Selector value */
2276 return Frequency;
2277 }
2278 #endif
2279
2280 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK)
2281 /* Return SYSTEM_DIV2_CLK frequency */
Clock_Ip_Get_SYSTEM_DIV2_CLK_Frequency(void)2282 static uint32 Clock_Ip_Get_SYSTEM_DIV2_CLK_Frequency(void)
2283 {
2284 return Clock_Ip_Get_SYSTEM_CLK_Frequency() >> 1U;
2285 }
2286 #endif
2287
2288 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_CLK)
2289 /* Return SYSTEM_DIV4_CLK frequency */
Clock_Ip_Get_SYSTEM_DIV4_CLK_Frequency(void)2290 static uint32 Clock_Ip_Get_SYSTEM_DIV4_CLK_Frequency(void)
2291 {
2292 return Clock_Ip_Get_SYSTEM_CLK_Frequency() >> 2U;
2293 }
2294 #endif
2295
2296
2297 /* Return ADC0_CLK frequency */
Clock_Ip_Get_ADC0_CLK_Frequency(void)2298 static uint32 Clock_Ip_Get_ADC0_CLK_Frequency(void) {
2299
2300 uint32 Frequency;
2301 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2302 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->ADC0PCTL & GPR0_PCTL_ADC0PCTL_PCTL_MASK) >> GPR0_PCTL_ADC0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2303 return Frequency;
2304 }
2305
2306 /* Return ADC1_CLK frequency */
Clock_Ip_Get_ADC1_CLK_Frequency(void)2307 static uint32 Clock_Ip_Get_ADC1_CLK_Frequency(void) {
2308
2309 uint32 Frequency;
2310 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2311 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->ADC1PCTL & GPR0_PCTL_ADC1PCTL_PCTL_MASK) >> GPR0_PCTL_ADC1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2312 return Frequency;
2313 }
2314
2315 /* Return CE_PIT0_CLK frequency */
Clock_Ip_Get_CE_PIT0_CLK_Frequency(void)2316 static uint32 Clock_Ip_Get_CE_PIT0_CLK_Frequency(void) {
2317
2318 uint32 Frequency;
2319 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2320 Frequency = Frequency >> 2U;
2321 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT0PCTL & GPR3_PCTL_PIT0PCTL_PCTL_MASK) >> GPR3_PCTL_PIT0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2322 return Frequency;
2323 }
2324
2325 /* Return CE_PIT1_CLK frequency */
Clock_Ip_Get_CE_PIT1_CLK_Frequency(void)2326 static uint32 Clock_Ip_Get_CE_PIT1_CLK_Frequency(void) {
2327
2328 uint32 Frequency;
2329 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2330 Frequency = Frequency >> 2U;
2331 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT1PCTL & GPR3_PCTL_PIT1PCTL_PCTL_MASK) >> GPR3_PCTL_PIT1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2332 return Frequency;
2333 }
2334
2335 /* Return CE_PIT2_CLK frequency */
Clock_Ip_Get_CE_PIT2_CLK_Frequency(void)2336 static uint32 Clock_Ip_Get_CE_PIT2_CLK_Frequency(void) {
2337
2338 uint32 Frequency;
2339 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2340 Frequency = Frequency >> 2U;
2341 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT2PCTL & GPR3_PCTL_PIT2PCTL_PCTL_MASK) >> GPR3_PCTL_PIT2PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2342 return Frequency;
2343 }
2344
2345 /* Return CE_PIT3_CLK frequency */
Clock_Ip_Get_CE_PIT3_CLK_Frequency(void)2346 static uint32 Clock_Ip_Get_CE_PIT3_CLK_Frequency(void) {
2347
2348 uint32 Frequency;
2349 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2350 Frequency = Frequency >> 2U;
2351 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT3PCTL & GPR3_PCTL_PIT3PCTL_PCTL_MASK) >> GPR3_PCTL_PIT3PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2352 return Frequency;
2353 }
2354
2355 /* Return CE_PIT4_CLK frequency */
Clock_Ip_Get_CE_PIT4_CLK_Frequency(void)2356 static uint32 Clock_Ip_Get_CE_PIT4_CLK_Frequency(void) {
2357
2358 uint32 Frequency;
2359 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2360 Frequency = Frequency >> 2U;
2361 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT4PCTL & GPR3_PCTL_PIT4PCTL_PCTL_MASK) >> GPR3_PCTL_PIT4PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2362 return Frequency;
2363 }
2364
2365 /* Return CE_PIT5_CLK frequency */
Clock_Ip_Get_CE_PIT5_CLK_Frequency(void)2366 static uint32 Clock_Ip_Get_CE_PIT5_CLK_Frequency(void) {
2367
2368 uint32 Frequency;
2369 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2370 Frequency = Frequency >> 2U;
2371 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT5PCTL & GPR3_PCTL_PIT5PCTL_PCTL_MASK) >> GPR3_PCTL_PIT5PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2372 return Frequency;
2373 }
2374
2375 /* Return CTU_CLK frequency */
Clock_Ip_Get_CTU_CLK_Frequency(void)2376 static uint32 Clock_Ip_Get_CTU_CLK_Frequency(void) {
2377
2378 uint32 Frequency;
2379 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
2380 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> MC_CGM_MUX_9_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2381 Frequency /= (((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2382 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->CTUPCTL & GPR0_PCTL_CTUPCTL_PCTL_MASK) >> GPR0_PCTL_CTUPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2383 return Frequency;
2384 }
2385
2386 /* Return DMACRC0_CLK frequency */
Clock_Ip_Get_DMACRC0_CLK_Frequency(void)2387 static uint32 Clock_Ip_Get_DMACRC0_CLK_Frequency(void) {
2388
2389 uint32 Frequency;
2390 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2391 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->EDMA0PCTL & GPR0_PCTL_EDMA0PCTL_PCTL_1_MASK) >> GPR0_PCTL_EDMA0PCTL_PCTL_1_SHIFT)]; /* Apply peripheral clock gate */
2392 return Frequency;
2393 }
2394
2395 /* Return DMACRC1_CLK frequency */
Clock_Ip_Get_DMACRC1_CLK_Frequency(void)2396 static uint32 Clock_Ip_Get_DMACRC1_CLK_Frequency(void) {
2397
2398 uint32 Frequency;
2399 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2400 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->EDMA1PCTL & GPR1_PCTL_EDMA1PCTL_PCTL_1_MASK) >> GPR1_PCTL_EDMA1PCTL_PCTL_1_SHIFT)]; /* Apply peripheral clock gate */
2401 return Frequency;
2402 }
2403
2404 /* Return DMACRC4_CLK frequency */
Clock_Ip_Get_DMACRC4_CLK_Frequency(void)2405 static uint32 Clock_Ip_Get_DMACRC4_CLK_Frequency(void) {
2406
2407 uint32 Frequency;
2408 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2409 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_1_MASK) >> GPR4_PCTL_EDMA4PCTL_PCTL_1_SHIFT)]; /* Apply peripheral clock gate */
2410 return Frequency;
2411 }
2412
2413 /* Return DMACRC5_CLK frequency */
Clock_Ip_Get_DMACRC5_CLK_Frequency(void)2414 static uint32 Clock_Ip_Get_DMACRC5_CLK_Frequency(void) {
2415
2416 uint32 Frequency;
2417 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2418 Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2419 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_1_MASK) >> GPR5_PCTL_EDMA5PCTL_PCTL_1_SHIFT)]; /* Apply peripheral clock gate */
2420 return Frequency;
2421 }
2422
2423 /* Return DMAMUX0_CLK frequency */
Clock_Ip_Get_DMAMUX0_CLK_Frequency(void)2424 static uint32 Clock_Ip_Get_DMAMUX0_CLK_Frequency(void) {
2425
2426 uint32 Frequency;
2427 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2428 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2429 Frequency /= (((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2430 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->EDMA0PCTL & GPR0_PCTL_EDMA0PCTL_PCTL_2_MASK) >> GPR0_PCTL_EDMA0PCTL_PCTL_2_SHIFT)]; /* Apply peripheral clock gate */
2431 return Frequency;
2432 }
2433
2434 /* Return DMAMUX1_CLK frequency */
Clock_Ip_Get_DMAMUX1_CLK_Frequency(void)2435 static uint32 Clock_Ip_Get_DMAMUX1_CLK_Frequency(void) {
2436
2437 uint32 Frequency;
2438 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2439 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2440 Frequency /= (((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2441 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->EDMA1PCTL & GPR1_PCTL_EDMA1PCTL_PCTL_2_MASK) >> GPR1_PCTL_EDMA1PCTL_PCTL_2_SHIFT)]; /* Apply peripheral clock gate */
2442 return Frequency;
2443 }
2444
2445 /* Return DMAMUX4_CLK frequency */
Clock_Ip_Get_DMAMUX4_CLK_Frequency(void)2446 static uint32 Clock_Ip_Get_DMAMUX4_CLK_Frequency(void) {
2447
2448 uint32 Frequency;
2449 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2450 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2451 Frequency /= (((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */ Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_2_MASK) >> GPR4_PCTL_EDMA4PCTL_PCTL_2_SHIFT)]; /* Apply peripheral clock gate */
2452 return Frequency;
2453 }
2454
2455 /* Return DMAMUX5_CLK frequency */
Clock_Ip_Get_DMAMUX5_CLK_Frequency(void)2456 static uint32 Clock_Ip_Get_DMAMUX5_CLK_Frequency(void) {
2457
2458 uint32 Frequency;
2459 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2460 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2461 Frequency /= (((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2462 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_2_MASK) >> GPR5_PCTL_EDMA5PCTL_PCTL_2_SHIFT)]; /* Apply peripheral clock gate */
2463 return Frequency;
2464 }
2465
2466 /* Return CLKOUT0_CLK frequency */
Clock_Ip_Get_CLKOUT0_CLK_Frequency(void)2467 static uint32 Clock_Ip_Get_CLKOUT0_CLK_Frequency(void) {
2468
2469 uint32 Frequency;
2470 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX0;
2471 if (0U == ((IP_MC_CGM_0->MUX_10_CSS & MC_CGM_MUX_10_CSS_SELSTAT_MASK) >> MC_CGM_MUX_10_CSS_SELSTAT_SHIFT))
2472 {
2473 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2474 }
2475 else
2476 {
2477 Frequency = Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency();
2478 }
2479 Frequency /= (((IP_MC_CGM_0->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DIV_MASK) >> MC_CGM_MUX_10_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2480 return Frequency;
2481 }
2482
2483 /* Return CLKOUT1_CLK frequency */
Clock_Ip_Get_CLKOUT1_CLK_Frequency(void)2484 static uint32 Clock_Ip_Get_CLKOUT1_CLK_Frequency(void) {
2485
2486 uint32 Frequency;
2487 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX1;
2488 if (0U == ((IP_MC_CGM_1->MUX_10_CSS & MC_CGM_MUX_10_CSS_SELSTAT_MASK) >> MC_CGM_MUX_10_CSS_SELSTAT_SHIFT))
2489 {
2490 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2491 }
2492 else
2493 {
2494 Frequency = Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency();
2495 }
2496 Frequency /= (((IP_MC_CGM_1->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DIV_MASK) >> MC_CGM_MUX_10_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2497 return Frequency;
2498 }
2499
2500 /* Return CLKOUT2_CLK frequency */
Clock_Ip_Get_CLKOUT2_CLK_Frequency(void)2501 static uint32 Clock_Ip_Get_CLKOUT2_CLK_Frequency(void) {
2502
2503 uint32 Frequency;
2504 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX2;
2505 if (0U == ((IP_MC_CGM_4->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT))
2506 {
2507 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2508 }
2509 else
2510 {
2511 Frequency = Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency();
2512 }
2513 Frequency /= (((IP_MC_CGM_4->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2514 return Frequency;
2515 }
2516
2517 /* Return CLKOUT3_CLK frequency */
Clock_Ip_Get_CLKOUT3_CLK_Frequency(void)2518 static uint32 Clock_Ip_Get_CLKOUT3_CLK_Frequency(void) {
2519
2520 uint32 Frequency;
2521 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX3;
2522 if (0U == ((IP_MC_CGM_5->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT))
2523 {
2524 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2525 }
2526 else
2527 {
2528 Frequency = Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency();
2529 }
2530 Frequency /= (((IP_MC_CGM_5->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2531 return Frequency;
2532 }
2533
2534 /* Return CLKOUT4_CLK frequency */
Clock_Ip_Get_CLKOUT4_CLK_Frequency(void)2535 static uint32 Clock_Ip_Get_CLKOUT4_CLK_Frequency(void) {
2536
2537 uint32 Frequency;
2538 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX4;
2539 if (0U == ((IP_MC_CGM_3->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT))
2540 {
2541 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2542 }
2543 else
2544 {
2545 Frequency = Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency();
2546 }
2547 Frequency /= (((IP_MC_CGM_3->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2548 return Frequency;
2549 }
2550
2551 /* Return EDMA_CLK frequency */
Clock_Ip_Get_CE_EDMA_CLK_Frequency(void)2552 static uint32 Clock_Ip_Get_CE_EDMA_CLK_Frequency(void) {
2553
2554 uint32 Frequency;
2555 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2556 Frequency = Frequency >> 1U;
2557 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->EDMACEPCTL & GPR3_PCTL_EDMACEPCTL_PCTL_MASK) >> GPR3_PCTL_EDMACEPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2558 return Frequency;
2559 }
2560
2561 /* Return EDMA0_CLK frequency */
Clock_Ip_Get_EDMA0_CLK_Frequency(void)2562 static uint32 Clock_Ip_Get_EDMA0_CLK_Frequency(void) {
2563
2564 uint32 Frequency;
2565 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2566 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->EDMA0PCTL & GPR0_PCTL_EDMA0PCTL_PCTL_0_MASK) >> GPR0_PCTL_EDMA0PCTL_PCTL_0_SHIFT)]; /* Apply peripheral clock gate */
2567 return Frequency;
2568 }
2569
2570 /* Return EDMA1_CLK frequency */
Clock_Ip_Get_EDMA1_CLK_Frequency(void)2571 static uint32 Clock_Ip_Get_EDMA1_CLK_Frequency(void) {
2572
2573 uint32 Frequency;
2574 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2575 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->EDMA1PCTL & GPR1_PCTL_EDMA1PCTL_PCTL_0_MASK) >> GPR1_PCTL_EDMA1PCTL_PCTL_0_SHIFT)]; /* Apply peripheral clock gate */
2576 return Frequency;
2577 }
2578
2579 /* Return EDMA3_CLK frequency */
Clock_Ip_Get_EDMA3_CLK_Frequency(void)2580 static uint32 Clock_Ip_Get_EDMA3_CLK_Frequency(void) {
2581
2582 uint32 Frequency;
2583 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2584 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->EDMA3PCTL & GPR3_PCTL_EDMA3PCTL_PCTL_MASK) >> GPR3_PCTL_EDMA3PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2585 return Frequency;
2586 }
2587
2588 /* Return EDMA4_CLK frequency */
Clock_Ip_Get_EDMA4_CLK_Frequency(void)2589 static uint32 Clock_Ip_Get_EDMA4_CLK_Frequency(void) {
2590
2591 uint32 Frequency;
2592 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2593 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_0_MASK) >> GPR4_PCTL_EDMA4PCTL_PCTL_0_SHIFT)]; /* Apply peripheral clock gate */
2594 return Frequency;
2595 }
2596
2597 /* Return EDMA5_CLK frequency */
Clock_Ip_Get_EDMA5_CLK_Frequency(void)2598 static uint32 Clock_Ip_Get_EDMA5_CLK_Frequency(void) {
2599
2600 uint32 Frequency;
2601 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2602 Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2603 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_0_MASK) >> GPR5_PCTL_EDMA5PCTL_PCTL_0_SHIFT)]; /* Apply peripheral clock gate */
2604 return Frequency;
2605 }
2606
2607 /* Return ETH0_TX_MII_CLK frequency */
Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency(void)2608 static uint32 Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency(void) {
2609
2610 uint32 Frequency;
2611 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
2612 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> MC_CGM_MUX_6_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2613 Frequency /= (((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2614 return Frequency;
2615 }
2616
2617 /* Return ENET0_CLK frequency */
Clock_Ip_Get_ENET0_CLK_Frequency(void)2618 static uint32 Clock_Ip_Get_ENET0_CLK_Frequency(void) {
2619
2620 uint32 Frequency;
2621 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
2622 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->ENET0PCTL & GPR1_PCTL_ENET0PCTL_PCTL_MASK) >> GPR1_PCTL_ENET0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2623 Frequency /= (((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2624 return Frequency;
2625 }
2626
2627 /* Return P3_CAN_PE_CLK frequency */
Clock_Ip_Get_P3_CAN_PE_CLK_Frequency(void)2628 static uint32 Clock_Ip_Get_P3_CAN_PE_CLK_Frequency(void) {
2629
2630 uint32 Frequency;
2631 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2632 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DE_MASK) >> MC_CGM_MUX_3_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2633 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2634 return Frequency;
2635 }
2636
2637 /* Return FLEXCAN0_CLK frequency */
Clock_Ip_Get_FLEXCAN0_CLK_Frequency(void)2638 static uint32 Clock_Ip_Get_FLEXCAN0_CLK_Frequency(void) {
2639
2640 uint32 Frequency;
2641 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2642 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN0PCTL & GPR3_PCTL_CAN0PCTL_PCTL_MASK) >> GPR3_PCTL_CAN0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2643 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2644 return Frequency;
2645 }
2646
2647 /* Return FLEXCAN1_CLK frequency */
Clock_Ip_Get_FLEXCAN1_CLK_Frequency(void)2648 static uint32 Clock_Ip_Get_FLEXCAN1_CLK_Frequency(void) {
2649
2650 uint32 Frequency;
2651 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2652 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN1PCTL & GPR3_PCTL_CAN1PCTL_PCTL_MASK) >> GPR3_PCTL_CAN1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2653 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2654 return Frequency;
2655 }
2656
2657 /* Return FLEXCAN2_CLK frequency */
Clock_Ip_Get_FLEXCAN2_CLK_Frequency(void)2658 static uint32 Clock_Ip_Get_FLEXCAN2_CLK_Frequency(void) {
2659
2660 uint32 Frequency;
2661 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2662 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN2PCTL & GPR3_PCTL_CAN2PCTL_PCTL_MASK) >> GPR3_PCTL_CAN2PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2663 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2664 return Frequency;
2665 }
2666
2667 /* Return FLEXCAN3_CLK frequency */
Clock_Ip_Get_FLEXCAN3_CLK_Frequency(void)2668 static uint32 Clock_Ip_Get_FLEXCAN3_CLK_Frequency(void) {
2669
2670 uint32 Frequency;
2671 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2672 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN3PCTL & GPR3_PCTL_CAN3PCTL_PCTL_MASK) >> GPR3_PCTL_CAN3PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2673 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2674 return Frequency;
2675 }
2676
2677 /* Return FLEXCAN4_CLK frequency */
Clock_Ip_Get_FLEXCAN4_CLK_Frequency(void)2678 static uint32 Clock_Ip_Get_FLEXCAN4_CLK_Frequency(void) {
2679
2680 uint32 Frequency;
2681 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2682 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN4PCTL & GPR3_PCTL_CAN4PCTL_PCTL_MASK) >> GPR3_PCTL_CAN4PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2683 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2684 return Frequency;
2685 }
2686
2687 /* Return FLEXCAN5_CLK frequency */
Clock_Ip_Get_FLEXCAN5_CLK_Frequency(void)2688 static uint32 Clock_Ip_Get_FLEXCAN5_CLK_Frequency(void) {
2689
2690 uint32 Frequency;
2691 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2692 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN5PCTL & GPR3_PCTL_CAN5PCTL_PCTL_MASK) >> GPR3_PCTL_CAN5PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2693 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2694 return Frequency;
2695 }
2696
2697 /* Return FLEXCAN6_CLK frequency */
Clock_Ip_Get_FLEXCAN6_CLK_Frequency(void)2698 static uint32 Clock_Ip_Get_FLEXCAN6_CLK_Frequency(void) {
2699
2700 uint32 Frequency;
2701 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2702 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN6PCTL & GPR3_PCTL_CAN6PCTL_PCTL_MASK) >> GPR3_PCTL_CAN6PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2703 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2704 return Frequency;
2705 }
2706
2707 /* Return FLEXCAN7_CLK frequency */
Clock_Ip_Get_FLEXCAN7_CLK_Frequency(void)2708 static uint32 Clock_Ip_Get_FLEXCAN7_CLK_Frequency(void) {
2709
2710 uint32 Frequency;
2711 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2712 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN7PCTL & GPR3_PCTL_CAN7PCTL_PCTL_MASK) >> GPR3_PCTL_CAN7PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2713 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2714 return Frequency;
2715 }
2716
2717 /* Return FLEXCAN8_CLK frequency */
Clock_Ip_Get_FLEXCAN8_CLK_Frequency(void)2718 static uint32 Clock_Ip_Get_FLEXCAN8_CLK_Frequency(void) {
2719
2720 uint32 Frequency;
2721 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2722 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN8PCTL & GPR3_PCTL_CAN8PCTL_PCTL_MASK) >> GPR3_PCTL_CAN8PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2723 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2724 return Frequency;
2725 }
2726
2727 /* Return FLEXCAN9_CLK frequency */
Clock_Ip_Get_FLEXCAN9_CLK_Frequency(void)2728 static uint32 Clock_Ip_Get_FLEXCAN9_CLK_Frequency(void) {
2729
2730 uint32 Frequency;
2731 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2732 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN9PCTL & GPR3_PCTL_CAN9PCTL_PCTL_MASK) >> GPR3_PCTL_CAN9PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2733 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2734 return Frequency;
2735 }
2736
2737 /* Return FLEXCAN10_CLK frequency */
Clock_Ip_Get_FLEXCAN10_CLK_Frequency(void)2738 static uint32 Clock_Ip_Get_FLEXCAN10_CLK_Frequency(void) {
2739
2740 uint32 Frequency;
2741 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2742 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN10PCTL & GPR3_PCTL_CAN10PCTL_PCTL_MASK) >> GPR3_PCTL_CAN10PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2743 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2744 return Frequency;
2745 }
2746
2747 /* Return FLEXCAN11_CLK frequency */
Clock_Ip_Get_FLEXCAN11_CLK_Frequency(void)2748 static uint32 Clock_Ip_Get_FLEXCAN11_CLK_Frequency(void) {
2749
2750 uint32 Frequency;
2751 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2752 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN11PCTL & GPR3_PCTL_CAN11PCTL_PCTL_MASK) >> GPR3_PCTL_CAN11PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2753 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2754 return Frequency;
2755 }
2756
2757 /* Return FLEXCAN12_CLK frequency */
Clock_Ip_Get_FLEXCAN12_CLK_Frequency(void)2758 static uint32 Clock_Ip_Get_FLEXCAN12_CLK_Frequency(void) {
2759
2760 uint32 Frequency;
2761 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2762 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN12PCTL & GPR3_PCTL_CAN12PCTL_PCTL_MASK) >> GPR3_PCTL_CAN12PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2763 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2764 return Frequency;
2765 }
2766
2767 /* Return FLEXCAN13_CLK frequency */
Clock_Ip_Get_FLEXCAN13_CLK_Frequency(void)2768 static uint32 Clock_Ip_Get_FLEXCAN13_CLK_Frequency(void) {
2769
2770 uint32 Frequency;
2771 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2772 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN13PCTL & GPR3_PCTL_CAN13PCTL_PCTL_MASK) >> GPR3_PCTL_CAN13PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2773 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2774 return Frequency;
2775 }
2776
2777 /* Return FLEXCAN14_CLK frequency */
Clock_Ip_Get_FLEXCAN14_CLK_Frequency(void)2778 static uint32 Clock_Ip_Get_FLEXCAN14_CLK_Frequency(void) {
2779
2780 uint32 Frequency;
2781 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2782 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN14PCTL & GPR3_PCTL_CAN14PCTL_PCTL_MASK) >> GPR3_PCTL_CAN14PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2783 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2784 return Frequency;
2785 }
2786
2787 /* Return FLEXCAN15_CLK frequency */
Clock_Ip_Get_FLEXCAN15_CLK_Frequency(void)2788 static uint32 Clock_Ip_Get_FLEXCAN15_CLK_Frequency(void) {
2789
2790 uint32 Frequency;
2791 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2792 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN15PCTL & GPR3_PCTL_CAN15PCTL_PCTL_MASK) >> GPR3_PCTL_CAN15PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2793 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2794 return Frequency;
2795 }
2796
2797 /* Return FLEXCAN16_CLK frequency */
Clock_Ip_Get_FLEXCAN16_CLK_Frequency(void)2798 static uint32 Clock_Ip_Get_FLEXCAN16_CLK_Frequency(void) {
2799
2800 uint32 Frequency;
2801 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2802 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN16PCTL & GPR3_PCTL_CAN16PCTL_PCTL_MASK) >> GPR3_PCTL_CAN16PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2803 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2804 return Frequency;
2805 }
2806
2807 /* Return FLEXCAN17_CLK frequency */
Clock_Ip_Get_FLEXCAN17_CLK_Frequency(void)2808 static uint32 Clock_Ip_Get_FLEXCAN17_CLK_Frequency(void) {
2809
2810 uint32 Frequency;
2811 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2812 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN17PCTL & GPR3_PCTL_CAN17PCTL_PCTL_MASK) >> GPR3_PCTL_CAN17PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2813 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2814 return Frequency;
2815 }
2816
2817 /* Return FLEXCAN18_CLK frequency */
Clock_Ip_Get_FLEXCAN18_CLK_Frequency(void)2818 static uint32 Clock_Ip_Get_FLEXCAN18_CLK_Frequency(void) {
2819
2820 uint32 Frequency;
2821 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2822 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN18PCTL & GPR3_PCTL_CAN18PCTL_PCTL_MASK) >> GPR3_PCTL_CAN18PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2823 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2824 return Frequency;
2825 }
2826
2827 /* Return FLEXCAN19_CLK frequency */
Clock_Ip_Get_FLEXCAN19_CLK_Frequency(void)2828 static uint32 Clock_Ip_Get_FLEXCAN19_CLK_Frequency(void) {
2829
2830 uint32 Frequency;
2831 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2832 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN19PCTL & GPR3_PCTL_CAN19PCTL_PCTL_MASK) >> GPR3_PCTL_CAN19PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2833 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2834 return Frequency;
2835 }
2836
2837 /* Return FLEXCAN20_CLK frequency */
Clock_Ip_Get_FLEXCAN20_CLK_Frequency(void)2838 static uint32 Clock_Ip_Get_FLEXCAN20_CLK_Frequency(void) {
2839
2840 uint32 Frequency;
2841 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2842 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN20PCTL & GPR3_PCTL_CAN20PCTL_PCTL_MASK) >> GPR3_PCTL_CAN20PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2843 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2844 return Frequency;
2845 }
2846
2847 /* Return FLEXCAN21_CLK frequency */
Clock_Ip_Get_FLEXCAN21_CLK_Frequency(void)2848 static uint32 Clock_Ip_Get_FLEXCAN21_CLK_Frequency(void) {
2849
2850 uint32 Frequency;
2851 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2852 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN21PCTL & GPR3_PCTL_CAN21PCTL_PCTL_MASK) >> GPR3_PCTL_CAN21PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2853 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2854 return Frequency;
2855 }
2856
2857 /* Return FLEXCAN22_CLK frequency */
Clock_Ip_Get_FLEXCAN22_CLK_Frequency(void)2858 static uint32 Clock_Ip_Get_FLEXCAN22_CLK_Frequency(void) {
2859
2860 uint32 Frequency;
2861 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2862 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN22PCTL & GPR3_PCTL_CAN22PCTL_PCTL_MASK) >> GPR3_PCTL_CAN22PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2863 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2864 return Frequency;
2865 }
2866
2867 /* Return FLEXCAN23_CLK frequency */
Clock_Ip_Get_FLEXCAN23_CLK_Frequency(void)2868 static uint32 Clock_Ip_Get_FLEXCAN23_CLK_Frequency(void) {
2869
2870 uint32 Frequency;
2871 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2872 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN23PCTL & GPR3_PCTL_CAN23PCTL_PCTL_MASK) >> GPR3_PCTL_CAN23PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2873 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2874 return Frequency;
2875 }
2876
2877 /* Return IIIC0_CLK frequency */
Clock_Ip_Get_IIIC0_CLK_Frequency(void)2878 static uint32 Clock_Ip_Get_IIIC0_CLK_Frequency(void) {
2879
2880 uint32 Frequency;
2881 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2882 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->I3C0PCTL & GPR0_PCTL_I3C0PCTL_PCTL_MASK) >> GPR0_PCTL_I3C0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2883 return Frequency;
2884 }
2885
2886 /* Return IIIC1_CLK frequency */
Clock_Ip_Get_IIIC1_CLK_Frequency(void)2887 static uint32 Clock_Ip_Get_IIIC1_CLK_Frequency(void) {
2888
2889 uint32 Frequency;
2890 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2891 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->I3C1PCTL & GPR1_PCTL_I3C1PCTL_PCTL_MASK) >> GPR1_PCTL_I3C1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2892 return Frequency;
2893 }
2894
2895 /* Return IIIC2_CLK frequency */
Clock_Ip_Get_IIIC2_CLK_Frequency(void)2896 static uint32 Clock_Ip_Get_IIIC2_CLK_Frequency(void) {
2897
2898 uint32 Frequency;
2899 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2900 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->I3C2PCTL & GPR4_PCTL_I3C2PCTL_PCTL_MASK) >> GPR4_PCTL_I3C2PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2901 return Frequency;
2902 }
2903
2904
2905 /* Return P4_LIN_BAUD_CLK frequency */
Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency(void)2906 static uint32 Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency(void) {
2907
2908 uint32 Frequency;
2909 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
2910 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC_CGM_MUX_8_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2911 Frequency /= (((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2912 return Frequency;
2913 }
2914
2915 /* Return LIN6_CLK frequency */
Clock_Ip_Get_LIN6_CLK_Frequency(void)2916 static uint32 Clock_Ip_Get_LIN6_CLK_Frequency(void) {
2917
2918 uint32 Frequency;
2919 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
2920 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->LIN6PCTL & GPR4_PCTL_LIN6PCTL_PCTL_MASK) >> GPR4_PCTL_LIN6PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2921 Frequency /= (((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2922 return Frequency;
2923 }
2924
2925 /* Return LIN7_CLK frequency */
Clock_Ip_Get_LIN7_CLK_Frequency(void)2926 static uint32 Clock_Ip_Get_LIN7_CLK_Frequency(void) {
2927
2928 uint32 Frequency;
2929 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
2930 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->LIN7PCTL & GPR4_PCTL_LIN7PCTL_PCTL_MASK) >> GPR4_PCTL_LIN7PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2931 Frequency /= (((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2932 return Frequency;
2933 }
2934
2935 /* Return LIN8_CLK frequency */
Clock_Ip_Get_LIN8_CLK_Frequency(void)2936 static uint32 Clock_Ip_Get_LIN8_CLK_Frequency(void) {
2937
2938 uint32 Frequency;
2939 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
2940 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->LIN8PCTL & GPR4_PCTL_LIN8PCTL_PCTL_MASK) >> GPR4_PCTL_LIN8PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2941 Frequency /= (((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2942 return Frequency;
2943 }
2944
2945 /* Return P0_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_P0_CLKOUT_SRC_CLK_Frequency(void)2946 static uint32 Clock_Ip_Get_P0_CLKOUT_SRC_CLK_Frequency(void) {
2947
2948 return Clock_Ip_apfFreqTableCLKOUT0SEL[((IP_GPR0->CLKOUT0SEL & GPR0_CLKOUT0SEL_MUXSEL_MASK) >> GPR0_CLKOUT0SEL_MUXSEL_SHIFT)]();/* Selector value */
2949 }
2950
2951 /* Return P0_CTU_PER_CLK frequency */
Clock_Ip_Get_P0_CTU_PER_CLK_Frequency(void)2952 static uint32 Clock_Ip_Get_P0_CTU_PER_CLK_Frequency(void) {
2953
2954 uint32 Frequency;
2955 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
2956 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> MC_CGM_MUX_9_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2957 Frequency /= (((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2958 return Frequency;
2959 }
2960
2961 /* Return P0_DSPI_MSC_CLK frequency */
Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency(void)2962 static uint32 Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency(void) {
2963
2964 uint32 Frequency;
2965 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
2966 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> MC_CGM_MUX_7_DC_1_DE_SHIFT)]; /* Divider enable/disable */
2967 Frequency /= (((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DIV_MASK) >> MC_CGM_MUX_7_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
2968 return Frequency;
2969 }
2970
2971 /* Return P0_EMIOS_LCU_CLK frequency */
Clock_Ip_Get_P0_EMIOS_LCU_CLK_Frequency(void)2972 static uint32 Clock_Ip_Get_P0_EMIOS_LCU_CLK_Frequency(void) {
2973
2974 uint32 Frequency;
2975 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
2976 return Frequency;
2977 }
2978
2979 /* Return P0_GTM_CLK frequency */
Clock_Ip_Get_P0_GTM_CLK_Frequency(void)2980 static uint32 Clock_Ip_Get_P0_GTM_CLK_Frequency(void) {
2981
2982 uint32 Frequency;
2983 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
2984 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2985 Frequency /= (((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2986 return Frequency;
2987 }
2988
2989 /* Return P0_GTM_NOC_CLK frequency */
Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency(void)2990 static uint32 Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency(void) {
2991
2992 uint32 Frequency;
2993 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
2994 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2995 Frequency /= (((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2996 return Frequency;
2997 }
2998
2999 /* Return P0_GTM_TS_CLK frequency */
Clock_Ip_Get_P0_GTM_TS_CLK_Frequency(void)3000 static uint32 Clock_Ip_Get_P0_GTM_TS_CLK_Frequency(void) {
3001
3002 uint32 Frequency;
3003 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3004 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3005 Frequency /= ((((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U) * 5U); /* Apply divider value */
3006 return Frequency;
3007 }
3008
3009 /* Return P0_LIN_CLK frequency */
Clock_Ip_Get_P0_LIN_CLK_Frequency(void)3010 static uint32 Clock_Ip_Get_P0_LIN_CLK_Frequency(void) {
3011
3012 uint32 Frequency;
3013 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
3014 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3015 Frequency /= ((((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3016 return Frequency;
3017 }
3018
3019
3020 /* Return P0_PSI5_125K_CLK frequency */
Clock_Ip_Get_P0_PSI5_125K_CLK_Frequency(void)3021 static uint32 Clock_Ip_Get_P0_PSI5_125K_CLK_Frequency(void) {
3022
3023 uint32 Frequency;
3024 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3025 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DE_MASK) >> MC_CGM_MUX_2_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3026 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DIV_MASK) >> MC_CGM_MUX_2_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3027 return Frequency;
3028 }
3029
3030 /* Return P0_PSI5_189K_CLK frequency */
Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency(void)3031 static uint32 Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency(void) {
3032
3033 uint32 Frequency;
3034 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3035 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DE_MASK) >> MC_CGM_MUX_2_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3036 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_MASK) >> MC_CGM_MUX_2_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3037 return Frequency;
3038 }
3039
3040 /* Return P0_PSI5_S_BAUD_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency(void)3041 static uint32 Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency(void) {
3042
3043 uint32 Frequency;
3044 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3045 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> MC_CGM_MUX_2_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3046 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DIV_MASK) >> MC_CGM_MUX_2_DC_5_DIV_SHIFT) + 1U); /* Apply divider value */
3047 return Frequency;
3048 }
3049
3050 /* Return P0_PSI5_S_CORE_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency(void)3051 static uint32 Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency(void) {
3052
3053 uint32 Frequency;
3054 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3055 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> MC_CGM_MUX_2_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3056 Frequency /= ((((IP_MC_CGM_0->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DIV_MASK) >> MC_CGM_MUX_2_DC_5_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3057 return Frequency;
3058 }
3059
3060 /* Return P0_PSI5_S_TRIG1_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_TRIG1_CLK_Frequency(void)3061 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG1_CLK_Frequency(void) {
3062
3063 uint32 Frequency;
3064 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3065 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3066 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_1 & MC_CGM_MUX_3_DC_1_DE_MASK) >> MC_CGM_MUX_3_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3067 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_1 & MC_CGM_MUX_3_DC_1_DIV_MASK) >> MC_CGM_MUX_3_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3068 return Frequency;
3069 }
3070
3071 /* Return P0_PSI5_S_TRIG2_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_TRIG2_CLK_Frequency(void)3072 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG2_CLK_Frequency(void) {
3073
3074 uint32 Frequency;
3075 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3076 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3077 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_2 & MC_CGM_MUX_3_DC_2_DE_MASK) >> MC_CGM_MUX_3_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3078 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_2 & MC_CGM_MUX_3_DC_2_DIV_MASK) >> MC_CGM_MUX_3_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3079 return Frequency;
3080 }
3081
3082 /* Return P0_PSI5_S_TRIG3_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_TRIG3_CLK_Frequency(void)3083 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG3_CLK_Frequency(void) {
3084
3085 uint32 Frequency;
3086 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3087 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3088 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DE_MASK) >> MC_CGM_MUX_3_DC_3_DE_SHIFT)]; /* Divider enable/disable */
3089 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DIV_MASK) >> MC_CGM_MUX_3_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
3090 return Frequency;
3091 }
3092
3093 /* Return P0_PSI5_S_UART_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency(void)3094 static uint32 Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency(void) {
3095
3096 uint32 Frequency;
3097 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3098 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DE_MASK) >> MC_CGM_MUX_2_DC_4_DE_SHIFT)]; /* Divider enable/disable */
3099 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DIV_MASK) >> MC_CGM_MUX_2_DC_4_DIV_SHIFT) + 1U); /* Apply divider value */
3100 return Frequency;
3101 }
3102
3103 /* Return P0_PSI5_S_WDOG0_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_WDOG0_CLK_Frequency(void)3104 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG0_CLK_Frequency(void) {
3105
3106 uint32 Frequency;
3107 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3108 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3109 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_4 & MC_CGM_MUX_3_DC_4_DE_MASK) >> MC_CGM_MUX_3_DC_4_DE_SHIFT)]; /* Divider enable/disable */
3110 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_4 & MC_CGM_MUX_3_DC_4_DIV_MASK) >> MC_CGM_MUX_3_DC_4_DIV_SHIFT) + 1U); /* Apply divider value */
3111 return Frequency;
3112 }
3113
3114 /* Return P0_PSI5_S_WDOG1_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_WDOG1_CLK_Frequency(void)3115 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG1_CLK_Frequency(void) {
3116
3117 uint32 Frequency;
3118 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3119 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3120 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_5 & MC_CGM_MUX_3_DC_5_DE_MASK) >> MC_CGM_MUX_3_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3121 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_5 & MC_CGM_MUX_3_DC_5_DIV_MASK) >> MC_CGM_MUX_3_DC_5_DIV_SHIFT) + 1U); /* Apply divider value */
3122 return Frequency;
3123 }
3124
3125 /* Return P0_PSI5_S_WDOG2_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_WDOG2_CLK_Frequency(void)3126 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG2_CLK_Frequency(void) {
3127
3128 uint32 Frequency;
3129 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3130 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3131 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_6 & MC_CGM_MUX_3_DC_6_DE_MASK) >> MC_CGM_MUX_3_DC_6_DE_SHIFT)]; /* Divider enable/disable */
3132 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_6 & MC_CGM_MUX_3_DC_6_DIV_MASK) >> MC_CGM_MUX_3_DC_6_DIV_SHIFT) + 1U); /* Apply divider value */
3133 return Frequency;
3134 }
3135
3136 /* Return P0_PSI5_S_WDOG3_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_WDOG3_CLK_Frequency(void)3137 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG3_CLK_Frequency(void) {
3138
3139 uint32 Frequency;
3140 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3141 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3142 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_7 & MC_CGM_MUX_3_DC_7_DE_MASK) >> MC_CGM_MUX_3_DC_7_DE_SHIFT)]; /* Divider enable/disable */
3143 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_7 & MC_CGM_MUX_3_DC_7_DIV_MASK) >> MC_CGM_MUX_3_DC_7_DIV_SHIFT) + 1U); /* Apply divider value */
3144 return Frequency;
3145 }
3146
3147 /* Return P0_REG_INTF_2X_CLK frequency */
Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency(void)3148 static uint32 Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency(void) {
3149
3150 uint32 Frequency;
3151 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3152 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DE_MASK) >> MC_CGM_MUX_1_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3153 Frequency /= (((IP_MC_CGM_0->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DIV_MASK) >> MC_CGM_MUX_1_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3154 return Frequency;
3155 }
3156
3157 /* Return P1_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_P1_CLKOUT_SRC_CLK_Frequency(void)3158 static uint32 Clock_Ip_Get_P1_CLKOUT_SRC_CLK_Frequency(void) {
3159
3160 return Clock_Ip_apfFreqTableCLKOUT1SEL[((IP_GPR1->CLKOUT1SEL & GPR1_CLKOUT1SEL_MUXSEL_MASK) >> GPR1_CLKOUT1SEL_MUXSEL_SHIFT)]();/* Selector value */
3161 }
3162
3163
3164 /* Return P1_DSPI60_CLK frequency */
Clock_Ip_Get_P1_DSPI60_CLK_Frequency(void)3165 static uint32 Clock_Ip_Get_P1_DSPI60_CLK_Frequency(void) {
3166
3167 uint32 Frequency;
3168 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3169 return Frequency;
3170 }
3171
3172 /* Return ETH_TS_CLK frequency */
Clock_Ip_Get_ETH_TS_CLK_Frequency(void)3173 static uint32 Clock_Ip_Get_ETH_TS_CLK_Frequency(void) {
3174
3175 uint32 Frequency;
3176 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3177 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> MC_CGM_MUX_5_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3178 Frequency /= (((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3179 return Frequency;
3180 }
3181
3182 /* Return ETH_TS_DIV4_CLK frequency */
Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency(void)3183 static uint32 Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency(void) {
3184
3185 uint32 Frequency;
3186 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3187 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> MC_CGM_MUX_5_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3188 Frequency /= ((((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SHIFT) + 1U) * 4U); /* Apply divider value */
3189 return Frequency;
3190 }
3191
3192 /* Return ETH0_REF_RMII_CLK frequency */
Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency(void)3193 static uint32 Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency(void) {
3194
3195 uint32 Frequency;
3196 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3197 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_7_DC_2 & MC_CGM_MUX_7_DC_2_DE_MASK) >> MC_CGM_MUX_7_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3198 Frequency /= (((IP_MC_CGM_1->MUX_7_DC_2 & MC_CGM_MUX_7_DC_2_DIV_MASK) >> MC_CGM_MUX_7_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3199 return Frequency;
3200 }
3201
3202 /* Return ETH0_RX_MII_CLK frequency */
Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency(void)3203 static uint32 Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency(void) {
3204
3205 uint32 Frequency;
3206 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3207 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3208 Frequency /= (((IP_MC_CGM_1->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3209 return Frequency;
3210 }
3211
3212 /* Return ETH0_RX_RGMII_CLK frequency */
Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency(void)3213 static uint32 Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency(void) {
3214
3215 uint32 Frequency;
3216 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3217 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> MC_CGM_MUX_7_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3218 Frequency /= (((IP_MC_CGM_1->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DIV_MASK) >> MC_CGM_MUX_7_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3219 return Frequency;
3220 }
3221
3222 /* Return ETH0_TX_RGMII_CLK frequency */
Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency(void)3223 static uint32 Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency(void) {
3224
3225 uint32 Frequency;
3226 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
3227 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_6_DC_1 & MC_CGM_MUX_6_DC_1_DE_MASK) >> MC_CGM_MUX_6_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3228 Frequency /= (((IP_MC_CGM_1->MUX_6_DC_1 & MC_CGM_MUX_6_DC_1_DIV_MASK) >> MC_CGM_MUX_6_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3229 return Frequency;
3230 }
3231
3232 /* Return ETH0_TX_RGMII_LPBK_CLK frequency */
Clock_Ip_Get_ETH0_TX_RGMII_LPBK_CLK_Frequency(void)3233 static uint32 Clock_Ip_Get_ETH0_TX_RGMII_LPBK_CLK_Frequency(void) {
3234
3235 uint32 Frequency;
3236 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
3237 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_6_DC_1 & MC_CGM_MUX_6_DC_1_DE_MASK) >> MC_CGM_MUX_6_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3238 Frequency /= (((IP_MC_CGM_1->MUX_6_DC_1 & MC_CGM_MUX_6_DC_1_DIV_MASK) >> MC_CGM_MUX_6_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3239 return Frequency;
3240 }
3241
3242 /* Return ETH1_REF_RMII_CLK frequency */
Clock_Ip_Get_ETH1_REF_RMII_CLK_Frequency(void)3243 static uint32 Clock_Ip_Get_ETH1_REF_RMII_CLK_Frequency(void) {
3244
3245 uint32 Frequency;
3246 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3247 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_9_DC_2 & MC_CGM_MUX_9_DC_2_DE_MASK) >> MC_CGM_MUX_9_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3248 Frequency /= (((IP_MC_CGM_1->MUX_9_DC_2 & MC_CGM_MUX_9_DC_2_DIV_MASK) >> MC_CGM_MUX_9_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3249 return Frequency;
3250 }
3251
3252 /* Return ETH1_RX_MII_CLK frequency */
Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency(void)3253 static uint32 Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency(void) {
3254
3255 uint32 Frequency;
3256 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3257 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> MC_CGM_MUX_9_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3258 Frequency /= (((IP_MC_CGM_1->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3259 return Frequency;
3260 }
3261
3262 /* Return ETH1_RX_RGMII_CLK frequency */
Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency(void)3263 static uint32 Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency(void) {
3264
3265 uint32 Frequency;
3266 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3267 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> MC_CGM_MUX_9_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3268 Frequency /= (((IP_MC_CGM_1->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3269 return Frequency;
3270 }
3271
3272 /* Return ETH1_TX_MII_CLK frequency */
Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency(void)3273 static uint32 Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency(void) {
3274
3275 uint32 Frequency;
3276 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
3277 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC_CGM_MUX_8_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3278 Frequency /= (((IP_MC_CGM_1->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3279 return Frequency;
3280 }
3281
3282 /* Return ETH1_TX_RGMII_CLK frequency */
Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency(void)3283 static uint32 Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency(void) {
3284
3285 uint32 Frequency;
3286 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
3287 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DE_MASK) >> MC_CGM_MUX_8_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3288 Frequency /= (((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DIV_MASK) >> MC_CGM_MUX_8_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3289 return Frequency;
3290 }
3291
3292 /* Return ETH1_TX_RGMII_LPBK_CLK frequency */
Clock_Ip_Get_ETH1_TX_RGMII_LPBK_CLK_Frequency(void)3293 static uint32 Clock_Ip_Get_ETH1_TX_RGMII_LPBK_CLK_Frequency(void) {
3294
3295 uint32 Frequency;
3296 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
3297 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DE_MASK) >> MC_CGM_MUX_8_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3298 Frequency /= (((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DIV_MASK) >> MC_CGM_MUX_8_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3299 return Frequency;
3300 }
3301
3302 /* Return P1_LFAST1_REF_CLK frequency */
Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency(void)3303 static uint32 Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency(void) {
3304
3305 uint32 Frequency;
3306 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_12_CSS & MC_CGM_MUX_12_CSS_SELSTAT_MASK) >> MC_CGM_MUX_12_CSS_SELSTAT_SHIFT)]();/* Selector value */
3307 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DE_MASK) >> MC_CGM_MUX_12_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3308 Frequency /= (((IP_MC_CGM_1->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DIV_MASK) >> MC_CGM_MUX_12_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3309 return Frequency;
3310 }
3311
3312 /* Return P1_LFAST_DFT_CLK frequency */
Clock_Ip_Get_P1_LFAST_DFT_CLK_Frequency(void)3313 static uint32 Clock_Ip_Get_P1_LFAST_DFT_CLK_Frequency(void) {
3314
3315 uint32 Frequency;
3316 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_13_CSS & MC_CGM_MUX_13_CSS_SELSTAT_MASK) >> MC_CGM_MUX_13_CSS_SELSTAT_SHIFT)]();/* Selector value */
3317 return Frequency;
3318 }
3319
3320 /* Return P1_NETC_AXI_CLK frequency */
Clock_Ip_Get_P1_NETC_AXI_CLK_Frequency(void)3321 static uint32 Clock_Ip_Get_P1_NETC_AXI_CLK_Frequency(void) {
3322
3323 uint32 Frequency;
3324 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_14_CSS & MC_CGM_MUX_14_CSS_SELSTAT_MASK) >> MC_CGM_MUX_14_CSS_SELSTAT_SHIFT)]();/* Selector value */
3325 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_14_DC_0 & MC_CGM_MUX_14_DC_0_DE_MASK) >> MC_CGM_MUX_14_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3326 Frequency /= (((IP_MC_CGM_1->MUX_14_DC_0 & MC_CGM_MUX_14_DC_0_DIV_MASK) >> MC_CGM_MUX_14_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3327 return Frequency;
3328 }
3329
3330 /* Return P1_LIN_CLK frequency */
Clock_Ip_Get_P1_LIN_CLK_Frequency(void)3331 static uint32 Clock_Ip_Get_P1_LIN_CLK_Frequency(void) {
3332
3333 uint32 Frequency;
3334 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
3335 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3336 Frequency /= ((((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3337 return Frequency;
3338 }
3339
3340 /* Return P3_AES_CLK frequency */
Clock_Ip_Get_P3_AES_CLK_Frequency(void)3341 static uint32 Clock_Ip_Get_P3_AES_CLK_Frequency(void) {
3342
3343 uint32 Frequency;
3344 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3345 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_3->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DE_MASK) >> MC_CGM_MUX_2_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3346 Frequency /= (((IP_MC_CGM_3->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DIV_MASK) >> MC_CGM_MUX_2_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3347 return Frequency;
3348 }
3349
3350 /* Return P3_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_P3_CLKOUT_SRC_CLK_Frequency(void)3351 static uint32 Clock_Ip_Get_P3_CLKOUT_SRC_CLK_Frequency(void) {
3352
3353 return Clock_Ip_apfFreqTableCLKOUT4SEL[((IP_GPR3->CLKOUT4SEL & GPR3_CLKOUT4SEL_MUXSEL_MASK) >> GPR3_CLKOUT4SEL_MUXSEL_SHIFT)]();/* Selector value */
3354 }
3355
3356
3357 /* Return P3_DBG_TS_CLK frequency */
Clock_Ip_Get_P3_DBG_TS_CLK_Frequency(void)3358 static uint32 Clock_Ip_Get_P3_DBG_TS_CLK_Frequency(void) {
3359
3360 uint32 Frequency;
3361 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3362 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_3->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3363 Frequency /= (((IP_MC_CGM_3->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3364 return Frequency;
3365 }
3366
3367 /* Return P3_REG_INTF_CLK frequency */
Clock_Ip_Get_P3_REG_INTF_CLK_Frequency(void)3368 static uint32 Clock_Ip_Get_P3_REG_INTF_CLK_Frequency(void) {
3369
3370 uint32 Frequency;
3371 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3372 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_3->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3373 Frequency /= (((IP_MC_CGM_3->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3374 return Frequency;
3375 }
3376
3377 /* Return P4_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_P4_CLKOUT_SRC_CLK_Frequency(void)3378 static uint32 Clock_Ip_Get_P4_CLKOUT_SRC_CLK_Frequency(void) {
3379
3380 return Clock_Ip_apfFreqTableCLKOUT2SEL[((IP_GPR4->CLKOUT2SEL & GPR4_CLKOUT2SEL_MUXSEL_MASK) >> GPR4_CLKOUT2SEL_MUXSEL_SHIFT)]();/* Selector value */
3381 }
3382
3383
3384 /* Return P4_DSPI60_CLK frequency */
Clock_Ip_Get_P4_DSPI60_CLK_Frequency(void)3385 static uint32 Clock_Ip_Get_P4_DSPI60_CLK_Frequency(void) {
3386
3387 uint32 Frequency;
3388 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3389 return Frequency;
3390 }
3391
3392 /* Return P4_EMIOS_LCU_CLK frequency */
Clock_Ip_Get_P4_EMIOS_LCU_CLK_Frequency(void)3393 static uint32 Clock_Ip_Get_P4_EMIOS_LCU_CLK_Frequency(void) {
3394
3395 uint32 Frequency;
3396 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_11_CSS & MC_CGM_MUX_11_CSS_SELSTAT_MASK) >> MC_CGM_MUX_11_CSS_SELSTAT_SHIFT)]();/* Selector value */
3397 return Frequency;
3398 }
3399
3400 /* Return P4_LIN_CLK frequency */
Clock_Ip_Get_P4_LIN_CLK_Frequency(void)3401 static uint32 Clock_Ip_Get_P4_LIN_CLK_Frequency(void) {
3402
3403 uint32 Frequency;
3404 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
3405 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC_CGM_MUX_8_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3406 Frequency /= ((((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3407 return Frequency;
3408 }
3409
3410 /* Return P4_PSI5_125K_CLK frequency */
Clock_Ip_Get_P4_PSI5_125K_CLK_Frequency(void)3411 static uint32 Clock_Ip_Get_P4_PSI5_125K_CLK_Frequency(void) {
3412
3413 uint32 Frequency;
3414 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3415 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DE_MASK) >> MC_CGM_MUX_2_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3416 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DIV_MASK) >> MC_CGM_MUX_2_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3417 return Frequency;
3418 }
3419
3420 /* Return P4_PSI5_189K_CLK frequency */
Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency(void)3421 static uint32 Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency(void) {
3422
3423 uint32 Frequency;
3424 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3425 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DE_MASK) >> MC_CGM_MUX_2_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3426 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_MASK) >> MC_CGM_MUX_2_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3427 return Frequency;
3428 }
3429
3430 /* Return P4_PSI5_S_BAUD_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency(void)3431 static uint32 Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency(void) {
3432
3433 uint32 Frequency;
3434 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3435 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> MC_CGM_MUX_2_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3436 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DIV_MASK) >> MC_CGM_MUX_2_DC_5_DIV_SHIFT) + 1U); /* Apply divider value */
3437 return Frequency;
3438 }
3439
3440 /* Return P4_PSI5_S_CORE_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency(void)3441 static uint32 Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency(void) {
3442
3443 uint32 Frequency;
3444 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3445 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> MC_CGM_MUX_2_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3446 Frequency /= ((((IP_MC_CGM_4->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DIV_MASK) >> MC_CGM_MUX_2_DC_5_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3447 return Frequency;
3448 }
3449
3450 /* Return P4_PSI5_S_TRIG0_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_TRIG0_CLK_Frequency(void)3451 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG0_CLK_Frequency(void) {
3452
3453 uint32 Frequency;
3454 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3455 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3456 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DE_MASK) >> MC_CGM_MUX_3_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3457 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3458 return Frequency;
3459 }
3460
3461 /* Return P4_PSI5_S_TRIG1_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_TRIG1_CLK_Frequency(void)3462 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG1_CLK_Frequency(void) {
3463
3464 uint32 Frequency;
3465 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3466 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3467 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_1 & MC_CGM_MUX_3_DC_1_DE_MASK) >> MC_CGM_MUX_3_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3468 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_1 & MC_CGM_MUX_3_DC_1_DIV_MASK) >> MC_CGM_MUX_3_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3469 return Frequency;
3470 }
3471
3472 /* Return P4_PSI5_S_TRIG2_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_TRIG2_CLK_Frequency(void)3473 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG2_CLK_Frequency(void) {
3474
3475 uint32 Frequency;
3476 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3477 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3478 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_2 & MC_CGM_MUX_3_DC_2_DE_MASK) >> MC_CGM_MUX_3_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3479 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_2 & MC_CGM_MUX_3_DC_2_DIV_MASK) >> MC_CGM_MUX_3_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3480 return Frequency;
3481 }
3482
3483 /* Return P4_PSI5_S_TRIG3_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_TRIG3_CLK_Frequency(void)3484 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG3_CLK_Frequency(void) {
3485
3486 uint32 Frequency;
3487 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3488 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3489 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DE_MASK) >> MC_CGM_MUX_3_DC_3_DE_SHIFT)]; /* Divider enable/disable */
3490 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DIV_MASK) >> MC_CGM_MUX_3_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
3491 return Frequency;
3492 }
3493
3494 /* Return P4_PSI5_S_UART_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency(void)3495 static uint32 Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency(void) {
3496
3497 uint32 Frequency;
3498 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3499 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DE_MASK) >> MC_CGM_MUX_2_DC_4_DE_SHIFT)]; /* Divider enable/disable */
3500 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DIV_MASK) >> MC_CGM_MUX_2_DC_4_DIV_SHIFT) + 1U); /* Apply divider value */
3501 return Frequency;
3502 }
3503
3504 /* Return P4_PSI5_S_WDOG0_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_WDOG0_CLK_Frequency(void)3505 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG0_CLK_Frequency(void) {
3506
3507 uint32 Frequency;
3508 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3509 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3510 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_4 & MC_CGM_MUX_3_DC_4_DE_MASK) >> MC_CGM_MUX_3_DC_4_DE_SHIFT)]; /* Divider enable/disable */
3511 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_4 & MC_CGM_MUX_3_DC_4_DIV_MASK) >> MC_CGM_MUX_3_DC_4_DIV_SHIFT) + 1U); /* Apply divider value */
3512 return Frequency;
3513 }
3514
3515 /* Return P4_PSI5_S_WDOG1_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_WDOG1_CLK_Frequency(void)3516 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG1_CLK_Frequency(void) {
3517
3518 uint32 Frequency;
3519 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3520 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3521 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_5 & MC_CGM_MUX_3_DC_5_DE_MASK) >> MC_CGM_MUX_3_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3522 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_5 & MC_CGM_MUX_3_DC_5_DIV_MASK) >> MC_CGM_MUX_3_DC_5_DIV_SHIFT) + 1U); /* Apply divider value */
3523 return Frequency;
3524 }
3525
3526 /* Return P4_PSI5_S_WDOG2_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_WDOG2_CLK_Frequency(void)3527 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG2_CLK_Frequency(void) {
3528
3529 uint32 Frequency;
3530 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3531 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3532 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_6 & MC_CGM_MUX_3_DC_6_DE_MASK) >> MC_CGM_MUX_3_DC_6_DE_SHIFT)]; /* Divider enable/disable */
3533 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_6 & MC_CGM_MUX_3_DC_6_DIV_MASK) >> MC_CGM_MUX_3_DC_6_DIV_SHIFT) + 1U); /* Apply divider value */
3534 return Frequency;
3535 }
3536
3537 /* Return P4_PSI5_S_WDOG3_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_WDOG3_CLK_Frequency(void)3538 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG3_CLK_Frequency(void) {
3539
3540 uint32 Frequency;
3541 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3542 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3543 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_7 & MC_CGM_MUX_3_DC_7_DE_MASK) >> MC_CGM_MUX_3_DC_7_DE_SHIFT)]; /* Divider enable/disable */
3544 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_7 & MC_CGM_MUX_3_DC_7_DIV_MASK) >> MC_CGM_MUX_3_DC_7_DIV_SHIFT) + 1U); /* Apply divider value */
3545 return Frequency;
3546 }
3547
3548 /* Return P4_QSPI0_2X_CLK frequency */
Clock_Ip_Get_P4_QSPI0_2X_CLK_Frequency(void)3549 static uint32 Clock_Ip_Get_P4_QSPI0_2X_CLK_Frequency(void) {
3550
3551 uint32 Frequency;
3552 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3553 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3554 Frequency /= (((IP_MC_CGM_4->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3555 return Frequency;
3556 }
3557
3558 /* Return P4_QSPI0_1X_CLK frequency */
Clock_Ip_Get_P4_QSPI0_1X_CLK_Frequency(void)3559 static uint32 Clock_Ip_Get_P4_QSPI0_1X_CLK_Frequency(void) {
3560
3561 uint32 Frequency;
3562 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3563 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3564 Frequency /= ((((IP_MC_CGM_4->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3565 return Frequency;
3566 }
3567
3568 /* Return P4_QSPI1_2X_CLK frequency */
Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency(void)3569 static uint32 Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency(void) {
3570
3571 uint32 Frequency;
3572 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3573 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> MC_CGM_MUX_9_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3574 Frequency /= (((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3575 return Frequency;
3576 }
3577
3578 /* Return P4_QSPI1_1X_CLK frequency */
Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency(void)3579 static uint32 Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency(void) {
3580
3581 uint32 Frequency;
3582 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3583 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> MC_CGM_MUX_9_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3584 Frequency /= ((((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3585 return Frequency;
3586 }
3587
3588 /* Return P4_REG_INTF_2X_CLK frequency */
Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency(void)3589 static uint32 Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency(void) {
3590
3591 uint32 Frequency;
3592 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3593 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DE_MASK) >> MC_CGM_MUX_1_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3594 Frequency /= (((IP_MC_CGM_4->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DIV_MASK) >> MC_CGM_MUX_1_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3595 return Frequency;
3596 }
3597
3598 /* Return P4_REG_INTF_CLK frequency */
Clock_Ip_Get_P4_REG_INTF_CLK_Frequency(void)3599 static uint32 Clock_Ip_Get_P4_REG_INTF_CLK_Frequency(void) {
3600
3601 uint32 Frequency;
3602 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3603 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3604 Frequency /= (((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3605 return Frequency;
3606 }
3607
3608 /* Return P4_SDHC_IP_CLK frequency */
Clock_Ip_Get_P4_SDHC_IP_CLK_Frequency(void)3609 static uint32 Clock_Ip_Get_P4_SDHC_IP_CLK_Frequency(void) {
3610
3611 uint32 Frequency;
3612 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_10_CSS & MC_CGM_MUX_10_CSS_SELSTAT_MASK) >> MC_CGM_MUX_10_CSS_SELSTAT_SHIFT)]();/* Selector value */
3613 return Frequency;
3614 }
3615
3616 /* Return P4_SDHC_IP_DIV2_CLK frequency */
Clock_Ip_Get_P4_SDHC_IP_DIV2_CLK_Frequency(void)3617 static uint32 Clock_Ip_Get_P4_SDHC_IP_DIV2_CLK_Frequency(void) {
3618
3619 uint32 Frequency;
3620 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_10_CSS & MC_CGM_MUX_10_CSS_SELSTAT_MASK) >> MC_CGM_MUX_10_CSS_SELSTAT_SHIFT)]();/* Selector value */
3621 Frequency = Frequency >> 1U;
3622 return Frequency;
3623 }
3624 /* Return P5_DIPORT_CLK frequency */
Clock_Ip_Get_P5_DIPORT_CLK_Frequency(void)3625 static uint32 Clock_Ip_Get_P5_DIPORT_CLK_Frequency(void) {
3626
3627 uint32 Frequency;
3628 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3629 return Frequency;
3630 }
3631
3632 /* Return P5_AE_CLK frequency */
Clock_Ip_Get_P5_AE_CLK_Frequency(void)3633 static uint32 Clock_Ip_Get_P5_AE_CLK_Frequency(void) {
3634
3635 uint32 Frequency;
3636 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3637 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> MC_CGM_MUX_5_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3638 Frequency /= (((IP_MC_CGM_5->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3639 return Frequency;
3640 }
3641
3642 /* Return P5_CANXL_PE_CLK frequency */
Clock_Ip_Get_P5_CANXL_PE_CLK_Frequency(void)3643 static uint32 Clock_Ip_Get_P5_CANXL_PE_CLK_Frequency(void) {
3644
3645 uint32 Frequency;
3646 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3647 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_5_DC_1 & MC_CGM_MUX_5_DC_1_DE_MASK) >> MC_CGM_MUX_5_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3648 Frequency /= (((IP_MC_CGM_5->MUX_5_DC_1 & MC_CGM_MUX_5_DC_1_DIV_MASK) >> MC_CGM_MUX_5_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3649 return Frequency;
3650 }
3651 /* Return P5_CANXL_CHI_CLK frequency */
Clock_Ip_Get_P5_CANXL_CHI_CLK_Frequency(void)3652 static uint32 Clock_Ip_Get_P5_CANXL_CHI_CLK_Frequency(void) {
3653
3654 uint32 Frequency;
3655 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3656 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_5_DC_2 & MC_CGM_MUX_5_DC_2_DE_MASK) >> MC_CGM_MUX_5_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3657 Frequency /= (((IP_MC_CGM_5->MUX_5_DC_2 & MC_CGM_MUX_5_DC_2_DIV_MASK) >> MC_CGM_MUX_5_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3658 return Frequency;
3659 }
3660
3661 /* Return P5_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_P5_CLKOUT_SRC_CLK_Frequency(void)3662 static uint32 Clock_Ip_Get_P5_CLKOUT_SRC_CLK_Frequency(void) {
3663
3664 return Clock_Ip_apfFreqTableCLKOUT3SEL[((IP_GPR5->CLKOUT3SEL & GPR5_CLKOUT3SEL_MUXSEL_MASK) >> GPR5_CLKOUT3SEL_MUXSEL_SHIFT)]();/* Selector value */
3665 }
3666
3667
3668 /* Return P5_LIN_CLK frequency */
Clock_Ip_Get_P5_LIN_CLK_Frequency(void)3669 static uint32 Clock_Ip_Get_P5_LIN_CLK_Frequency(void) {
3670
3671 uint32 Frequency;
3672 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3673 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3674 Frequency /= ((((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3675 return Frequency;
3676 }
3677
3678 /* Return P6_REG_INTF_CLK frequency */
Clock_Ip_Get_P6_REG_INTF_CLK_Frequency(void)3679 static uint32 Clock_Ip_Get_P6_REG_INTF_CLK_Frequency(void) {
3680
3681 uint32 Frequency;
3682 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_6->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3683 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_6->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3684 Frequency /= (((IP_MC_CGM_6->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3685 return Frequency;
3686 }
3687
3688 /* Return PIT0_CLK frequency */
Clock_Ip_Get_PIT0_CLK_Frequency(void)3689 static uint32 Clock_Ip_Get_PIT0_CLK_Frequency(void) {
3690
3691 uint32 Frequency;
3692 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3693 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3694 Frequency /= (((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3695 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->EDMA0PCTL & GPR0_PCTL_EDMA0PCTL_PCTL_3_MASK) >> GPR0_PCTL_EDMA0PCTL_PCTL_3_SHIFT)]; /* Apply peripheral clock gate */
3696 return Frequency;
3697 }
3698
3699 /* Return PIT1_CLK frequency */
Clock_Ip_Get_PIT1_CLK_Frequency(void)3700 static uint32 Clock_Ip_Get_PIT1_CLK_Frequency(void) {
3701
3702 uint32 Frequency;
3703 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3704 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3705 Frequency /= (((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3706 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->EDMA1PCTL & GPR1_PCTL_EDMA1PCTL_PCTL_3_MASK) >> GPR1_PCTL_EDMA1PCTL_PCTL_3_SHIFT)]; /* Apply peripheral clock gate */
3707 return Frequency;
3708 }
3709
3710 /* Return PIT4_CLK frequency */
Clock_Ip_Get_PIT4_CLK_Frequency(void)3711 static uint32 Clock_Ip_Get_PIT4_CLK_Frequency(void) {
3712
3713 uint32 Frequency;
3714 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3715 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3716 Frequency /= (((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3717 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_3_MASK) >> GPR4_PCTL_EDMA4PCTL_PCTL_3_SHIFT)]; /* Apply peripheral clock gate */
3718 return Frequency;
3719 }
3720
3721 /* Return PIT5_CLK frequency */
Clock_Ip_Get_PIT5_CLK_Frequency(void)3722 static uint32 Clock_Ip_Get_PIT5_CLK_Frequency(void) {
3723
3724 uint32 Frequency;
3725 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3726 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3727 Frequency /= (((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3728 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_3_MASK) >> GPR5_PCTL_EDMA5PCTL_PCTL_3_SHIFT)]; /* Apply peripheral clock gate */
3729 return Frequency;
3730 }
3731
3732 /* Return P4_PSI5_1US_CLK frequency */
Clock_Ip_Get_P4_PSI5_1US_CLK_Frequency(void)3733 static uint32 Clock_Ip_Get_P4_PSI5_1US_CLK_Frequency(void) {
3734
3735 uint32 Frequency;
3736 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3737 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3738 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3739 return Frequency;
3740 }
3741
3742 /* Return PSI5_1_CLK frequency */
Clock_Ip_Get_PSI5_1_CLK_Frequency(void)3743 static uint32 Clock_Ip_Get_PSI5_1_CLK_Frequency(void) {
3744
3745 uint32 Frequency;
3746 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3747 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->PSI51PCTL & GPR4_PCTL_PSI51PCTL_PCTL_MASK) >> GPR4_PCTL_PSI51PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3748 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3749 return Frequency;
3750 }
3751
3752 /* Return PSI5S_0_CLK frequency */
Clock_Ip_Get_PSI5S_0_CLK_Frequency(void)3753 static uint32 Clock_Ip_Get_PSI5S_0_CLK_Frequency(void) {
3754
3755 uint32 Frequency;
3756 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3757 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->PSI5S0PCTL & GPR0_PCTL_PSI5S0PCTL_PCTL_MASK) >> GPR0_PCTL_PSI5S0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3758 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
3759 return Frequency;
3760 }
3761
3762 /* Return PSI5S_1_CLK frequency */
Clock_Ip_Get_PSI5S_1_CLK_Frequency(void)3763 static uint32 Clock_Ip_Get_PSI5S_1_CLK_Frequency(void) {
3764
3765 uint32 Frequency;
3766 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3767 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->PSI5S1PCTL & GPR4_PCTL_PSI5S1PCTL_PCTL_MASK) >> GPR4_PCTL_PSI5S1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3768 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
3769 return Frequency;
3770 }
3771
3772 /* Return QSPI0_CLK frequency */
Clock_Ip_Get_QSPI0_CLK_Frequency(void)3773 static uint32 Clock_Ip_Get_QSPI0_CLK_Frequency(void) {
3774
3775 uint32 Frequency;
3776 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3777 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->QSPI0PCTL & GPR4_PCTL_QSPI0PCTL_PCTL_MASK) >> GPR4_PCTL_QSPI0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3778 Frequency /= ((((IP_MC_CGM_4->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3779 return Frequency;
3780 }
3781
3782 /* Return QSPI1_CLK frequency */
Clock_Ip_Get_QSPI1_CLK_Frequency(void)3783 static uint32 Clock_Ip_Get_QSPI1_CLK_Frequency(void) {
3784
3785 uint32 Frequency;
3786 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3787 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->QSPI1PCTL & GPR4_PCTL_QSPI1PCTL_PCTL_MASK) >> GPR4_PCTL_QSPI1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3788 Frequency /= ((((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3789 return Frequency;
3790 }
3791
3792 /* Return RTU0_REG_INTF_CLK frequency */
Clock_Ip_Get_RTU0_REG_INTF_CLK_Frequency(void)3793 static uint32 Clock_Ip_Get_RTU0_REG_INTF_CLK_Frequency(void) {
3794
3795 uint32 Frequency;
3796 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_RTU0__MC_CGM->MUX_1_CSS & RTU_MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> RTU_MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3797 Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU0__MC_CGM->MUX_1_DC_0 & RTU_MC_CGM_MUX_1_DC_0_DE_MASK) >> RTU_MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3798 Frequency /= (((IP_RTU0__MC_CGM->MUX_1_DC_0 & RTU_MC_CGM_MUX_1_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3799 return Frequency;
3800 }
3801
3802 /* Return RTU1_REG_INTF_CLK frequency */
Clock_Ip_Get_RTU1_REG_INTF_CLK_Frequency(void)3803 static uint32 Clock_Ip_Get_RTU1_REG_INTF_CLK_Frequency(void) {
3804
3805 uint32 Frequency;
3806 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_RTU1__MC_CGM->MUX_1_CSS & RTU_MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> RTU_MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3807 Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU1__MC_CGM->MUX_1_DC_0 & RTU_MC_CGM_MUX_1_DC_0_DE_MASK) >> RTU_MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3808 Frequency /= (((IP_RTU1__MC_CGM->MUX_1_DC_0 & RTU_MC_CGM_MUX_1_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3809 return Frequency;
3810 }
3811
3812 /* Return RXLUT_CLK frequency */
Clock_Ip_Get_RXLUT_CLK_Frequency(void)3813 static uint32 Clock_Ip_Get_RXLUT_CLK_Frequency(void) {
3814
3815 uint32 Frequency;
3816 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
3817 Frequency = Frequency >> 1U;
3818 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->RXLUTPCTL & GPR3_PCTL_RXLUTPCTL_PCTL_MASK) >> GPR3_PCTL_RXLUTPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3819 return Frequency;
3820 }
3821 /* Return P4_SDHC_CLK frequency */
Clock_Ip_Get_P4_SDHC_CLK_Frequency(void)3822 static uint32 Clock_Ip_Get_P4_SDHC_CLK_Frequency(void) {
3823
3824 uint32 Frequency;
3825 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3826 Frequency /= (((IP_MC_CGM_4->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3827 return Frequency;
3828 }
3829
3830 /* Return SDHC0_CLK frequency */
Clock_Ip_Get_SDHC0_CLK_Frequency(void)3831 static uint32 Clock_Ip_Get_SDHC0_CLK_Frequency(void) {
3832
3833 uint32 Frequency;
3834 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3835 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->SDHCPCTL & GPR4_PCTL_SDHCPCTL_PCTL_MASK) >> GPR4_PCTL_SDHCPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3836 Frequency /= (((IP_MC_CGM_4->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3837 return Frequency;
3838 }
3839
3840 /* Return SINC_CLK frequency */
Clock_Ip_Get_SINC_CLK_Frequency(void)3841 static uint32 Clock_Ip_Get_SINC_CLK_Frequency(void) {
3842
3843 uint32 Frequency;
3844 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3845 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3846 Frequency /= (((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3847 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->SINCPCTL & GPR0_PCTL_SINCPCTL_PCTL_MASK) >> GPR0_PCTL_SINCPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3848 return Frequency;
3849 }
3850
3851 /* Return SIPI0_CLK frequency */
Clock_Ip_Get_SIPI0_CLK_Frequency(void)3852 static uint32 Clock_Ip_Get_SIPI0_CLK_Frequency(void) {
3853
3854 uint32 Frequency;
3855 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
3856 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->SIPI0PCTL & GPR1_PCTL_SIPI0PCTL_PCTL_MASK) >> GPR1_PCTL_SIPI0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3857 return Frequency;
3858 }
3859
3860 /* Return SIPI1_CLK frequency */
Clock_Ip_Get_SIPI1_CLK_Frequency(void)3861 static uint32 Clock_Ip_Get_SIPI1_CLK_Frequency(void) {
3862
3863 uint32 Frequency;
3864 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
3865 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->SIPI1PCTL & GPR1_PCTL_SIPI1PCTL_PCTL_MASK) >> GPR1_PCTL_SIPI1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3866 return Frequency;
3867 }
3868
3869 /* Return SIUL2_0_CLK frequency */
Clock_Ip_Get_SIUL2_0_CLK_Frequency(void)3870 static uint32 Clock_Ip_Get_SIUL2_0_CLK_Frequency(void) {
3871
3872 uint32 Frequency;
3873 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
3874 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->SIUL0PCTL & GPR0_PCTL_SIUL0PCTL_PCTL_MASK) >> GPR0_PCTL_SIUL0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3875 return Frequency;
3876 }
3877
3878 /* Return SIUL2_1_CLK frequency */
Clock_Ip_Get_SIUL2_1_CLK_Frequency(void)3879 static uint32 Clock_Ip_Get_SIUL2_1_CLK_Frequency(void) {
3880
3881 uint32 Frequency;
3882 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();/* Selector value */
3883 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->SIUL1PCTL & GPR1_PCTL_SIUL1PCTL_PCTL_MASK) >> GPR1_PCTL_SIUL1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3884 return Frequency;
3885 }
3886
3887 /* Return SIUL2_4_CLK frequency */
Clock_Ip_Get_SIUL2_4_CLK_Frequency(void)3888 static uint32 Clock_Ip_Get_SIUL2_4_CLK_Frequency(void) {
3889
3890 uint32 Frequency;
3891 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
3892 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->SIUL4PCTL & GPR4_PCTL_SIUL4PCTL_PCTL_MASK) >> GPR4_PCTL_SIUL4PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3893 return Frequency;
3894 }
3895
3896 /* Return SIUL2_5_CLK frequency */
Clock_Ip_Get_SIUL2_5_CLK_Frequency(void)3897 static uint32 Clock_Ip_Get_SIUL2_5_CLK_Frequency(void) {
3898
3899 uint32 Frequency;
3900 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();/* Selector value */
3901 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->SIUL5PCTL & GPR5_PCTL_SIUL5PCTL_PCTL_MASK) >> GPR5_PCTL_SIUL5PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3902 return Frequency;
3903 }
3904
3905
3906 /* Return P4_DSPI_CLK frequency */
Clock_Ip_Get_P4_DSPI_CLK_Frequency(void)3907 static uint32 Clock_Ip_Get_P4_DSPI_CLK_Frequency(void) {
3908
3909 uint32 Frequency;
3910 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
3911 return Frequency;
3912 }
3913
3914 /* Return SPI5_CLK frequency */
Clock_Ip_Get_SPI5_CLK_Frequency(void)3915 static uint32 Clock_Ip_Get_SPI5_CLK_Frequency(void) {
3916
3917 uint32 Frequency;
3918 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3919 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->DSPI5PCTL & GPR4_PCTL_DSPI5PCTL_PCTL_MASK) >> GPR4_PCTL_DSPI5PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3920 return Frequency;
3921 }
3922
3923 /* Return SPI6_CLK frequency */
Clock_Ip_Get_SPI6_CLK_Frequency(void)3924 static uint32 Clock_Ip_Get_SPI6_CLK_Frequency(void) {
3925
3926 uint32 Frequency;
3927 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3928 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->DSPI6PCTL & GPR4_PCTL_DSPI6PCTL_PCTL_MASK) >> GPR4_PCTL_DSPI6PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3929 return Frequency;
3930 }
3931
3932
3933 /* Return SPI7_CLK frequency */
Clock_Ip_Get_SPI7_CLK_Frequency(void)3934 static uint32 Clock_Ip_Get_SPI7_CLK_Frequency(void) {
3935
3936 uint32 Frequency;
3937 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
3938 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->DSPI7PCTL & GPR4_PCTL_DSPI7PCTL_PCTL_MASK) >> GPR4_PCTL_DSPI7PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3939 return Frequency;
3940 }
3941
3942 /* Return SRX0_CLK frequency */
Clock_Ip_Get_SRX0_CLK_Frequency(void)3943 static uint32 Clock_Ip_Get_SRX0_CLK_Frequency(void) {
3944
3945 uint32 Frequency;
3946 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
3947 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->SRX0PCTL & GPR1_PCTL_SRX0PCTL_PCTL_MASK) >> GPR1_PCTL_SRX0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3948 return Frequency;
3949 }
3950
3951 /* Return SRX1_CLK frequency */
Clock_Ip_Get_SRX1_CLK_Frequency(void)3952 static uint32 Clock_Ip_Get_SRX1_CLK_Frequency(void) {
3953
3954 uint32 Frequency;
3955 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
3956 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->SRX1PCTL & GPR4_PCTL_SRX1PCTL_PCTL_MASK) >> GPR4_PCTL_SRX1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3957 return Frequency;
3958 }
3959 /* Return CORE_PLL_REFCLKOUT frequency */
Clock_Ip_Get_CORE_PLL_REFCLKOUT_Frequency(void)3960 static uint32 Clock_Ip_Get_CORE_PLL_REFCLKOUT_Frequency(void) {
3961
3962 uint32 Frequency;
3963 Frequency = (((IP_CORE_PLL->PLLCLKMUX & PLLDIG_PLLCLKMUX_REFCLKSEL_MASK) >> PLLDIG_PLLCLKMUX_REFCLKSEL_SHIFT) == 0U) ? Clock_Ip_Get_FIRC_CLK_Frequency() : Clock_Ip_Get_FXOSC_CLK_Frequency();/* Selector value */
3964 return Frequency;
3965 }
3966
3967 /* Return PERIPH_PLL_REFCLKOUT frequency */
Clock_Ip_Get_PERIPH_PLL_REFCLKOUT_Frequency(void)3968 static uint32 Clock_Ip_Get_PERIPH_PLL_REFCLKOUT_Frequency(void) {
3969
3970 uint32 Frequency;
3971 Frequency = (((IP_PERIPH_PLL->PLLCLKMUX & PLLDIG_PLLCLKMUX_REFCLKSEL_MASK) >> PLLDIG_PLLCLKMUX_REFCLKSEL_SHIFT) == 0U) ? Clock_Ip_Get_FIRC_CLK_Frequency() : Clock_Ip_Get_FXOSC_CLK_Frequency();/* Selector value */
3972 return Frequency;
3973 }
3974
3975
3976 /* Return Px_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency(void)3977 static uint32 Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency(void) {
3978
3979 return Clock_Ip_apfFreqTableCLKOUT_MULTIPLEX[Clock_Ip_u32ClkoutIndex]();/* Selector value */
3980 }
3981
3982
3983 /* Return Px_PSI5_S_UTIL_CLK frequency */
Clock_Ip_Get_Px_PSI5_S_UTIL_CLK_Frequency(void)3984 static uint32 Clock_Ip_Get_Px_PSI5_S_UTIL_CLK_Frequency(void) {
3985
3986 return Clock_Ip_apfFreqTablePSI5_S_UTIL_MULTIPLEX[Clock_Ip_u32PSI5_S_UTILIndex]();/* Selector value */
3987 }
3988
3989 /* Return PLL_VCO frequency */
PLL_VCO(const PLLDIG_Type * Base)3990 static uint32 PLL_VCO(const PLLDIG_Type *Base)
3991 {
3992 uint32 Fin;
3993 uint32 Rdiv;
3994 uint32 Mfi;
3995 uint32 Mfn;
3996 uint32 Fout;
3997 uint32 Var1;
3998 uint32 Var2;
3999 uint32 Var3;
4000 uint32 Var4;
4001 uint32 Var5;
4002 Fin = (((Base->PLLCLKMUX & PLLDIG_PLLCLKMUX_REFCLKSEL_MASK) >> PLLDIG_PLLCLKMUX_REFCLKSEL_SHIFT) == 0U) ? Clock_Ip_Get_FIRC_CLK_Frequency() : Clock_Ip_Get_FXOSC_CLK_Frequency(); /* input freq */
4003 Rdiv = ((Base->PLLDV & PLLDIG_PLLDV_RDIV_MASK) >> PLLDIG_PLLDV_RDIV_SHIFT); /* Rdiv */
4004 Mfi = ((Base->PLLDV & PLLDIG_PLLDV_MFI_MASK) >> PLLDIG_PLLDV_MFI_SHIFT); /* Mfi */
4005 Mfn = ((Base->PLLFD & PLLDIG_PLLFD_MFN_MASK) >> PLLDIG_PLLFD_MFN_SHIFT); /* Mfn */
4006
4007
4008 Var1 = Mfi / Rdiv; /* Mfi divided by Rdiv */
4009 Var2 = Mfi - (Var1 * Rdiv); /* Mfi minus Var1 multiplied by Rdiv */
4010 Var3 = (Rdiv << CLOCK_IP_MUL_BY_16384) + (Rdiv << CLOCK_IP_MUL_BY_2048); /* Rdiv multiplied by 18432 */
4011 Var4 = Fin / Var3; /* Fin divide by (Rdiv multiplied by 18432) */
4012 Var5 = Fin - (Var4 * Var3); /* Fin minus Var4 multiplied by (Rdiv mul 18432) */
4013
4014 Fout = Var1 * Fin; /* Var1 multipied by Fin */
4015 Fout += Fin / Rdiv * Var2; /* Fin divided by Rdiv and multiplied by Var2 */
4016 Fout += Var4 * Mfn; /* Mfn multiplied by Var4 */
4017 Fout += Var5 * Mfn / Var3; /* Var5 multiplied by Mfn and divide by (Rdiv mul 18432) */
4018
4019 return Fout;
4020 }
4021
4022 /* Return LFAST_PLL_VCO frequency */
LFAST_PLL_VCO(const LFAST_Type * Base)4023 static uint32 LFAST_PLL_VCO(const LFAST_Type *Base)
4024 {
4025 uint32 Fin;
4026 uint32 Prediv;
4027 uint32 PllMode;
4028 uint32 Fbdiv;
4029 uint32 Fout = 0U;
4030
4031 /* Input frequency */
4032 if (Base == IP_LFAST_0) {
4033 Fin = Clock_Ip_Get_P1_LFAST0_REF_CLK_Frequency();
4034 }
4035 else if (Base == IP_LFAST_1) {
4036 Fin = Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency();
4037 }
4038 else {
4039 Fin = 0U;
4040 }
4041
4042 Prediv = ((Base->PLLCR & LFAST_PLLCR_PREDIV_MASK) >> LFAST_PLLCR_PREDIV_SHIFT) + 1U; /* Prediv */
4043 Fbdiv = ((Base->PLLCR & LFAST_PLLCR_FBDIV_MASK) >> LFAST_PLLCR_FBDIV_SHIFT); /* multiplied */
4044 PllMode = ((Base->PLLCR & LFAST_PLLCR_FDIVEN_MASK) >> LFAST_PLLCR_FDIVEN_SHIFT); /* Pll mode */
4045
4046 Fout = (uint32)(((Fin * Fbdiv )/ Prediv) + ((Fin * PllMode)/(2U*Prediv))); /* Fin multiplied by Fbdiv and divide by (Prediv) */
4047
4048 return (((Base->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >> LFAST_PLLLSR_PLDCR_SHIFT) == 1U) ? Fout : 0U;
4049 }
4050
4051 /* Return DFS_OUTPUT frequency */
DFS_OUTPUT(const DFS_Type * Base,uint32 Channel,uint32 Fin)4052 static uint32 DFS_OUTPUT(const DFS_Type *Base, uint32 Channel, uint32 Fin)
4053 {
4054 uint32 Mfi;
4055 uint32 Mfn;
4056 uint32 Divider;
4057 uint32 DividerResult;
4058 uint32 DividerModulo;
4059
4060 Mfi = ((Base->DVPORT[Channel] & DFS_DVPORT_MFI_MASK) >> DFS_DVPORT_MFI_SHIFT); /* Mfi */
4061 Mfn = ((Base->DVPORT[Channel] & DFS_DVPORT_MFN_MASK) >> DFS_DVPORT_MFN_SHIFT); /* Mfn */
4062
4063 Divider = ((Mfi << CLOCK_IP_MUL_BY_32) + (Mfi << CLOCK_IP_MUL_BY_4) + Mfn); /* mfi multiplied by 36 add mfn */
4064 DividerResult = (Divider != 0U) ? (Fin / Divider) : 0U; /* Fin divide by Divider */
4065 DividerModulo = Fin - (Divider * DividerResult); /* Fin minus DividerResult multiplied by Divider */
4066
4067 /* DividerResult multiplied by 18 added DividerModulo multiplied by 18 divide by Divider */
4068 return (Divider != 0U) ? ((DividerResult << CLOCK_IP_MUL_BY_16) + (DividerResult << CLOCK_IP_MUL_BY_2) +
4069 (((DividerModulo << CLOCK_IP_MUL_BY_16) + (DividerModulo << CLOCK_IP_MUL_BY_2)) / Divider)) : 0U;
4070 }
4071
4072 /* Get external frequency */
Clock_Ip_SetExternalOscillatorFrequency(Clock_Ip_NameType ExtOscName,uint32 Frequency)4073 void Clock_Ip_SetExternalOscillatorFrequency(Clock_Ip_NameType ExtOscName, uint32 Frequency)
4074 {
4075 (void)ExtOscName;
4076 Clock_Ip_u32Fxosc = Frequency;
4077 }
4078 /* Get external frequency */
Clock_Ip_SetExternalSignalFrequency(Clock_Ip_NameType SignalName,uint32 Frequency)4079 void Clock_Ip_SetExternalSignalFrequency(Clock_Ip_NameType SignalName, uint32 Frequency)
4080 {
4081 uint32 Index;
4082 for (Index = 0U; Index < CLOCK_IP_EXT_SIGNALS_NO; Index++)
4083 {
4084 if (SignalName == Clock_Ip_axExtSignalFreqEntries[Index].Name)
4085 {
4086 Clock_Ip_axExtSignalFreqEntries[Index].Frequency = Frequency;
4087 break;
4088 }
4089 }
4090 }
4091
4092 /* Return LFAST0_PLL_CLK_ frequency */
Clock_Ip_Get_LFAST0_PLL_CLK_Frequency(void)4093 static uint32 Clock_Ip_Get_LFAST0_PLL_CLK_Frequency(void)
4094 {
4095 return (((IP_LFAST_0->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >> LFAST_PLLLSR_PLDCR_SHIFT) == 1U) ? LFAST_PLL_VCO(IP_LFAST_0) : 0U;
4096 }
4097 /* Return LFAST0_PLL_CLK_ frequency */
Clock_Ip_Get_LFAST1_PLL_CLK_Frequency(void)4098 static uint32 Clock_Ip_Get_LFAST1_PLL_CLK_Frequency(void)
4099 {
4100 return (((IP_LFAST_1->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >> LFAST_PLLLSR_PLDCR_SHIFT) == 1U) ? LFAST_PLL_VCO(IP_LFAST_1) : 0U;
4101 }
4102 /*==================================================================================================
4103 * GLOBAL FUNCTIONS
4104 ==================================================================================================*/
4105
4106 /* Return frequency value */
Clock_Ip_GetFreq(Clock_Ip_NameType ClockName)4107 uint32 Clock_Ip_GetFreq(Clock_Ip_NameType ClockName)
4108 {
4109 return Clock_Ip_apfFreqTable[ClockName]();
4110 }
4111
4112 /* Clock stop section code */
4113 #define MCU_STOP_SEC_CODE
4114 #include "Mcu_MemMap.h"
4115
4116 #else
4117 /* Clock start section code */
4118 #define MCU_START_SEC_CODE
4119 #include "Mcu_MemMap.h"
4120
4121 /* Set external frequency */
4122 void Clock_Ip_SetExternalSignalFrequency(Clock_Ip_NameType SignalName, uint32 Frequency)
4123 {
4124 (void)SignalName;
4125 (void)Frequency;
4126 }
4127
4128 /* Clock stop section code */
4129 #define MCU_STOP_SEC_CODE
4130 #include "Mcu_MemMap.h"
4131
4132 #endif /* #if (defined(CLOCK_IP_GET_FREQUENCY_API) && (CLOCK_IP_GET_FREQUENCY_API == STD_ON)) */
4133
4134
4135 #endif /* (CLOCK_IP_PLATFORM_SPECIFIC) */
4136
4137
4138 #ifdef __cplusplus
4139 }
4140 #endif
4141
4142 /** @} */
4143
4144
