1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 /**
7 * @file Clock_Ip_Frequency.c
8 * @version 3.0.0
9 *
10 * @brief CLOCK driver implementations.
11 * @details CLOCK driver implementations.
12 *
13 * @addtogroup CLOCK_DRIVER Clock Ip Driver
14 * @{
15 */
16
17
18 #ifdef __cplusplus
19 extern "C"{
20 #endif
21
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29
30 #include "Clock_Ip_Private.h"
31
32 #if (defined(CLOCK_IP_GET_FREQUENCY_API) && (CLOCK_IP_GET_FREQUENCY_API == STD_ON))
33
34
35 /*==================================================================================================
36 * SOURCE FILE VERSION INFORMATION
37 ==================================================================================================*/
38 #define CLOCK_IP_FREQUENCY_VENDOR_ID_C 43
39 #define CLOCK_IP_FREQUENCY_AR_RELEASE_MAJOR_VERSION_C 4
40 #define CLOCK_IP_FREQUENCY_AR_RELEASE_MINOR_VERSION_C 7
41 #define CLOCK_IP_FREQUENCY_AR_RELEASE_REVISION_VERSION_C 0
42 #define CLOCK_IP_FREQUENCY_SW_MAJOR_VERSION_C 3
43 #define CLOCK_IP_FREQUENCY_SW_MINOR_VERSION_C 0
44 #define CLOCK_IP_FREQUENCY_SW_PATCH_VERSION_C 0
45
46 /*==================================================================================================
47 * FILE VERSION CHECKS
48 ==================================================================================================*/
49 /* Check if Clock_Ip_Frequency.c file and Clock_Ip_Private.h file are of the same vendor */
50 #if (CLOCK_IP_FREQUENCY_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
51 #error "Clock_Ip_Frequency.c and Clock_Ip_Private.h have different vendor ids"
52 #endif
53
54 /* Check if Clock_Ip_Frequency.c file and Clock_Ip_Private.h file are of the same Autosar version */
55 #if ((CLOCK_IP_FREQUENCY_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
56 (CLOCK_IP_FREQUENCY_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
57 (CLOCK_IP_FREQUENCY_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
58 )
59 #error "AutoSar Version Numbers of Clock_Ip_Frequency.c and Clock_Ip_Private.h are different"
60 #endif
61
62 /* Check if Clock_Ip_Frequency.c file and Clock_Ip_Private.h file are of the same Software version */
63 #if ((CLOCK_IP_FREQUENCY_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
64 (CLOCK_IP_FREQUENCY_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
65 (CLOCK_IP_FREQUENCY_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
66 )
67 #error "Software Version Numbers of Clock_Ip_Frequency.c and Clock_Ip_Private.h are different"
68 #endif
69 /*==================================================================================================
70 LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
71 ==================================================================================================*/
72
73 typedef struct{
74
75 Clock_Ip_NameType Name;
76 uint32 Frequency;
77
78 }extSignalFreq;
79
80 /*==================================================================================================
81 * LOCAL MACROS
82 ==================================================================================================*/
83
84
85 #define CLOCK_IP_SELECTOR_SOURCE_NO 32U
86 #define CLOCK_IP_RTC_SELECTOR_SOURCE_NO 4U
87 #define CLOCK_IP_FIRC_DIV_SEL_VALS_NO 4U
88 #define CLOCK_IP_MUL_BY_16384 14U
89 #define CLOCK_IP_MUL_BY_2048 11U
90 #define CLOCK_IP_DISABLED 0U
91 #define CLOCK_IP_ENABLED 0xFFFFFFFFU
92 #define CLOCK_IP_EXT_SIGNALS_NO 4U
93 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK)
94 #define CLOCK_IP_EMAC_MII_RX_CLK_INDEX_ENTRY 0U
95 #endif
96 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK)
97 #define CLOCK_IP_EMAC_MII_RMII_TX_CLK_INDEX_ENTRY 1U
98 #endif
99 #if defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK)
100 #define CLOCK_IP_GMAC0_MII_RX_CLK_INDEX_ENTRY 0U
101 #endif
102 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK)
103 #define CLOCK_IP_GMAC0_MII_RMII_TX_CLK_INDEX_ENTRY 1U
104 #endif
105 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK)
106 #define CLOCK_IP_LFAST_REF_EXT_CLK_INDEX_ENTRY 2U
107 #endif
108 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK)
109 #define CLOCK_IP_SWG_PAD_CLK_INDEX_ENTRY 3U
110 #endif
111
112 #define CLOCK_IP_PLL_CLK_FREQ 2000000000U
113 #define CLOCK_IP_PLL_CLK_CHECKSUM 4147U
114
115 #if defined(CLOCK_IP_HAS_PLLAUX_CLK)
116 #define CLOCK_IP_PLLAUX_CLK_FREQ 2000000000U
117 #define CLOCK_IP_PLLAUX_CLK_CHECKSUM 4147U
118 #endif
119 /*==================================================================================================
120 GLOBAL FUNCTION PROTOTYPES
121 ==================================================================================================*/
122
123 /*==================================================================================================
124 LOCAL FUNCTION PROTOTYPES
125 ==================================================================================================*/
126
127 /* Clock start section code */
128 #define MCU_START_SEC_CODE
129 #include "Mcu_MemMap.h"
130
131 uint32 Clock_Ip_Get_RTC_CLK_Frequency_TrustedCall(void);
132 static uint32 Clock_Ip_PLL_VCO(const PLL_Type *Base);
133 static uint32 Clock_Ip_Get_Zero_Frequency(void);
134 static uint32 Clock_Ip_Get_FIRC_CLK_Frequency(void);
135 static uint32 Clock_Ip_Get_FIRC_STANDBY_CLK_Frequency(void);
136 static uint32 Clock_Ip_Get_SIRC_CLK_Frequency(void);
137 static uint32 Clock_Ip_Get_SIRC_STANDBY_CLK_Frequency(void);
138 static uint32 Clock_Ip_Get_FXOSC_CLK_Frequency(void);
139 #if defined(CLOCK_IP_HAS_SXOSC_CLK)
140 static uint32 Clock_Ip_Get_SXOSC_CLK_Frequency(void);
141 #endif
142 static uint32 Clock_Ip_Get_PLL_CLK_Frequency(void);
143 #if defined(CLOCK_IP_HAS_PLLAUX_CLK)
144 static uint32 Clock_Ip_Get_PLLAUX_CLK_Frequency(void);
145 #endif
146 static uint32 Clock_Ip_Get_PLL_POSTDIV_CLK_Frequency(void);
147
148 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK)
149 static uint32 Clock_Ip_Get_PLLAUX_POSTDIV_CLK_Frequency(void);
150 #endif
151 static uint32 Clock_Ip_Get_PLL_PHI0_Frequency(void);
152 static uint32 Clock_Ip_Get_PLL_PHI1_Frequency(void);
153
154 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK)
155 static uint32 Clock_Ip_Get_PLLAUX_PHI0_Frequency(void);
156 #endif
157 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK)
158 static uint32 Clock_Ip_Get_PLLAUX_PHI1_Frequency(void);
159 #endif
160 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK)
161 static uint32 Clock_Ip_Get_PLLAUX_PHI2_Frequency(void);
162 #endif
163 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK)
164 static uint32 Clock_Ip_Get_emac_mii_rx_Frequency(void);
165 #endif
166 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK)
167 static uint32 Clock_Ip_Get_emac_mii_rmii_tx_Frequency(void);
168 #endif
169 #if defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK)
170 static uint32 Clock_Ip_Get_gmac0_mii_rx_Frequency(void);
171 #endif
172 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK)
173 static uint32 Clock_Ip_Get_gmac0_mii_rmii_tx_Frequency(void);
174 #endif
175 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK)
176 static uint32 Clock_Ip_Get_lfast_ext_ref_Frequency(void);
177 #endif
178 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK)
179 static uint32 Clock_Ip_Get_swg_pad_Frequency(void);
180 #endif
181 static uint32 Clock_Ip_Get_SCS_CLK_Frequency(void);
182 static uint32 Clock_Ip_Get_CORE_CLK_Frequency(void);
183 static uint32 Clock_Ip_Get_AIPS_PLAT_CLK_Frequency(void);
184 static uint32 Clock_Ip_Get_AIPS_SLOW_CLK_Frequency(void);
185 static uint32 Clock_Ip_Get_HSE_CLK_Frequency(void);
186 static uint32 Clock_Ip_Get_DCM_CLK_Frequency(void);
187 #if defined(CLOCK_IP_HAS_LBIST_CLK)
188 static uint32 Clock_Ip_Get_LBIST_CLK_Frequency(void);
189 #endif
190 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK)
191 static uint32 Clock_Ip_Get_QSPI_MEM_CLK_Frequency(void);
192 #endif
193 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK)
194 static uint32 Clock_Ip_Get_CM7_CORE_CLK_Frequency(void);
195 #endif
196 static uint32 Clock_Ip_Get_CLKOUT_RUN_CLK_Frequency(void);
197 static uint32 Clock_Ip_Get_ADC0_CLK_Frequency(void);
198 static uint32 Clock_Ip_Get_ADC1_CLK_Frequency(void);
199 #if defined(CLOCK_IP_HAS_ADC2_CLK)
200 static uint32 Clock_Ip_Get_ADC2_CLK_Frequency(void);
201 #endif
202 #if defined(CLOCK_IP_HAS_ADC3_CLK)
203 static uint32 Clock_Ip_Get_ADC3_CLK_Frequency(void);
204 #endif
205 #if defined(CLOCK_IP_HAS_ADC4_CLK)
206 static uint32 Clock_Ip_Get_ADC4_CLK_Frequency(void);
207 #endif
208 #if defined(CLOCK_IP_HAS_ADC5_CLK)
209 static uint32 Clock_Ip_Get_ADC5_CLK_Frequency(void);
210 #endif
211 #if defined(CLOCK_IP_HAS_ADC6_CLK)
212 static uint32 Clock_Ip_Get_ADC6_CLK_Frequency(void);
213 #endif
214 #if defined(CLOCK_IP_HAS_ADCBIST_CLK)
215 static uint32 Clock_Ip_Get_ADCBIST_CLK_Frequency(void);
216 #endif
217 #if defined(CLOCK_IP_HAS_AXBS_CLK)
218 static uint32 Clock_Ip_Get_AXBS_CLK_Frequency(void);
219 #endif
220 #if defined(CLOCK_IP_HAS_AXBS0_CLK)
221 static uint32 Clock_Ip_Get_AXBS0_CLK_Frequency(void);
222 #endif
223 #if defined(CLOCK_IP_HAS_AXBS1_CLK)
224 static uint32 Clock_Ip_Get_AXBS1_CLK_Frequency(void);
225 #endif
226 static uint32 Clock_Ip_Get_BCTU0_CLK_Frequency(void);
227 #if defined(CLOCK_IP_HAS_BCTU1_CLK)
228 static uint32 Clock_Ip_Get_BCTU1_CLK_Frequency(void);
229 #endif
230 static uint32 Clock_Ip_Get_CLKOUT_STANDBY_CLK_Frequency(void);
231 static uint32 Clock_Ip_Get_CMP0_CLK_Frequency(void);
232 #if defined(CLOCK_IP_HAS_CMP1_CLK)
233 static uint32 Clock_Ip_Get_CMP1_CLK_Frequency(void);
234 #endif
235 #if defined(CLOCK_IP_HAS_CMP2_CLK)
236 static uint32 Clock_Ip_Get_CMP2_CLK_Frequency(void);
237 #endif
238 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK)
239 static uint32 Clock_Ip_Get_COOLFLUX_D_RAM0_CLK_Frequency(void);
240 #endif
241 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK)
242 static uint32 Clock_Ip_Get_COOLFLUX_D_RAM1_CLK_Frequency(void);
243 #endif
244 #if defined(CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK)
245 static uint32 Clock_Ip_Get_COOLFLUX_DSP16L_CLK_Frequency(void);
246 #endif
247 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK)
248 static uint32 Clock_Ip_Get_COOLFLUX_I_RAM0_CLK_Frequency(void);
249 #endif
250 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK)
251 static uint32 Clock_Ip_Get_COOLFLUX_I_RAM1_CLK_Frequency(void);
252 #endif
253 static uint32 Clock_Ip_Get_CRC0_CLK_Frequency(void);
254 static uint32 Clock_Ip_Get_DMAMUX0_CLK_Frequency(void);
255 static uint32 Clock_Ip_Get_DMAMUX1_CLK_Frequency(void);
256 #if defined(CLOCK_IP_HAS_DMAMUX2_CLK)
257 static uint32 Clock_Ip_Get_DMAMUX2_CLK_Frequency(void);
258 #endif
259 #if defined(CLOCK_IP_HAS_DMAMUX3_CLK)
260 static uint32 Clock_Ip_Get_DMAMUX3_CLK_Frequency(void);
261 #endif
262 #if defined(CLOCK_IP_HAS_DSPI_MSC_CLK)
263 static uint32 Clock_Ip_Get_DSPI_MSC_CLK_Frequency(void);
264 #endif
265 static uint32 Clock_Ip_Get_EDMA0_CLK_Frequency(void);
266 static uint32 Clock_Ip_Get_EDMA0_TCD0_CLK_Frequency(void);
267 static uint32 Clock_Ip_Get_EDMA0_TCD1_CLK_Frequency(void);
268 static uint32 Clock_Ip_Get_EDMA0_TCD2_CLK_Frequency(void);
269 static uint32 Clock_Ip_Get_EDMA0_TCD3_CLK_Frequency(void);
270 static uint32 Clock_Ip_Get_EDMA0_TCD4_CLK_Frequency(void);
271 static uint32 Clock_Ip_Get_EDMA0_TCD5_CLK_Frequency(void);
272 static uint32 Clock_Ip_Get_EDMA0_TCD6_CLK_Frequency(void);
273 static uint32 Clock_Ip_Get_EDMA0_TCD7_CLK_Frequency(void);
274 static uint32 Clock_Ip_Get_EDMA0_TCD8_CLK_Frequency(void);
275 static uint32 Clock_Ip_Get_EDMA0_TCD9_CLK_Frequency(void);
276 static uint32 Clock_Ip_Get_EDMA0_TCD10_CLK_Frequency(void);
277 static uint32 Clock_Ip_Get_EDMA0_TCD11_CLK_Frequency(void);
278 #if defined(CLOCK_IP_HAS_EDMA0_TCD12_CLK)
279 static uint32 Clock_Ip_Get_EDMA0_TCD12_CLK_Frequency(void);
280 #endif
281 #if defined(CLOCK_IP_HAS_EDMA0_TCD13_CLK)
282 static uint32 Clock_Ip_Get_EDMA0_TCD13_CLK_Frequency(void);
283 #endif
284 #if defined(CLOCK_IP_HAS_EDMA0_TCD14_CLK)
285 static uint32 Clock_Ip_Get_EDMA0_TCD14_CLK_Frequency(void);
286 #endif
287 #if defined(CLOCK_IP_HAS_EDMA0_TCD15_CLK)
288 static uint32 Clock_Ip_Get_EDMA0_TCD15_CLK_Frequency(void);
289 #endif
290 #if defined(CLOCK_IP_HAS_EDMA0_TCD16_CLK)
291 static uint32 Clock_Ip_Get_EDMA0_TCD16_CLK_Frequency(void);
292 #endif
293 #if defined(CLOCK_IP_HAS_EDMA0_TCD17_CLK)
294 static uint32 Clock_Ip_Get_EDMA0_TCD17_CLK_Frequency(void);
295 #endif
296 #if defined(CLOCK_IP_HAS_EDMA0_TCD18_CLK)
297 static uint32 Clock_Ip_Get_EDMA0_TCD18_CLK_Frequency(void);
298 #endif
299 #if defined(CLOCK_IP_HAS_EDMA0_TCD19_CLK)
300 static uint32 Clock_Ip_Get_EDMA0_TCD19_CLK_Frequency(void);
301 #endif
302 #if defined(CLOCK_IP_HAS_EDMA0_TCD20_CLK)
303 static uint32 Clock_Ip_Get_EDMA0_TCD20_CLK_Frequency(void);
304 #endif
305 #if defined(CLOCK_IP_HAS_EDMA0_TCD21_CLK)
306 static uint32 Clock_Ip_Get_EDMA0_TCD21_CLK_Frequency(void);
307 #endif
308 #if defined(CLOCK_IP_HAS_EDMA0_TCD22_CLK)
309 static uint32 Clock_Ip_Get_EDMA0_TCD22_CLK_Frequency(void);
310 #endif
311 #if defined(CLOCK_IP_HAS_EDMA0_TCD23_CLK)
312 static uint32 Clock_Ip_Get_EDMA0_TCD23_CLK_Frequency(void);
313 #endif
314 #if defined(CLOCK_IP_HAS_EDMA0_TCD24_CLK)
315 static uint32 Clock_Ip_Get_EDMA0_TCD24_CLK_Frequency(void);
316 #endif
317 #if defined(CLOCK_IP_HAS_EDMA0_TCD25_CLK)
318 static uint32 Clock_Ip_Get_EDMA0_TCD25_CLK_Frequency(void);
319 #endif
320 #if defined(CLOCK_IP_HAS_EDMA0_TCD26_CLK)
321 static uint32 Clock_Ip_Get_EDMA0_TCD26_CLK_Frequency(void);
322 #endif
323 #if defined(CLOCK_IP_HAS_EDMA0_TCD27_CLK)
324 static uint32 Clock_Ip_Get_EDMA0_TCD27_CLK_Frequency(void);
325 #endif
326 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK)
327 static uint32 Clock_Ip_Get_EDMA0_TCD28_CLK_Frequency(void);
328 #endif
329 #if defined(CLOCK_IP_HAS_EDMA0_TCD29_CLK)
330 static uint32 Clock_Ip_Get_EDMA0_TCD29_CLK_Frequency(void);
331 #endif
332 #if defined(CLOCK_IP_HAS_EDMA0_TCD30_CLK)
333 static uint32 Clock_Ip_Get_EDMA0_TCD30_CLK_Frequency(void);
334 #endif
335 #if defined(CLOCK_IP_HAS_EDMA0_TCD31_CLK)
336 static uint32 Clock_Ip_Get_EDMA0_TCD31_CLK_Frequency(void);
337 #endif
338 #if defined(CLOCK_IP_HAS_EDMA1_CLK)
339 static uint32 Clock_Ip_Get_EDMA1_CLK_Frequency(void);
340 #endif
341 #if defined(CLOCK_IP_HAS_EDMA1_TCD0_CLK)
342 static uint32 Clock_Ip_Get_EDMA1_TCD0_CLK_Frequency(void);
343 #endif
344 #if defined(CLOCK_IP_HAS_EDMA1_TCD1_CLK)
345 static uint32 Clock_Ip_Get_EDMA1_TCD1_CLK_Frequency(void);
346 #endif
347 #if defined(CLOCK_IP_HAS_EDMA1_TCD2_CLK)
348 static uint32 Clock_Ip_Get_EDMA1_TCD2_CLK_Frequency(void);
349 #endif
350 #if defined(CLOCK_IP_HAS_EDMA1_TCD3_CLK)
351 static uint32 Clock_Ip_Get_EDMA1_TCD3_CLK_Frequency(void);
352 #endif
353 #if defined(CLOCK_IP_HAS_EDMA1_TCD4_CLK)
354 static uint32 Clock_Ip_Get_EDMA1_TCD4_CLK_Frequency(void);
355 #endif
356 #if defined(CLOCK_IP_HAS_EDMA1_TCD5_CLK)
357 static uint32 Clock_Ip_Get_EDMA1_TCD5_CLK_Frequency(void);
358 #endif
359 #if defined(CLOCK_IP_HAS_EDMA1_TCD6_CLK)
360 static uint32 Clock_Ip_Get_EDMA1_TCD6_CLK_Frequency(void);
361 #endif
362 #if defined(CLOCK_IP_HAS_EDMA1_TCD7_CLK)
363 static uint32 Clock_Ip_Get_EDMA1_TCD7_CLK_Frequency(void);
364 #endif
365 #if defined(CLOCK_IP_HAS_EDMA1_TCD8_CLK)
366 static uint32 Clock_Ip_Get_EDMA1_TCD8_CLK_Frequency(void);
367 #endif
368 #if defined(CLOCK_IP_HAS_EDMA1_TCD9_CLK)
369 static uint32 Clock_Ip_Get_EDMA1_TCD9_CLK_Frequency(void);
370 #endif
371 #if defined(CLOCK_IP_HAS_EDMA1_TCD10_CLK)
372 static uint32 Clock_Ip_Get_EDMA1_TCD10_CLK_Frequency(void);
373 #endif
374 #if defined(CLOCK_IP_HAS_EDMA1_TCD11_CLK)
375 static uint32 Clock_Ip_Get_EDMA1_TCD11_CLK_Frequency(void);
376 #endif
377 #if defined(CLOCK_IP_HAS_EDMA1_TCD12_CLK)
378 static uint32 Clock_Ip_Get_EDMA1_TCD12_CLK_Frequency(void);
379 #endif
380 #if defined(CLOCK_IP_HAS_EDMA1_TCD13_CLK)
381 static uint32 Clock_Ip_Get_EDMA1_TCD13_CLK_Frequency(void);
382 #endif
383 #if defined(CLOCK_IP_HAS_EDMA1_TCD14_CLK)
384 static uint32 Clock_Ip_Get_EDMA1_TCD14_CLK_Frequency(void);
385 #endif
386 #if defined(CLOCK_IP_HAS_EDMA1_TCD15_CLK)
387 static uint32 Clock_Ip_Get_EDMA1_TCD15_CLK_Frequency(void);
388 #endif
389 #if defined(CLOCK_IP_HAS_EDMA1_TCD16_CLK)
390 static uint32 Clock_Ip_Get_EDMA1_TCD16_CLK_Frequency(void);
391 #endif
392 #if defined(CLOCK_IP_HAS_EDMA1_TCD17_CLK)
393 static uint32 Clock_Ip_Get_EDMA1_TCD17_CLK_Frequency(void);
394 #endif
395 #if defined(CLOCK_IP_HAS_EDMA1_TCD18_CLK)
396 static uint32 Clock_Ip_Get_EDMA1_TCD18_CLK_Frequency(void);
397 #endif
398 #if defined(CLOCK_IP_HAS_EDMA1_TCD19_CLK)
399 static uint32 Clock_Ip_Get_EDMA1_TCD19_CLK_Frequency(void);
400 #endif
401 #if defined(CLOCK_IP_HAS_EDMA1_TCD20_CLK)
402 static uint32 Clock_Ip_Get_EDMA1_TCD20_CLK_Frequency(void);
403 #endif
404 #if defined(CLOCK_IP_HAS_EDMA1_TCD21_CLK)
405 static uint32 Clock_Ip_Get_EDMA1_TCD21_CLK_Frequency(void);
406 #endif
407 #if defined(CLOCK_IP_HAS_EDMA1_TCD22_CLK)
408 static uint32 Clock_Ip_Get_EDMA1_TCD22_CLK_Frequency(void);
409 #endif
410 #if defined(CLOCK_IP_HAS_EDMA1_TCD23_CLK)
411 static uint32 Clock_Ip_Get_EDMA1_TCD23_CLK_Frequency(void);
412 #endif
413 #if defined(CLOCK_IP_HAS_EDMA1_TCD24_CLK)
414 static uint32 Clock_Ip_Get_EDMA1_TCD24_CLK_Frequency(void);
415 #endif
416 #if defined(CLOCK_IP_HAS_EDMA1_TCD25_CLK)
417 static uint32 Clock_Ip_Get_EDMA1_TCD25_CLK_Frequency(void);
418 #endif
419 #if defined(CLOCK_IP_HAS_EDMA1_TCD26_CLK)
420 static uint32 Clock_Ip_Get_EDMA1_TCD26_CLK_Frequency(void);
421 #endif
422 #if defined(CLOCK_IP_HAS_EDMA1_TCD27_CLK)
423 static uint32 Clock_Ip_Get_EDMA1_TCD27_CLK_Frequency(void);
424 #endif
425 #if defined(CLOCK_IP_HAS_EDMA1_TCD28_CLK)
426 static uint32 Clock_Ip_Get_EDMA1_TCD28_CLK_Frequency(void);
427 #endif
428 #if defined(CLOCK_IP_HAS_EDMA1_TCD29_CLK)
429 static uint32 Clock_Ip_Get_EDMA1_TCD29_CLK_Frequency(void);
430 #endif
431 #if defined(CLOCK_IP_HAS_EDMA1_TCD30_CLK)
432 static uint32 Clock_Ip_Get_EDMA1_TCD30_CLK_Frequency(void);
433 #endif
434 #if defined(CLOCK_IP_HAS_EDMA1_TCD31_CLK)
435 static uint32 Clock_Ip_Get_EDMA1_TCD31_CLK_Frequency(void);
436 #endif
437 #if defined(CLOCK_IP_HAS_EFLEX_PWM0_CLK)
438 static uint32 Clock_Ip_Get_EFLEX_PWM0_CLK_Frequency(void);
439 #endif
440 #if defined(CLOCK_IP_HAS_EFLEX_PWM1_CLK)
441 static uint32 Clock_Ip_Get_EFLEX_PWM1_CLK_Frequency(void);
442 #endif
443 #if defined(CLOCK_IP_HAS_EIM_CLK)
444 static uint32 Clock_Ip_Get_EIM_CLK_Frequency(void);
445 #endif
446 #if defined(CLOCK_IP_HAS_EIM0_CLK)
447 static uint32 Clock_Ip_Get_EIM0_CLK_Frequency(void);
448 #endif
449 #if defined(CLOCK_IP_HAS_EIM1_CLK)
450 static uint32 Clock_Ip_Get_EIM1_CLK_Frequency(void);
451 #endif
452 #if defined(CLOCK_IP_HAS_EIM2_CLK)
453 static uint32 Clock_Ip_Get_EIM2_CLK_Frequency(void);
454 #endif
455 #if defined(CLOCK_IP_HAS_EIM3_CLK)
456 static uint32 Clock_Ip_Get_EIM3_CLK_Frequency(void);
457 #endif
458 #if defined(CLOCK_IP_HAS_GMAC0_CLK)
459 static uint32 Clock_Ip_Get_GMAC0_CLK_Frequency(void);
460 #endif
461 #if defined(CLOCK_IP_HAS_GMAC1_CLK)
462 static uint32 Clock_Ip_Get_GMAC1_CLK_Frequency(void);
463 #endif
464 #if defined(CLOCK_IP_HAS_GMAC0_RX_CLK)
465 static uint32 Clock_Ip_Get_GMAC0_RX_CLK_Frequency(void);
466 #endif
467 #if defined(CLOCK_IP_HAS_GMAC0_TX_CLK)
468 static uint32 Clock_Ip_Get_GMAC0_TX_CLK_Frequency(void);
469 #endif
470 #if defined(CLOCK_IP_HAS_GMAC_TS_CLK)
471 static uint32 Clock_Ip_Get_GMAC_TS_CLK_Frequency(void);
472 #endif
473 #if defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK)
474 static uint32 Clock_Ip_Get_GMAC0_TX_RMII_CLK_Frequency(void);
475 #endif
476 #if defined(CLOCK_IP_HAS_GMAC1_RX_CLK)
477 static uint32 Clock_Ip_Get_GMAC1_RX_CLK_Frequency(void);
478 #endif
479 #if defined(CLOCK_IP_HAS_GMAC1_TX_CLK)
480 static uint32 Clock_Ip_Get_GMAC1_TX_CLK_Frequency(void);
481 #endif
482 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK)
483 static uint32 Clock_Ip_Get_GMAC1_RMII_CLK_Frequency(void);
484 #endif
485 #if defined(CLOCK_IP_HAS_AES_CLK)
486 static uint32 Clock_Ip_Get_AES_CLK_Frequency(void);
487 #endif
488 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK)
489 static uint32 Clock_Ip_Get_EMAC_RX_CLK_Frequency(void);
490 #endif
491 #if defined(CLOCK_IP_HAS_EMAC0_RX_CLK)
492 static uint32 Clock_Ip_Get_EMAC0_RX_CLK_Frequency(void);
493 #endif
494 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK)
495 static uint32 Clock_Ip_Get_EMAC_TS_CLK_Frequency(void);
496 #endif
497 #if defined(CLOCK_IP_HAS_EMAC0_TS_CLK)
498 static uint32 Clock_Ip_Get_EMAC0_TS_CLK_Frequency(void);
499 #endif
500 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK)
501 static uint32 Clock_Ip_Get_EMAC_TX_CLK_Frequency(void);
502 #endif
503 #if defined(CLOCK_IP_HAS_EMAC0_TX_CLK)
504 static uint32 Clock_Ip_Get_EMAC0_TX_CLK_Frequency(void);
505 #endif
506 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK)
507 static uint32 Clock_Ip_Get_EMAC_TX_RMII_CLK_Frequency(void);
508 #endif
509 static uint32 Clock_Ip_Get_EMIOS0_CLK_Frequency(void);
510 #if defined(CLOCK_IP_HAS_EMIOS1_CLK)
511 static uint32 Clock_Ip_Get_EMIOS1_CLK_Frequency(void);
512 #endif
513 #if defined(CLOCK_IP_HAS_EMIOS2_CLK)
514 static uint32 Clock_Ip_Get_EMIOS2_CLK_Frequency(void);
515 #endif
516 static uint32 Clock_Ip_Get_ERM0_CLK_Frequency(void);
517 #if defined(CLOCK_IP_HAS_ERM1_CLK)
518 static uint32 Clock_Ip_Get_ERM1_CLK_Frequency(void);
519 #endif
520 #if defined(CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK)
521 static uint32 Clock_Ip_Get_ETPU_AB_REGISTERS_CLK_Frequency(void);
522 #endif
523 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK)
524 static uint32 Clock_Ip_Get_ETPU_CODE_RAM1_CLK_Frequency(void);
525 #endif
526 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK)
527 static uint32 Clock_Ip_Get_ETPU_CODE_RAM2_CLK_Frequency(void);
528 #endif
529 #if defined(CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK)
530 static uint32 Clock_Ip_Get_ETPU_RAM_MIRROR_CLK_Frequency(void);
531 #endif
532 #if defined(CLOCK_IP_HAS_ETPU_RAM_SDM_CLK)
533 static uint32 Clock_Ip_Get_ETPU_RAM_SDM_CLK_Frequency(void);
534 #endif
535 #if defined(CLOCK_IP_HAS_FCCU_CLK)
536 static uint32 Clock_Ip_Get_FCCU_CLK_Frequency(void);
537 #endif
538 #if defined(CLOCK_IP_HAS_FLASH0_CLK)
539 static uint32 Clock_Ip_Get_FLASH0_CLK_Frequency(void);
540 #endif
541 #if defined(CLOCK_IP_HAS_FLASH0_ALT_CLK)
542 static uint32 Clock_Ip_Get_FLASH0_ALT_CLK_Frequency(void);
543 #endif
544 #if defined(CLOCK_IP_HAS_FLASH1_CLK)
545 static uint32 Clock_Ip_Get_FLASH1_CLK_Frequency(void);
546 #endif
547 #if defined(CLOCK_IP_HAS_FLASH1_ALT_CLK)
548 static uint32 Clock_Ip_Get_FLASH1_ALT_CLK_Frequency(void);
549 #endif
550 static uint32 Clock_Ip_Get_FLEXCANA_CLK_Frequency(void);
551 static uint32 Clock_Ip_Get_FLEXCAN0_CLK_Frequency(void);
552 static uint32 Clock_Ip_Get_FLEXCAN1_CLK_Frequency(void);
553 static uint32 Clock_Ip_Get_FLEXCAN2_CLK_Frequency(void);
554 #if defined(CLOCK_IP_HAS_FLEXCANB_CLK)
555 static uint32 Clock_Ip_Get_FLEXCANB_CLK_Frequency(void);
556 #endif
557 #if defined(CLOCK_IP_HAS_FLEXCAN3_CLK)
558 static uint32 Clock_Ip_Get_FLEXCAN3_CLK_Frequency(void);
559 #endif
560 #if defined(CLOCK_IP_HAS_FLEXCAN4_CLK)
561 static uint32 Clock_Ip_Get_FLEXCAN4_CLK_Frequency(void);
562 #endif
563 #if defined(CLOCK_IP_HAS_FLEXCAN5_CLK)
564 static uint32 Clock_Ip_Get_FLEXCAN5_CLK_Frequency(void);
565 #endif
566 #if defined(CLOCK_IP_HAS_FLEXCAN6_CLK)
567 static uint32 Clock_Ip_Get_FLEXCAN6_CLK_Frequency(void);
568 #endif
569 #if defined(CLOCK_IP_HAS_FLEXCAN7_CLK)
570 static uint32 Clock_Ip_Get_FLEXCAN7_CLK_Frequency(void);
571 #endif
572 static uint32 Clock_Ip_Get_FLEXIO0_CLK_Frequency(void);
573 #if defined(CLOCK_IP_HAS_HSE_MU0_CLK)
574 static uint32 Clock_Ip_Get_HSE_MU0_CLK_Frequency(void);
575 #endif
576 #if defined(CLOCK_IP_HAS_HSE_MU1_CLK)
577 static uint32 Clock_Ip_Get_HSE_MU1_CLK_Frequency(void);
578 #endif
579 #if defined(CLOCK_IP_HAS_JDC_CLK)
580 static uint32 Clock_Ip_Get_JDC_CLK_Frequency(void);
581 #endif
582 #if defined(CLOCK_IP_HAS_IGF0_CLK)
583 static uint32 Clock_Ip_Get_IGF0_CLK_Frequency(void);
584 #endif
585 static uint32 Clock_Ip_Get_INTM_CLK_Frequency(void);
586 static uint32 Clock_Ip_Get_LCU0_CLK_Frequency(void);
587 static uint32 Clock_Ip_Get_LCU1_CLK_Frequency(void);
588 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK)
589 static uint32 Clock_Ip_Get_LFAST_REF_CLK_Frequency(void);
590 #endif
591 #if defined(CLOCK_IP_HAS_LPI2C0_CLK)
592 static uint32 Clock_Ip_Get_LPI2C0_CLK_Frequency(void);
593 #endif
594 static uint32 Clock_Ip_Get_LPI2C1_CLK_Frequency(void);
595 static uint32 Clock_Ip_Get_LPSPI0_CLK_Frequency(void);
596 static uint32 Clock_Ip_Get_LPSPI1_CLK_Frequency(void);
597 static uint32 Clock_Ip_Get_LPSPI2_CLK_Frequency(void);
598 static uint32 Clock_Ip_Get_LPSPI3_CLK_Frequency(void);
599 #if defined(CLOCK_IP_HAS_LPSPI4_CLK)
600 static uint32 Clock_Ip_Get_LPSPI4_CLK_Frequency(void);
601 #endif
602 #if defined(CLOCK_IP_HAS_LPSPI5_CLK)
603 static uint32 Clock_Ip_Get_LPSPI5_CLK_Frequency(void);
604 #endif
605 static uint32 Clock_Ip_Get_LPUART0_CLK_Frequency(void);
606 static uint32 Clock_Ip_Get_LPUART1_CLK_Frequency(void);
607 static uint32 Clock_Ip_Get_LPUART2_CLK_Frequency(void);
608 static uint32 Clock_Ip_Get_LPUART3_CLK_Frequency(void);
609 #if defined(CLOCK_IP_HAS_LPUART4_CLK)
610 static uint32 Clock_Ip_Get_LPUART4_CLK_Frequency(void);
611 #endif
612 #if defined(CLOCK_IP_HAS_LPUART5_CLK)
613 static uint32 Clock_Ip_Get_LPUART5_CLK_Frequency(void);
614 #endif
615 #if defined(CLOCK_IP_HAS_LPUART6_CLK)
616 static uint32 Clock_Ip_Get_LPUART6_CLK_Frequency(void);
617 #endif
618 #if defined(CLOCK_IP_HAS_LPUART7_CLK)
619 static uint32 Clock_Ip_Get_LPUART7_CLK_Frequency(void);
620 #endif
621 #if defined(CLOCK_IP_HAS_LPUART8_CLK)
622 static uint32 Clock_Ip_Get_LPUART8_CLK_Frequency(void);
623 #endif
624 #if defined(CLOCK_IP_HAS_LPUART9_CLK)
625 static uint32 Clock_Ip_Get_LPUART9_CLK_Frequency(void);
626 #endif
627 #if defined(CLOCK_IP_HAS_LPUART10_CLK)
628 static uint32 Clock_Ip_Get_LPUART10_CLK_Frequency(void);
629 #endif
630 #if defined(CLOCK_IP_HAS_LPUART11_CLK)
631 static uint32 Clock_Ip_Get_LPUART11_CLK_Frequency(void);
632 #endif
633 #if defined(CLOCK_IP_HAS_LPUART12_CLK)
634 static uint32 Clock_Ip_Get_LPUART12_CLK_Frequency(void);
635 #endif
636 #if defined(CLOCK_IP_HAS_LPUART13_CLK)
637 static uint32 Clock_Ip_Get_LPUART13_CLK_Frequency(void);
638 #endif
639 #if defined(CLOCK_IP_HAS_LPUART14_CLK)
640 static uint32 Clock_Ip_Get_LPUART14_CLK_Frequency(void);
641 #endif
642 #if defined(CLOCK_IP_HAS_LPUART15_CLK)
643 static uint32 Clock_Ip_Get_LPUART15_CLK_Frequency(void);
644 #endif
645 #if defined(CLOCK_IP_HAS_LPUART_MSC_CLK)
646 static uint32 Clock_Ip_Get_LPUART_MSC_CLK_Frequency(void);
647 #endif
648 static uint32 Clock_Ip_Get_MSCM_CLK_Frequency(void);
649 #if defined(CLOCK_IP_HAS_MU2A_CLK)
650 static uint32 Clock_Ip_Get_MU2A_CLK_Frequency(void);
651 #endif
652 #if defined(CLOCK_IP_HAS_MU2B_CLK)
653 static uint32 Clock_Ip_Get_MU2B_CLK_Frequency(void);
654 #endif
655 #if defined(CLOCK_IP_HAS_MU3A_CLK)
656 static uint32 Clock_Ip_Get_MU3A_CLK_Frequency(void);
657 #endif
658 #if defined(CLOCK_IP_HAS_MU3B_CLK)
659 static uint32 Clock_Ip_Get_MU3B_CLK_Frequency(void);
660 #endif
661 #if defined(CLOCK_IP_HAS_MU4A_CLK)
662 static uint32 Clock_Ip_Get_MU4A_CLK_Frequency(void);
663 #endif
664 #if defined(CLOCK_IP_HAS_MU4B_CLK)
665 static uint32 Clock_Ip_Get_MU4B_CLK_Frequency(void);
666 #endif
667 static uint32 Clock_Ip_Get_PIT0_CLK_Frequency(void);
668 static uint32 Clock_Ip_Get_PIT1_CLK_Frequency(void);
669 #if defined(CLOCK_IP_HAS_PIT2_CLK)
670 static uint32 Clock_Ip_Get_PIT2_CLK_Frequency(void);
671 #endif
672 #if defined(CLOCK_IP_HAS_PIT3_CLK)
673 static uint32 Clock_Ip_Get_PIT3_CLK_Frequency(void);
674 #endif
675 #if defined(CLOCK_IP_HAS_PRAMC0_CLK)
676 static uint32 Clock_Ip_Get_PRAMC0_CLK_Frequency(void);
677 #endif
678 #if defined(CLOCK_IP_HAS_PRAMC1_CLK)
679 static uint32 Clock_Ip_Get_PRAMC1_CLK_Frequency(void);
680 #endif
681 #if defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK)
682 static uint32 Clock_Ip_Get_QSPI_2XSFIF_CLK_Frequency(void);
683 #endif
684 #if defined(CLOCK_IP_HAS_QSPI0_CLK)
685 static uint32 Clock_Ip_Get_QSPI0_CLK_Frequency(void);
686 #endif
687 #if defined(CLOCK_IP_HAS_QSPI0_RAM_CLK)
688 static uint32 Clock_Ip_Get_QSPI0_RAM_CLK_Frequency(void);
689 #endif
690 #if defined(CLOCK_IP_HAS_QSPI0_TX_MEM_CLK)
691 static uint32 Clock_Ip_Get_QSPI0_TX_MEM_CLK_Frequency(void);
692 #endif
693 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK)
694 static uint32 Clock_Ip_Get_QSPI_SFCK_CLK_Frequency(void);
695 #endif
696 static uint32 Clock_Ip_Get_RTC_CLK_Frequency(void);
697 static uint32 Clock_Ip_Get_RTC0_CLK_Frequency(void);
698 #if defined(CLOCK_IP_HAS_SAI0_CLK)
699 static uint32 Clock_Ip_Get_SAI0_CLK_Frequency(void);
700 #endif
701 #if defined(CLOCK_IP_HAS_SAI1_CLK)
702 static uint32 Clock_Ip_Get_SAI1_CLK_Frequency(void);
703 #endif
704 #if defined(CLOCK_IP_HAS_SDA_AP_CLK)
705 static uint32 Clock_Ip_Get_SDA_AP_CLK_Frequency(void);
706 #endif
707 #if defined(CLOCK_IP_HAS_SDADC0_CLK)
708 static uint32 Clock_Ip_Get_SDADC0_CLK_Frequency(void);
709 #endif
710 #if defined(CLOCK_IP_HAS_SDADC1_CLK)
711 static uint32 Clock_Ip_Get_SDADC1_CLK_Frequency(void);
712 #endif
713 #if defined(CLOCK_IP_HAS_SDADC2_CLK)
714 static uint32 Clock_Ip_Get_SDADC2_CLK_Frequency(void);
715 #endif
716 #if defined(CLOCK_IP_HAS_SDADC3_CLK)
717 static uint32 Clock_Ip_Get_SDADC3_CLK_Frequency(void);
718 #endif
719 #if defined(CLOCK_IP_HAS_SEMA42_CLK)
720 static uint32 Clock_Ip_Get_SEMA42_CLK_Frequency(void);
721 #endif
722 #if defined(CLOCK_IP_HAS_SIPI0_CLK)
723 static uint32 Clock_Ip_Get_SIPI0_CLK_Frequency(void);
724 #endif
725 static uint32 Clock_Ip_Get_SIUL2_CLK_Frequency(void);
726 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_0_CLK)
727 static uint32 Clock_Ip_Get_SIUL2_PDAC0_0_CLK_Frequency(void);
728 #endif
729 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_1_CLK)
730 static uint32 Clock_Ip_Get_SIUL2_PDAC0_1_CLK_Frequency(void);
731 #endif
732 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_0_CLK)
733 static uint32 Clock_Ip_Get_SIUL2_PDAC1_0_CLK_Frequency(void);
734 #endif
735 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_1_CLK)
736 static uint32 Clock_Ip_Get_SIUL2_PDAC1_1_CLK_Frequency(void);
737 #endif
738 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_0_CLK)
739 static uint32 Clock_Ip_Get_SIUL2_PDAC2_0_CLK_Frequency(void);
740 #endif
741 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_1_CLK)
742 static uint32 Clock_Ip_Get_SIUL2_PDAC2_1_CLK_Frequency(void);
743 #endif
744 static uint32 Clock_Ip_Get_STCU0_CLK_Frequency(void);
745 static uint32 Clock_Ip_Get_STMA_CLK_Frequency(void);
746 static uint32 Clock_Ip_Get_STM0_CLK_Frequency(void);
747 #if defined(CLOCK_IP_HAS_STMB_CLK)
748 static uint32 Clock_Ip_Get_STMB_CLK_Frequency(void);
749 #endif
750 #if defined(CLOCK_IP_HAS_STM1_CLK)
751 static uint32 Clock_Ip_Get_STM1_CLK_Frequency(void);
752 #endif
753 #if defined(CLOCK_IP_HAS_STMC_CLK)
754 static uint32 Clock_Ip_Get_STMC_CLK_Frequency(void);
755 #endif
756 #if defined(CLOCK_IP_HAS_STM2_CLK)
757 static uint32 Clock_Ip_Get_STM2_CLK_Frequency(void);
758 #endif
759 #if defined(CLOCK_IP_HAS_STMD_CLK)
760 static uint32 Clock_Ip_Get_STMD_CLK_Frequency(void);
761 #endif
762 #if defined(CLOCK_IP_HAS_STM3_CLK)
763 static uint32 Clock_Ip_Get_STM3_CLK_Frequency(void);
764 #endif
765 #if defined(CLOCK_IP_HAS_USDHC_CLK)
766 static uint32 Clock_Ip_Get_USDHC_CLK_Frequency(void);
767 #endif
768 #if defined(CLOCK_IP_HAS_SWG_CLK)
769 static uint32 Clock_Ip_Get_SWG_CLK_Frequency(void);
770 #endif
771 #if defined(CLOCK_IP_HAS_SWG0_CLK)
772 static uint32 Clock_Ip_Get_SWG0_CLK_Frequency(void);
773 #endif
774 #if defined(CLOCK_IP_HAS_SWG1_CLK)
775 static uint32 Clock_Ip_Get_SWG1_CLK_Frequency(void);
776 #endif
777 static uint32 Clock_Ip_Get_SWT0_CLK_Frequency(void);
778 #if defined(CLOCK_IP_HAS_SWT1_CLK)
779 static uint32 Clock_Ip_Get_SWT1_CLK_Frequency(void);
780 #endif
781 #if defined(CLOCK_IP_HAS_SWT2_CLK)
782 static uint32 Clock_Ip_Get_SWT2_CLK_Frequency(void);
783 #endif
784 #if defined(CLOCK_IP_HAS_SWT3_CLK)
785 static uint32 Clock_Ip_Get_SWT3_CLK_Frequency(void);
786 #endif
787 #if defined(CLOCK_IP_HAS_TCM_CM7_0_CLK)
788 static uint32 Clock_Ip_Get_TCM_CM7_0_CLK_Frequency(void);
789 #endif
790 #if defined(CLOCK_IP_HAS_TCM_CM7_1_CLK)
791 static uint32 Clock_Ip_Get_TCM_CM7_1_CLK_Frequency(void);
792 #endif
793 static uint32 Clock_Ip_Get_TEMPSENSE_CLK_Frequency(void);
794 static uint32 Clock_Ip_Get_TRACE_CLK_Frequency(void);
795 static uint32 Clock_Ip_Get_TRGMUX0_CLK_Frequency(void);
796 #if defined(CLOCK_IP_HAS_TRGMUX1_CLK)
797 static uint32 Clock_Ip_Get_TRGMUX1_CLK_Frequency(void);
798 #endif
799 #if defined(CLOCK_IP_HAS_TSENSE0_CLK)
800 static uint32 Clock_Ip_Get_TSENSE0_CLK_Frequency(void);
801 #endif
802 static uint32 Clock_Ip_Get_WKPU0_CLK_Frequency(void);
803 #if defined(CLOCK_IP_HAS_XRDC_CLK)
804 static uint32 Clock_Ip_Get_XRDC_CLK_Frequency(void);
805 #endif
806 #if defined(CLOCK_IP_HAS_AES_ACCEL_CLK)
807 static uint32 Clock_Ip_Get_AES_ACCEL_CLK_Frequency(void);
808 #endif
809 #if defined(CLOCK_IP_HAS_AES_APP0_CLK)
810 static uint32 Clock_Ip_Get_AES_APP0_CLK_Frequency(void);
811 #endif
812 #if defined(CLOCK_IP_HAS_AES_APP1_CLK)
813 static uint32 Clock_Ip_Get_AES_APP1_CLK_Frequency(void);
814 #endif
815 #if defined(CLOCK_IP_HAS_AES_APP2_CLK)
816 static uint32 Clock_Ip_Get_AES_APP2_CLK_Frequency(void);
817 #endif
818 #if defined(CLOCK_IP_HAS_AES_APP3_CLK)
819 static uint32 Clock_Ip_Get_AES_APP3_CLK_Frequency(void);
820 #endif
821 #if defined(CLOCK_IP_HAS_AES_APP4_CLK)
822 static uint32 Clock_Ip_Get_AES_APP4_CLK_Frequency(void);
823 #endif
824 #if defined(CLOCK_IP_HAS_AES_APP5_CLK)
825 static uint32 Clock_Ip_Get_AES_APP5_CLK_Frequency(void);
826 #endif
827 #if defined(CLOCK_IP_HAS_AES_APP6_CLK)
828 static uint32 Clock_Ip_Get_AES_APP6_CLK_Frequency(void);
829 #endif
830 #if defined(CLOCK_IP_HAS_AES_APP7_CLK)
831 static uint32 Clock_Ip_Get_AES_APP7_CLK_Frequency(void);
832 #endif
833
834 /* Clock stop section code */
835 #define MCU_STOP_SEC_CODE
836 #include "Mcu_MemMap.h"
837
838 /*==================================================================================================
839 LOCAL CONSTANTS
840 ==================================================================================================*/
841
842 /* Clock start constant section data */
843 #define MCU_START_SEC_CONST_UNSPECIFIED
844 #include "Mcu_MemMap.h"
845
846 typedef uint32 (*getFreqType)(void);
847 static const getFreqType Clock_Ip_apfFreqTableClkSrc[CLOCK_IP_SELECTOR_SOURCE_NO] =
848 {
849 Clock_Ip_Get_FIRC_CLK_Frequency, /* clock name for 0 hardware value */
850 Clock_Ip_Get_SIRC_CLK_Frequency, /* clock name for 1 hardware value */
851 Clock_Ip_Get_FXOSC_CLK_Frequency, /* clock name for 2 hardware value */
852 Clock_Ip_Get_Zero_Frequency, /* clock name for 3 hardware value */
853 #if defined(CLOCK_IP_HAS_SXOSC_CLK)
854 Clock_Ip_Get_SXOSC_CLK_Frequency, /* clock name for 4 hardware value */
855 #else
856 Clock_Ip_Get_Zero_Frequency,
857 #endif
858 Clock_Ip_Get_Zero_Frequency, /* clock name for 5 hardware value */
859 Clock_Ip_Get_Zero_Frequency, /* clock name for 6 hardware value */
860 Clock_Ip_Get_Zero_Frequency, /* clock name for 7 hardware value */
861 Clock_Ip_Get_PLL_PHI0_Frequency,
862 Clock_Ip_Get_PLL_PHI1_Frequency,
863 Clock_Ip_Get_Zero_Frequency, /* clock name for 10 hardware value */
864 Clock_Ip_Get_Zero_Frequency, /* clock name for 11 hardware value */
865 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK)
866 Clock_Ip_Get_PLLAUX_PHI0_Frequency,
867 #else
868 Clock_Ip_Get_Zero_Frequency,
869 #endif
870 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK)
871 Clock_Ip_Get_PLLAUX_PHI1_Frequency,
872 #else
873 Clock_Ip_Get_Zero_Frequency,
874 #endif
875 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK)
876 Clock_Ip_Get_PLLAUX_PHI2_Frequency,
877 #else
878 Clock_Ip_Get_Zero_Frequency,
879 #endif
880 Clock_Ip_Get_Zero_Frequency, /* clock name for 15 hardware value */
881 Clock_Ip_Get_CORE_CLK_Frequency, /* clock name for 16 hardware value */
882 Clock_Ip_Get_Zero_Frequency, /* clock name for 17 hardware value */
883 Clock_Ip_Get_Zero_Frequency, /* clock name for 18 hardware value */
884 Clock_Ip_Get_HSE_CLK_Frequency, /* clock name for 19 hardware value */
885 Clock_Ip_Get_Zero_Frequency, /* clock name for 20 hardware value */
886 Clock_Ip_Get_Zero_Frequency, /* clock name for 21 hardware value */
887 Clock_Ip_Get_AIPS_PLAT_CLK_Frequency, /* clock name for 22 hardware value */
888 Clock_Ip_Get_AIPS_SLOW_CLK_Frequency, /* clock name for 23 hardware value */
889 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK)
890 Clock_Ip_Get_emac_mii_rmii_tx_Frequency, /* clock name for 24 hardware value */
891 #elif defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK)
892 Clock_Ip_Get_gmac0_mii_rmii_tx_Frequency, /* clock name for 24 hardware value */
893 #else
894 Clock_Ip_Get_Zero_Frequency,
895 #endif
896 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK)
897 Clock_Ip_Get_emac_mii_rx_Frequency, /* clock name for 25 hardware value */
898 #elif defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK)
899 Clock_Ip_Get_gmac0_mii_rx_Frequency, /* clock name for 25 hardware value */
900 #else
901 Clock_Ip_Get_Zero_Frequency,
902 #endif
903 Clock_Ip_Get_Zero_Frequency, /* clock name for 26 hardware value */
904 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK)
905 Clock_Ip_Get_lfast_ext_ref_Frequency, /* clock name for 27 hardware value */
906 #else
907 Clock_Ip_Get_Zero_Frequency,
908 #endif
909 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK)
910 Clock_Ip_Get_swg_pad_Frequency, /* clock name for 28 hardware value */
911 #else
912 Clock_Ip_Get_Zero_Frequency,
913 #endif
914 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
915 Clock_Ip_Get_Zero_Frequency, /* clock name for 30 hardware value */
916 Clock_Ip_Get_Zero_Frequency, /* clock name for 31 hardware value */
917 };
918
919 static const getFreqType Clock_Ip_apfFreqTableRTC_CLK[CLOCK_IP_RTC_SELECTOR_SOURCE_NO] =
920 {
921 #if defined(CLOCK_IP_HAS_SXOSC_CLK)
922 Clock_Ip_Get_SXOSC_CLK_Frequency, /* clock name for 0 hardware value */
923 #else
924 Clock_Ip_Get_Zero_Frequency,
925 #endif
926 Clock_Ip_Get_SIRC_CLK_Frequency, /* clock name for 1 hardware value */
927 Clock_Ip_Get_FIRC_CLK_Frequency, /* clock name for 2 hardware value */
928 Clock_Ip_Get_FXOSC_CLK_Frequency, /* clock name for 3 hardware value */
929 };
930
931 static const getFreqType Clock_Ip_apfFreqTable[CLOCK_IP_NAMES_NO] =
932 {
933 Clock_Ip_Get_Zero_Frequency, /* CLOCK_IS_OFF */
934 Clock_Ip_Get_FIRC_CLK_Frequency, /* FIRC_CLK */
935 Clock_Ip_Get_FIRC_STANDBY_CLK_Frequency, /* FIRC_STANDBY_CLK */
936 Clock_Ip_Get_SIRC_CLK_Frequency, /* SIRC_CLK */
937 Clock_Ip_Get_SIRC_STANDBY_CLK_Frequency, /* SIRC_STANDBY_CLK */
938 Clock_Ip_Get_FXOSC_CLK_Frequency, /* FXOSC_CLK */
939 #if defined(CLOCK_IP_HAS_SXOSC_CLK)
940 Clock_Ip_Get_SXOSC_CLK_Frequency, /* SXOSC_CLK */
941 #endif
942 Clock_Ip_Get_PLL_CLK_Frequency,
943 #if defined(CLOCK_IP_HAS_PLLAUX_CLK)
944 Clock_Ip_Get_PLLAUX_CLK_Frequency,
945 #endif
946 Clock_Ip_Get_PLL_POSTDIV_CLK_Frequency,
947 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK)
948 Clock_Ip_Get_PLLAUX_POSTDIV_CLK_Frequency,
949 #endif
950 Clock_Ip_Get_PLL_PHI0_Frequency,
951 Clock_Ip_Get_PLL_PHI1_Frequency,
952 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK)
953 Clock_Ip_Get_PLLAUX_PHI0_Frequency,
954 #endif
955 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK)
956 Clock_Ip_Get_PLLAUX_PHI1_Frequency,
957 #endif
958 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK)
959 Clock_Ip_Get_PLLAUX_PHI2_Frequency,
960 #endif
961 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK)
962 Clock_Ip_Get_emac_mii_rx_Frequency, /* emac_mii_rx */
963 #elif defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK)
964 Clock_Ip_Get_gmac0_mii_rx_Frequency, /* emac_mii_rx */
965 #endif
966 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK)
967 Clock_Ip_Get_emac_mii_rmii_tx_Frequency, /* emac_mii_rmii_tx */
968 #elif defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK)
969 Clock_Ip_Get_gmac0_mii_rmii_tx_Frequency, /* emac_mii_rmii_tx */
970 #endif
971 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK)
972 Clock_Ip_Get_lfast_ext_ref_Frequency, /* lfast_ext_ref */
973 #endif
974 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK)
975 Clock_Ip_Get_swg_pad_Frequency, /* swg_pad */
976 #endif
977 Clock_Ip_Get_SCS_CLK_Frequency, /* SCS_CLK */
978 Clock_Ip_Get_CORE_CLK_Frequency, /* CORE_CLK */
979 Clock_Ip_Get_AIPS_PLAT_CLK_Frequency, /* AIPS_PLAT_CLK */
980 Clock_Ip_Get_AIPS_SLOW_CLK_Frequency, /* AIPS_SLOW_CLK */
981 Clock_Ip_Get_HSE_CLK_Frequency, /* HSE_CLK */
982 Clock_Ip_Get_DCM_CLK_Frequency, /* DCM_CLK */
983 #if defined(CLOCK_IP_HAS_LBIST_CLK)
984 Clock_Ip_Get_LBIST_CLK_Frequency, /* LBIST_CLK */
985 #endif
986 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK)
987 Clock_Ip_Get_QSPI_MEM_CLK_Frequency, /* QSPI_MEM_CLK */
988 #endif
989 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK)
990 Clock_Ip_Get_CM7_CORE_CLK_Frequency, /* CM7_CORE_CLK */
991 #endif
992 Clock_Ip_Get_CLKOUT_RUN_CLK_Frequency, /* CLKOUT_RUN_CLK */
993 Clock_Ip_Get_Zero_Frequency, /* THE_LAST_PRODUCER_CLK */
994 Clock_Ip_Get_ADC0_CLK_Frequency, /* ADC0_CLK */
995 Clock_Ip_Get_ADC1_CLK_Frequency, /* ADC1_CLK */
996 #if defined(CLOCK_IP_HAS_ADC2_CLK)
997 Clock_Ip_Get_ADC2_CLK_Frequency, /* ADC2_CLK */
998 #endif
999 #if defined(CLOCK_IP_HAS_ADC3_CLK)
1000 Clock_Ip_Get_ADC3_CLK_Frequency, /* ADC3_CLK */
1001 #endif
1002 #if defined(CLOCK_IP_HAS_ADC4_CLK)
1003 Clock_Ip_Get_ADC4_CLK_Frequency, /* ADC4_CLK */
1004 #endif
1005 #if defined(CLOCK_IP_HAS_ADC5_CLK)
1006 Clock_Ip_Get_ADC5_CLK_Frequency, /* ADC5_CLK */
1007 #endif
1008 #if defined(CLOCK_IP_HAS_ADC6_CLK)
1009 Clock_Ip_Get_ADC6_CLK_Frequency, /* ADC6_CLK */
1010 #endif
1011 #if defined(CLOCK_IP_HAS_ADCBIST_CLK)
1012 Clock_Ip_Get_ADCBIST_CLK_Frequency, /* ADCBIST_CLK */
1013 #endif
1014 #if defined(CLOCK_IP_HAS_AES_ACCEL_CLK)
1015 Clock_Ip_Get_AES_ACCEL_CLK_Frequency, /* AES_ACCEL_CLK */
1016 #endif
1017 #if defined(CLOCK_IP_HAS_AES_APP0_CLK)
1018 Clock_Ip_Get_AES_APP0_CLK_Frequency, /* AES_APP0_CLK */
1019 #endif
1020 #if defined(CLOCK_IP_HAS_AES_APP1_CLK)
1021 Clock_Ip_Get_AES_APP1_CLK_Frequency, /* AES_APP1_CLK */
1022 #endif
1023 #if defined(CLOCK_IP_HAS_AES_APP2_CLK)
1024 Clock_Ip_Get_AES_APP2_CLK_Frequency, /* AES_APP2_CLK */
1025 #endif
1026 #if defined(CLOCK_IP_HAS_AES_APP3_CLK)
1027 Clock_Ip_Get_AES_APP3_CLK_Frequency, /* AES_APP3_CLK */
1028 #endif
1029 #if defined(CLOCK_IP_HAS_AES_APP4_CLK)
1030 Clock_Ip_Get_AES_APP4_CLK_Frequency, /* AES_APP4_CLK */
1031 #endif
1032 #if defined(CLOCK_IP_HAS_AES_APP5_CLK)
1033 Clock_Ip_Get_AES_APP5_CLK_Frequency, /* AES_APP5_CLK */
1034 #endif
1035 #if defined(CLOCK_IP_HAS_AES_APP6_CLK)
1036 Clock_Ip_Get_AES_APP6_CLK_Frequency, /* AES_APP6_CLK */
1037 #endif
1038 #if defined(CLOCK_IP_HAS_AES_APP7_CLK)
1039 Clock_Ip_Get_AES_APP7_CLK_Frequency, /* AES_APP7_CLK */
1040 #endif
1041 #if defined(CLOCK_IP_HAS_AES_CLK)
1042 Clock_Ip_Get_AES_CLK_Frequency, /* AES_CLK */
1043 #endif
1044 #if defined(CLOCK_IP_HAS_AXBS_CLK)
1045 Clock_Ip_Get_AXBS_CLK_Frequency, /* AXBS_CLK */
1046 #endif
1047 #if defined(CLOCK_IP_HAS_AXBS0_CLK)
1048 Clock_Ip_Get_AXBS0_CLK_Frequency, /* AXBS0_CLK */
1049 #endif
1050 #if defined(CLOCK_IP_HAS_AXBS1_CLK)
1051 Clock_Ip_Get_AXBS1_CLK_Frequency, /* AXBS1_CLK */
1052 #endif
1053 Clock_Ip_Get_BCTU0_CLK_Frequency, /* BCTU0_CLK */
1054 #if defined(CLOCK_IP_HAS_BCTU1_CLK)
1055 Clock_Ip_Get_BCTU1_CLK_Frequency, /* BCTU1_CLK */
1056 #endif
1057 Clock_Ip_Get_CLKOUT_STANDBY_CLK_Frequency, /* CLKOUT_STANDBY_CLK */
1058 Clock_Ip_Get_CMP0_CLK_Frequency, /* CMP0_CLK */
1059 #if defined(CLOCK_IP_HAS_CMP1_CLK)
1060 Clock_Ip_Get_CMP1_CLK_Frequency, /* CMP1_CLK */
1061 #endif
1062 #if defined(CLOCK_IP_HAS_CMP2_CLK)
1063 Clock_Ip_Get_CMP2_CLK_Frequency, /* CMP2_CLK */
1064 #endif
1065 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK)
1066 Clock_Ip_Get_COOLFLUX_D_RAM0_CLK_Frequency, /* COOLFLUX_D_RAM0_CLK */
1067 #endif
1068 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK)
1069 Clock_Ip_Get_COOLFLUX_D_RAM1_CLK_Frequency, /* COOLFLUX_D_RAM1_CLK */
1070 #endif
1071 #if defined(CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK)
1072 Clock_Ip_Get_COOLFLUX_DSP16L_CLK_Frequency, /* COOLFLUX_DSP16L_CLK */
1073 #endif
1074 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK)
1075 Clock_Ip_Get_COOLFLUX_I_RAM0_CLK_Frequency, /* COOLFLUX_I_RAM0_CLK */
1076 #endif
1077 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK)
1078 Clock_Ip_Get_COOLFLUX_I_RAM1_CLK_Frequency, /* COOLFLUX_I_RAM1_CLK */
1079 #endif
1080 Clock_Ip_Get_CRC0_CLK_Frequency, /* CRC0_CLK */
1081 Clock_Ip_Get_DCM_CLK_Frequency, /* DCM0_CLK */
1082 Clock_Ip_Get_DMAMUX0_CLK_Frequency, /* DMAMUX0_CLK */
1083 Clock_Ip_Get_DMAMUX1_CLK_Frequency, /* DMAMUX1_CLK */
1084 #if defined(CLOCK_IP_HAS_DMAMUX2_CLK)
1085 Clock_Ip_Get_DMAMUX2_CLK_Frequency, /* DMAMUX2_CLK */
1086 #endif
1087 #if defined(CLOCK_IP_HAS_DMAMUX3_CLK)
1088 Clock_Ip_Get_DMAMUX3_CLK_Frequency, /* DMAMUX3_CLK */
1089 #endif
1090 #if defined(CLOCK_IP_HAS_DSPI_MSC_CLK)
1091 Clock_Ip_Get_DSPI_MSC_CLK_Frequency, /* DSPI_MSC_CLK */
1092 #endif
1093 Clock_Ip_Get_EDMA0_CLK_Frequency, /* EDMA0_CLK */
1094 Clock_Ip_Get_EDMA0_TCD0_CLK_Frequency, /* EDMA0_TCD0_CLK */
1095 Clock_Ip_Get_EDMA0_TCD1_CLK_Frequency, /* EDMA0_TCD1_CLK */
1096 Clock_Ip_Get_EDMA0_TCD2_CLK_Frequency, /* EDMA0_TCD2_CLK */
1097 Clock_Ip_Get_EDMA0_TCD3_CLK_Frequency, /* EDMA0_TCD3_CLK */
1098 Clock_Ip_Get_EDMA0_TCD4_CLK_Frequency, /* EDMA0_TCD4_CLK */
1099 Clock_Ip_Get_EDMA0_TCD5_CLK_Frequency, /* EDMA0_TCD5_CLK */
1100 Clock_Ip_Get_EDMA0_TCD6_CLK_Frequency, /* EDMA0_TCD6_CLK */
1101 Clock_Ip_Get_EDMA0_TCD7_CLK_Frequency, /* EDMA0_TCD7_CLK */
1102 Clock_Ip_Get_EDMA0_TCD8_CLK_Frequency, /* EDMA0_TCD8_CLK */
1103 Clock_Ip_Get_EDMA0_TCD9_CLK_Frequency, /* EDMA0_TCD9_CLK */
1104 Clock_Ip_Get_EDMA0_TCD10_CLK_Frequency, /* EDMA0_TCD10_CLK */
1105 Clock_Ip_Get_EDMA0_TCD11_CLK_Frequency, /* EDMA0_TCD11_CLK */
1106 #if defined(CLOCK_IP_HAS_EDMA0_TCD12_CLK)
1107 Clock_Ip_Get_EDMA0_TCD12_CLK_Frequency, /* EDMA0_TCD12_CLK */
1108 #endif
1109 #if defined(CLOCK_IP_HAS_EDMA0_TCD13_CLK)
1110 Clock_Ip_Get_EDMA0_TCD13_CLK_Frequency, /* EDMA0_TCD13_CLK */
1111 #endif
1112 #if defined(CLOCK_IP_HAS_EDMA0_TCD14_CLK)
1113 Clock_Ip_Get_EDMA0_TCD14_CLK_Frequency, /* EDMA0_TCD14_CLK */
1114 #endif
1115 #if defined(CLOCK_IP_HAS_EDMA0_TCD15_CLK)
1116 Clock_Ip_Get_EDMA0_TCD15_CLK_Frequency, /* EDMA0_TCD15_CLK */
1117 #endif
1118 #if defined(CLOCK_IP_HAS_EDMA0_TCD16_CLK)
1119 Clock_Ip_Get_EDMA0_TCD16_CLK_Frequency, /* EDMA0_TCD16_CLK */
1120 #endif
1121 #if defined(CLOCK_IP_HAS_EDMA0_TCD17_CLK)
1122 Clock_Ip_Get_EDMA0_TCD17_CLK_Frequency, /* EDMA0_TCD17_CLK */
1123 #endif
1124 #if defined(CLOCK_IP_HAS_EDMA0_TCD18_CLK)
1125 Clock_Ip_Get_EDMA0_TCD18_CLK_Frequency, /* EDMA0_TCD18_CLK */
1126 #endif
1127 #if defined(CLOCK_IP_HAS_EDMA0_TCD19_CLK)
1128 Clock_Ip_Get_EDMA0_TCD19_CLK_Frequency, /* EDMA0_TCD19_CLK */
1129 #endif
1130 #if defined(CLOCK_IP_HAS_EDMA0_TCD20_CLK)
1131 Clock_Ip_Get_EDMA0_TCD20_CLK_Frequency, /* EDMA0_TCD20_CLK */
1132 #endif
1133 #if defined(CLOCK_IP_HAS_EDMA0_TCD21_CLK)
1134 Clock_Ip_Get_EDMA0_TCD21_CLK_Frequency, /* EDMA0_TCD21_CLK */
1135 #endif
1136 #if defined(CLOCK_IP_HAS_EDMA0_TCD22_CLK)
1137 Clock_Ip_Get_EDMA0_TCD22_CLK_Frequency, /* EDMA0_TCD22_CLK */
1138 #endif
1139 #if defined(CLOCK_IP_HAS_EDMA0_TCD23_CLK)
1140 Clock_Ip_Get_EDMA0_TCD23_CLK_Frequency, /* EDMA0_TCD23_CLK */
1141 #endif
1142 #if defined(CLOCK_IP_HAS_EDMA0_TCD24_CLK)
1143 Clock_Ip_Get_EDMA0_TCD24_CLK_Frequency, /* EDMA0_TCD24_CLK */
1144 #endif
1145 #if defined(CLOCK_IP_HAS_EDMA0_TCD25_CLK)
1146 Clock_Ip_Get_EDMA0_TCD25_CLK_Frequency, /* EDMA0_TCD25_CLK */
1147 #endif
1148 #if defined(CLOCK_IP_HAS_EDMA0_TCD26_CLK)
1149 Clock_Ip_Get_EDMA0_TCD26_CLK_Frequency, /* EDMA0_TCD26_CLK */
1150 #endif
1151 #if defined(CLOCK_IP_HAS_EDMA0_TCD27_CLK)
1152 Clock_Ip_Get_EDMA0_TCD27_CLK_Frequency, /* EDMA0_TCD27_CLK */
1153 #endif
1154 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK)
1155 Clock_Ip_Get_EDMA0_TCD28_CLK_Frequency, /* EDMA0_TCD28_CLK */
1156 #endif
1157 #if defined(CLOCK_IP_HAS_EDMA0_TCD29_CLK)
1158 Clock_Ip_Get_EDMA0_TCD29_CLK_Frequency, /* EDMA0_TCD29_CLK */
1159 #endif
1160 #if defined(CLOCK_IP_HAS_EDMA0_TCD30_CLK)
1161 Clock_Ip_Get_EDMA0_TCD30_CLK_Frequency, /* EDMA0_TCD30_CLK */
1162 #endif
1163 #if defined(CLOCK_IP_HAS_EDMA0_TCD31_CLK)
1164 Clock_Ip_Get_EDMA0_TCD31_CLK_Frequency, /* EDMA0_TCD31_CLK */
1165 #endif
1166 #if defined(CLOCK_IP_HAS_EDMA1_CLK)
1167 Clock_Ip_Get_EDMA1_CLK_Frequency, /* EDMA1_CLK */
1168 #endif
1169 #if defined(CLOCK_IP_HAS_EDMA1_TCD0_CLK)
1170 Clock_Ip_Get_EDMA1_TCD0_CLK_Frequency, /* EDMA1_TCD0_CLK */
1171 #endif
1172 #if defined(CLOCK_IP_HAS_EDMA1_TCD1_CLK)
1173 Clock_Ip_Get_EDMA1_TCD1_CLK_Frequency, /* EDMA1_TCD1_CLK */
1174 #endif
1175 #if defined(CLOCK_IP_HAS_EDMA1_TCD2_CLK)
1176 Clock_Ip_Get_EDMA1_TCD2_CLK_Frequency, /* EDMA1_TCD2_CLK */
1177 #endif
1178 #if defined(CLOCK_IP_HAS_EDMA1_TCD3_CLK)
1179 Clock_Ip_Get_EDMA1_TCD3_CLK_Frequency, /* EDMA1_TCD3_CLK */
1180 #endif
1181 #if defined(CLOCK_IP_HAS_EDMA1_TCD4_CLK)
1182 Clock_Ip_Get_EDMA1_TCD4_CLK_Frequency, /* EDMA1_TCD4_CLK */
1183 #endif
1184 #if defined(CLOCK_IP_HAS_EDMA1_TCD5_CLK)
1185 Clock_Ip_Get_EDMA1_TCD5_CLK_Frequency, /* EDMA1_TCD5_CLK */
1186 #endif
1187 #if defined(CLOCK_IP_HAS_EDMA1_TCD6_CLK)
1188 Clock_Ip_Get_EDMA1_TCD6_CLK_Frequency, /* EDMA1_TCD6_CLK */
1189 #endif
1190 #if defined(CLOCK_IP_HAS_EDMA1_TCD7_CLK)
1191 Clock_Ip_Get_EDMA1_TCD7_CLK_Frequency, /* EDMA1_TCD7_CLK */
1192 #endif
1193 #if defined(CLOCK_IP_HAS_EDMA1_TCD8_CLK)
1194 Clock_Ip_Get_EDMA1_TCD8_CLK_Frequency, /* EDMA1_TCD8_CLK */
1195 #endif
1196 #if defined(CLOCK_IP_HAS_EDMA1_TCD9_CLK)
1197 Clock_Ip_Get_EDMA1_TCD9_CLK_Frequency, /* EDMA1_TCD9_CLK */
1198 #endif
1199 #if defined(CLOCK_IP_HAS_EDMA1_TCD10_CLK)
1200 Clock_Ip_Get_EDMA1_TCD10_CLK_Frequency, /* EDMA1_TCD10_CLK */
1201 #endif
1202 #if defined(CLOCK_IP_HAS_EDMA1_TCD11_CLK)
1203 Clock_Ip_Get_EDMA1_TCD11_CLK_Frequency, /* EDMA1_TCD11_CLK */
1204 #endif
1205 #if defined(CLOCK_IP_HAS_EDMA1_TCD12_CLK)
1206 Clock_Ip_Get_EDMA1_TCD12_CLK_Frequency, /* EDMA1_TCD12_CLK */
1207 #endif
1208 #if defined(CLOCK_IP_HAS_EDMA1_TCD13_CLK)
1209 Clock_Ip_Get_EDMA1_TCD13_CLK_Frequency, /* EDMA1_TCD13_CLK */
1210 #endif
1211 #if defined(CLOCK_IP_HAS_EDMA1_TCD14_CLK)
1212 Clock_Ip_Get_EDMA1_TCD14_CLK_Frequency, /* EDMA1_TCD14_CLK */
1213 #endif
1214 #if defined(CLOCK_IP_HAS_EDMA1_TCD15_CLK)
1215 Clock_Ip_Get_EDMA1_TCD15_CLK_Frequency, /* EDMA1_TCD15_CLK */
1216 #endif
1217 #if defined(CLOCK_IP_HAS_EDMA1_TCD16_CLK)
1218 Clock_Ip_Get_EDMA1_TCD16_CLK_Frequency, /* EDMA1_TCD16_CLK */
1219 #endif
1220 #if defined(CLOCK_IP_HAS_EDMA1_TCD17_CLK)
1221 Clock_Ip_Get_EDMA1_TCD17_CLK_Frequency, /* EDMA1_TCD17_CLK */
1222 #endif
1223 #if defined(CLOCK_IP_HAS_EDMA1_TCD18_CLK)
1224 Clock_Ip_Get_EDMA1_TCD18_CLK_Frequency, /* EDMA1_TCD18_CLK */
1225 #endif
1226 #if defined(CLOCK_IP_HAS_EDMA1_TCD19_CLK)
1227 Clock_Ip_Get_EDMA1_TCD19_CLK_Frequency, /* EDMA1_TCD19_CLK */
1228 #endif
1229 #if defined(CLOCK_IP_HAS_EDMA1_TCD20_CLK)
1230 Clock_Ip_Get_EDMA1_TCD20_CLK_Frequency, /* EDMA1_TCD20_CLK */
1231 #endif
1232 #if defined(CLOCK_IP_HAS_EDMA1_TCD21_CLK)
1233 Clock_Ip_Get_EDMA1_TCD21_CLK_Frequency, /* EDMA1_TCD21_CLK */
1234 #endif
1235 #if defined(CLOCK_IP_HAS_EDMA1_TCD22_CLK)
1236 Clock_Ip_Get_EDMA1_TCD22_CLK_Frequency, /* EDMA1_TCD22_CLK */
1237 #endif
1238 #if defined(CLOCK_IP_HAS_EDMA1_TCD23_CLK)
1239 Clock_Ip_Get_EDMA1_TCD23_CLK_Frequency, /* EDMA1_TCD23_CLK */
1240 #endif
1241 #if defined(CLOCK_IP_HAS_EDMA1_TCD24_CLK)
1242 Clock_Ip_Get_EDMA1_TCD24_CLK_Frequency, /* EDMA1_TCD24_CLK */
1243 #endif
1244 #if defined(CLOCK_IP_HAS_EDMA1_TCD25_CLK)
1245 Clock_Ip_Get_EDMA1_TCD25_CLK_Frequency, /* EDMA1_TCD25_CLK */
1246 #endif
1247 #if defined(CLOCK_IP_HAS_EDMA1_TCD26_CLK)
1248 Clock_Ip_Get_EDMA1_TCD26_CLK_Frequency, /* EDMA1_TCD26_CLK */
1249 #endif
1250 #if defined(CLOCK_IP_HAS_EDMA1_TCD27_CLK)
1251 Clock_Ip_Get_EDMA1_TCD27_CLK_Frequency, /* EDMA1_TCD27_CLK */
1252 #endif
1253 #if defined(CLOCK_IP_HAS_EDMA1_TCD28_CLK)
1254 Clock_Ip_Get_EDMA1_TCD28_CLK_Frequency, /* EDMA1_TCD28_CLK */
1255 #endif
1256 #if defined(CLOCK_IP_HAS_EDMA1_TCD29_CLK)
1257 Clock_Ip_Get_EDMA1_TCD29_CLK_Frequency, /* EDMA1_TCD29_CLK */
1258 #endif
1259 #if defined(CLOCK_IP_HAS_EDMA1_TCD30_CLK)
1260 Clock_Ip_Get_EDMA1_TCD30_CLK_Frequency, /* EDMA1_TCD30_CLK */
1261 #endif
1262 #if defined(CLOCK_IP_HAS_EDMA1_TCD31_CLK)
1263 Clock_Ip_Get_EDMA1_TCD31_CLK_Frequency, /* EDMA1_TCD31_CLK */
1264 #endif
1265 #if defined(CLOCK_IP_HAS_EFLEX_PWM0_CLK)
1266 Clock_Ip_Get_EFLEX_PWM0_CLK_Frequency, /* EFLEX_PWM0_CLK */
1267 #endif
1268 #if defined(CLOCK_IP_HAS_EFLEX_PWM1_CLK)
1269 Clock_Ip_Get_EFLEX_PWM1_CLK_Frequency, /* EFLEX_PWM1_CLK */
1270 #endif
1271 #if defined(CLOCK_IP_HAS_EIM_CLK)
1272 Clock_Ip_Get_EIM_CLK_Frequency, /* EIM_CLK */
1273 #endif
1274 #if defined(CLOCK_IP_HAS_EIM0_CLK)
1275 Clock_Ip_Get_EIM0_CLK_Frequency, /* EIM0_CLK */
1276 #endif
1277 #if defined(CLOCK_IP_HAS_EIM1_CLK)
1278 Clock_Ip_Get_EIM1_CLK_Frequency, /* EIM1_CLK */
1279 #endif
1280 #if defined(CLOCK_IP_HAS_EIM2_CLK)
1281 Clock_Ip_Get_EIM2_CLK_Frequency, /* EIM2_CLK */
1282 #endif
1283 #if defined(CLOCK_IP_HAS_EIM3_CLK)
1284 Clock_Ip_Get_EIM3_CLK_Frequency, /* EIM3_CLK */
1285 #endif
1286 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK)
1287 Clock_Ip_Get_EMAC_RX_CLK_Frequency, /* EMAC_RX_CLK */
1288 #endif
1289 #if defined(CLOCK_IP_HAS_EMAC0_RX_CLK)
1290 Clock_Ip_Get_EMAC0_RX_CLK_Frequency, /* EMAC0_RX_CLK */
1291 #endif
1292 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK)
1293 Clock_Ip_Get_EMAC_TS_CLK_Frequency, /* EMAC_TS_CLK */
1294 #endif
1295 #if defined(CLOCK_IP_HAS_EMAC0_TS_CLK)
1296 Clock_Ip_Get_EMAC0_TS_CLK_Frequency, /* EMAC0_TS_CLK */
1297 #endif
1298 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK)
1299 Clock_Ip_Get_EMAC_TX_CLK_Frequency, /* EMAC_TX_CLK */
1300 #endif
1301 #if defined(CLOCK_IP_HAS_EMAC0_TX_CLK)
1302 Clock_Ip_Get_EMAC0_TX_CLK_Frequency, /* EMAC0_TX_CLK */
1303 #endif
1304 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK)
1305 Clock_Ip_Get_EMAC_TX_RMII_CLK_Frequency, /* EMAC_TX_RMII_CLK */
1306 #endif
1307 #if defined(CLOCK_IP_HAS_EMAC0_TX_RMII_CLK)
1308 Clock_Ip_Get_EMAC_TX_RMII_CLK_Frequency, /* EMAC0_TX_RMII_CLK */
1309 #endif
1310 Clock_Ip_Get_EMIOS0_CLK_Frequency, /* EMIOS0_CLK */
1311 #if defined(CLOCK_IP_HAS_EMIOS1_CLK)
1312 Clock_Ip_Get_EMIOS1_CLK_Frequency, /* EMIOS1_CLK */
1313 #endif
1314 #if defined(CLOCK_IP_HAS_EMIOS2_CLK)
1315 Clock_Ip_Get_EMIOS2_CLK_Frequency, /* EMIOS2_CLK */
1316 #endif
1317 Clock_Ip_Get_ERM0_CLK_Frequency, /* ERM0_CLK */
1318 #if defined(CLOCK_IP_HAS_ERM1_CLK)
1319 Clock_Ip_Get_ERM1_CLK_Frequency, /* ERM1_CLK */
1320 #endif
1321 #if defined(CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK)
1322 Clock_Ip_Get_ETPU_AB_REGISTERS_CLK_Frequency, /* ETPU_AB_REGISTERS_CLK */
1323 #endif
1324 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK)
1325 Clock_Ip_Get_ETPU_CODE_RAM1_CLK_Frequency, /* ETPU_CODE_RAM1_CLK */
1326 #endif
1327 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK)
1328 Clock_Ip_Get_ETPU_CODE_RAM2_CLK_Frequency, /* ETPU_CODE_RAM2_CLK */
1329 #endif
1330 #if defined(CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK)
1331 Clock_Ip_Get_ETPU_RAM_MIRROR_CLK_Frequency, /* ETPU_RAM_MIRROR_CLK */
1332 #endif
1333 #if defined(CLOCK_IP_HAS_ETPU_RAM_SDM_CLK)
1334 Clock_Ip_Get_ETPU_RAM_SDM_CLK_Frequency, /* ETPU_RAM_SDM_CLK */
1335 #endif
1336 #if defined(CLOCK_IP_HAS_FCCU_CLK)
1337 Clock_Ip_Get_FCCU_CLK_Frequency, /* FCCU_CLK */
1338 #endif
1339 #if defined(CLOCK_IP_HAS_FLASH0_CLK)
1340 Clock_Ip_Get_FLASH0_CLK_Frequency, /* FLASH0_CLK */
1341 #endif
1342 #if defined(CLOCK_IP_HAS_FLASH0_ALT_CLK)
1343 Clock_Ip_Get_FLASH0_ALT_CLK_Frequency, /* FLASH0_ALT_CLK */
1344 #endif
1345 #if defined(CLOCK_IP_HAS_FLASH1_CLK)
1346 Clock_Ip_Get_FLASH1_CLK_Frequency, /* FLASH1_CLK */
1347 #endif
1348 #if defined(CLOCK_IP_HAS_FLASH1_ALT_CLK)
1349 Clock_Ip_Get_FLASH1_ALT_CLK_Frequency, /* FLASH1_ALT_CLK */
1350 #endif
1351 Clock_Ip_Get_FLEXCANA_CLK_Frequency, /* FLEXCANA_CLK */
1352 Clock_Ip_Get_FLEXCAN0_CLK_Frequency, /* FLEXCAN0_CLK */
1353 Clock_Ip_Get_FLEXCAN1_CLK_Frequency, /* FLEXCAN1_CLK */
1354 Clock_Ip_Get_FLEXCAN2_CLK_Frequency, /* FLEXCAN2_CLK */
1355 #if defined(CLOCK_IP_HAS_FLEXCANB_CLK)
1356 Clock_Ip_Get_FLEXCANB_CLK_Frequency, /* FLEXCANB_CLK */
1357 #endif
1358 #if defined(CLOCK_IP_HAS_FLEXCAN3_CLK)
1359 Clock_Ip_Get_FLEXCAN3_CLK_Frequency, /* FLEXCAN3_CLK */
1360 #endif
1361 #if defined(CLOCK_IP_HAS_FLEXCAN4_CLK)
1362 Clock_Ip_Get_FLEXCAN4_CLK_Frequency, /* FLEXCAN4_CLK */
1363 #endif
1364 #if defined(CLOCK_IP_HAS_FLEXCAN5_CLK)
1365 Clock_Ip_Get_FLEXCAN5_CLK_Frequency, /* FLEXCAN5_CLK */
1366 #endif
1367 #if defined(CLOCK_IP_HAS_FLEXCAN6_CLK)
1368 Clock_Ip_Get_FLEXCAN6_CLK_Frequency, /* FLEXCAN6_CLK */
1369 #endif
1370 #if defined(CLOCK_IP_HAS_FLEXCAN7_CLK)
1371 Clock_Ip_Get_FLEXCAN7_CLK_Frequency, /* FLEXCAN7_CLK */
1372 #endif
1373 Clock_Ip_Get_FLEXIO0_CLK_Frequency, /* FLEXIO0_CLK */
1374 #if defined(CLOCK_IP_HAS_HSE_MU0_CLK)
1375 Clock_Ip_Get_HSE_MU0_CLK_Frequency, /* HSE_MU0_CLK */
1376 #endif
1377 #if defined(CLOCK_IP_HAS_HSE_MU1_CLK)
1378 Clock_Ip_Get_HSE_MU1_CLK_Frequency, /* HSE_MU1_CLK */
1379 #endif
1380 #if defined(CLOCK_IP_HAS_JDC_CLK)
1381 Clock_Ip_Get_JDC_CLK_Frequency, /* JDC_CLK */
1382 #endif
1383 #if defined(CLOCK_IP_HAS_IGF0_CLK)
1384 Clock_Ip_Get_IGF0_CLK_Frequency, /* IGF0_CLK */
1385 #endif
1386 #if defined(CLOCK_IP_HAS_GMAC0_CLK)
1387 Clock_Ip_Get_GMAC0_CLK_Frequency, /* GMAC0_CLK */
1388 #endif
1389 #if defined(CLOCK_IP_HAS_GMAC1_CLK)
1390 Clock_Ip_Get_GMAC1_CLK_Frequency, /* GMAC1_CLK */
1391 #endif
1392 #if defined(CLOCK_IP_HAS_GMAC0_RX_CLK)
1393 Clock_Ip_Get_GMAC0_RX_CLK_Frequency, /* GMAC0_RX_CLK */
1394 #endif
1395 #if defined(CLOCK_IP_HAS_GMAC0_TX_CLK)
1396 Clock_Ip_Get_GMAC0_TX_CLK_Frequency, /* GMAC0_TX_CLK */
1397 #endif
1398 #if defined(CLOCK_IP_HAS_GMAC_TS_CLK)
1399 Clock_Ip_Get_GMAC_TS_CLK_Frequency, /* GMAC_TS_CLK */
1400 #endif
1401 #if defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK)
1402 Clock_Ip_Get_GMAC0_TX_RMII_CLK_Frequency, /* GMAC0_TX_RMII_CLK */
1403 #endif
1404 #if defined(CLOCK_IP_HAS_GMAC1_RX_CLK)
1405 Clock_Ip_Get_GMAC1_RX_CLK_Frequency, /* GMAC1_RX_CLK */
1406 #endif
1407 #if defined(CLOCK_IP_HAS_GMAC1_TX_CLK)
1408 Clock_Ip_Get_GMAC1_TX_CLK_Frequency, /* GMAC1_TX_CLK */
1409 #endif
1410 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK)
1411 Clock_Ip_Get_GMAC1_RMII_CLK_Frequency, /* GMAC1_RMII_CLK */
1412 #endif
1413 Clock_Ip_Get_INTM_CLK_Frequency, /* INTM_CLK */
1414 Clock_Ip_Get_LCU0_CLK_Frequency, /* LCU0_CLK */
1415 Clock_Ip_Get_LCU1_CLK_Frequency, /* LCU1_CLK */
1416 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK)
1417 Clock_Ip_Get_LFAST_REF_CLK_Frequency, /* LFAST_REF_CLK */
1418 #endif
1419 #if defined(CLOCK_IP_HAS_LPI2C0_CLK)
1420 Clock_Ip_Get_LPI2C0_CLK_Frequency, /* LPI2C0_CLK */
1421 #endif
1422 Clock_Ip_Get_LPI2C1_CLK_Frequency, /* LPI2C1_CLK */
1423 Clock_Ip_Get_LPSPI0_CLK_Frequency, /* LPSPI0_CLK */
1424 Clock_Ip_Get_LPSPI1_CLK_Frequency, /* LPSPI1_CLK */
1425 Clock_Ip_Get_LPSPI2_CLK_Frequency, /* LPSPI2_CLK */
1426 Clock_Ip_Get_LPSPI3_CLK_Frequency, /* LPSPI3_CLK */
1427 #if defined(CLOCK_IP_HAS_LPSPI4_CLK)
1428 Clock_Ip_Get_LPSPI4_CLK_Frequency, /* LPSPI4_CLK */
1429 #endif
1430 #if defined(CLOCK_IP_HAS_LPSPI5_CLK)
1431 Clock_Ip_Get_LPSPI5_CLK_Frequency, /* LPSPI5_CLK */
1432 #endif
1433 Clock_Ip_Get_LPUART0_CLK_Frequency, /* LPUART0_CLK */
1434 Clock_Ip_Get_LPUART1_CLK_Frequency, /* LPUART1_CLK */
1435 Clock_Ip_Get_LPUART2_CLK_Frequency, /* LPUART2_CLK */
1436 Clock_Ip_Get_LPUART3_CLK_Frequency, /* LPUART3_CLK */
1437 #if defined(CLOCK_IP_HAS_LPUART4_CLK)
1438 Clock_Ip_Get_LPUART4_CLK_Frequency, /* LPUART4_CLK */
1439 #endif
1440 #if defined(CLOCK_IP_HAS_LPUART5_CLK)
1441 Clock_Ip_Get_LPUART5_CLK_Frequency, /* LPUART5_CLK */
1442 #endif
1443 #if defined(CLOCK_IP_HAS_LPUART6_CLK)
1444 Clock_Ip_Get_LPUART6_CLK_Frequency, /* LPUART6_CLK */
1445 #endif
1446 #if defined(CLOCK_IP_HAS_LPUART7_CLK)
1447 Clock_Ip_Get_LPUART7_CLK_Frequency, /* LPUART7_CLK */
1448 #endif
1449 #if defined(CLOCK_IP_HAS_LPUART8_CLK)
1450 Clock_Ip_Get_LPUART8_CLK_Frequency, /* LPUART8_CLK */
1451 #endif
1452 #if defined(CLOCK_IP_HAS_LPUART9_CLK)
1453 Clock_Ip_Get_LPUART9_CLK_Frequency, /* LPUART9_CLK */
1454 #endif
1455 #if defined(CLOCK_IP_HAS_LPUART10_CLK)
1456 Clock_Ip_Get_LPUART10_CLK_Frequency, /* LPUART10_CLK */
1457 #endif
1458 #if defined(CLOCK_IP_HAS_LPUART11_CLK)
1459 Clock_Ip_Get_LPUART11_CLK_Frequency, /* LPUART11_CLK */
1460 #endif
1461 #if defined(CLOCK_IP_HAS_LPUART12_CLK)
1462 Clock_Ip_Get_LPUART12_CLK_Frequency, /* LPUART12_CLK */
1463 #endif
1464 #if defined(CLOCK_IP_HAS_LPUART13_CLK)
1465 Clock_Ip_Get_LPUART13_CLK_Frequency, /* LPUART13_CLK */
1466 #endif
1467 #if defined(CLOCK_IP_HAS_LPUART14_CLK)
1468 Clock_Ip_Get_LPUART14_CLK_Frequency, /* LPUART14_CLK */
1469 #endif
1470 #if defined(CLOCK_IP_HAS_LPUART15_CLK)
1471 Clock_Ip_Get_LPUART15_CLK_Frequency, /* LPUART15_CLK */
1472 #endif
1473 #if defined(CLOCK_IP_HAS_LPUART_MSC_CLK)
1474 Clock_Ip_Get_LPUART_MSC_CLK_Frequency, /* LPUART_MSC_CLK */
1475 #endif
1476 Clock_Ip_Get_MSCM_CLK_Frequency, /* MSCM_CLK */
1477 #if defined(CLOCK_IP_HAS_MU2A_CLK)
1478 Clock_Ip_Get_MU2A_CLK_Frequency, /* MU2A_CLK */
1479 #endif
1480 #if defined(CLOCK_IP_HAS_MU2B_CLK)
1481 Clock_Ip_Get_MU2B_CLK_Frequency, /* MU2B_CLK */
1482 #endif
1483 #if defined(CLOCK_IP_HAS_MU3A_CLK)
1484 Clock_Ip_Get_MU3A_CLK_Frequency, /* MU3A_CLK */
1485 #endif
1486 #if defined(CLOCK_IP_HAS_MU3B_CLK)
1487 Clock_Ip_Get_MU3B_CLK_Frequency, /* MU3B_CLK */
1488 #endif
1489 #if defined(CLOCK_IP_HAS_MU4A_CLK)
1490 Clock_Ip_Get_MU4A_CLK_Frequency, /* MU4A_CLK */
1491 #endif
1492 #if defined(CLOCK_IP_HAS_MU4B_CLK)
1493 Clock_Ip_Get_MU4B_CLK_Frequency, /* MU4B_CLK */
1494 #endif
1495 Clock_Ip_Get_PIT0_CLK_Frequency, /* PIT0_CLK */
1496 Clock_Ip_Get_PIT1_CLK_Frequency, /* PIT1_CLK */
1497 #if defined(CLOCK_IP_HAS_PIT2_CLK)
1498 Clock_Ip_Get_PIT2_CLK_Frequency, /* PIT2_CLK */
1499 #endif
1500 #if defined(CLOCK_IP_HAS_PIT3_CLK)
1501 Clock_Ip_Get_PIT3_CLK_Frequency, /* PIT3_CLK */
1502 #endif
1503 #if defined(CLOCK_IP_HAS_PRAMC0_CLK)
1504 Clock_Ip_Get_PRAMC0_CLK_Frequency, /* PRAMC0_CLK */
1505 #endif
1506 #if defined(CLOCK_IP_HAS_PRAMC1_CLK)
1507 Clock_Ip_Get_PRAMC1_CLK_Frequency, /* PRAMC1_CLK */
1508 #endif
1509 #if defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK)
1510 Clock_Ip_Get_QSPI_2XSFIF_CLK_Frequency, /* QSPI_2XSFIF_CLK */
1511 #endif
1512 #if defined(CLOCK_IP_HAS_QSPI0_CLK)
1513 Clock_Ip_Get_QSPI0_CLK_Frequency, /* QSPI0_CLK */
1514 #endif
1515 #if defined(CLOCK_IP_HAS_QSPI0_RAM_CLK)
1516 Clock_Ip_Get_QSPI0_RAM_CLK_Frequency, /* QSPI0_RAM_CLK */
1517 #endif
1518 #if defined(CLOCK_IP_HAS_QSPI0_TX_MEM_CLK)
1519 Clock_Ip_Get_QSPI0_TX_MEM_CLK_Frequency, /* QSPI0_TX_MEM_CLK */
1520 #endif
1521 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK)
1522 Clock_Ip_Get_QSPI_SFCK_CLK_Frequency, /* QSPI_SFCK_CLK */
1523 #endif
1524 Clock_Ip_Get_RTC_CLK_Frequency, /* RTC_CLK */
1525 Clock_Ip_Get_RTC0_CLK_Frequency, /* RTC0_CLK */
1526 #if defined(CLOCK_IP_HAS_SAI0_CLK)
1527 Clock_Ip_Get_SAI0_CLK_Frequency, /* SAI0_CLK */
1528 #endif
1529 #if defined(CLOCK_IP_HAS_SAI1_CLK)
1530 Clock_Ip_Get_SAI1_CLK_Frequency, /* SAI1_CLK */
1531 #endif
1532 #if defined(CLOCK_IP_HAS_SDA_AP_CLK)
1533 Clock_Ip_Get_SDA_AP_CLK_Frequency, /* SDA_AP_CLK */
1534 #endif
1535 #if defined(CLOCK_IP_HAS_SDADC0_CLK)
1536 Clock_Ip_Get_SDADC0_CLK_Frequency, /* SDADC0_CLK */
1537 #endif
1538 #if defined(CLOCK_IP_HAS_SDADC1_CLK)
1539 Clock_Ip_Get_SDADC1_CLK_Frequency, /* SDADC1_CLK */
1540 #endif
1541 #if defined(CLOCK_IP_HAS_SDADC2_CLK)
1542 Clock_Ip_Get_SDADC2_CLK_Frequency, /* SDADC2_CLK */
1543 #endif
1544 #if defined(CLOCK_IP_HAS_SDADC3_CLK)
1545 Clock_Ip_Get_SDADC3_CLK_Frequency, /* SDADC3_CLK */
1546 #endif
1547 #if defined(CLOCK_IP_HAS_SEMA42_CLK)
1548 Clock_Ip_Get_SEMA42_CLK_Frequency, /* SEMA42_CLK */
1549 #endif
1550 #if defined(CLOCK_IP_HAS_SIPI0_CLK)
1551 Clock_Ip_Get_SIPI0_CLK_Frequency, /* SIPI0_CLK */
1552 #endif
1553 Clock_Ip_Get_SIUL2_CLK_Frequency, /* SIUL2_CLK */
1554 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_0_CLK)
1555 Clock_Ip_Get_SIUL2_PDAC0_0_CLK_Frequency, /* SIUL2_PDAC0_0_CLK */
1556 #endif
1557 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_1_CLK)
1558 Clock_Ip_Get_SIUL2_PDAC0_1_CLK_Frequency, /* SIUL2_PDAC0_1_CLK */
1559 #endif
1560 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_0_CLK)
1561 Clock_Ip_Get_SIUL2_PDAC1_0_CLK_Frequency, /* SIUL2_PDAC1_0_CLK */
1562 #endif
1563 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_1_CLK)
1564 Clock_Ip_Get_SIUL2_PDAC1_1_CLK_Frequency, /* SIUL2_PDAC1_1_CLK */
1565 #endif
1566 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_0_CLK)
1567 Clock_Ip_Get_SIUL2_PDAC2_0_CLK_Frequency, /* SIUL2_PDAC2_0_CLK */
1568 #endif
1569 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_1_CLK)
1570 Clock_Ip_Get_SIUL2_PDAC2_1_CLK_Frequency, /* SIUL2_PDAC2_1_CLK */
1571 #endif
1572 Clock_Ip_Get_STCU0_CLK_Frequency, /* STCU0_CLK */
1573 Clock_Ip_Get_STMA_CLK_Frequency, /* STMA_CLK */
1574 Clock_Ip_Get_STM0_CLK_Frequency, /* STM0_CLK */
1575 #if defined(CLOCK_IP_HAS_STMB_CLK)
1576 Clock_Ip_Get_STMB_CLK_Frequency, /* STMB_CLK */
1577 #endif
1578 #if defined(CLOCK_IP_HAS_STM1_CLK)
1579 Clock_Ip_Get_STM1_CLK_Frequency, /* STM1_CLK */
1580 #endif
1581 #if defined(CLOCK_IP_HAS_STMC_CLK)
1582 Clock_Ip_Get_STMC_CLK_Frequency, /* STMC_CLK */
1583 #endif
1584 #if defined(CLOCK_IP_HAS_STM2_CLK)
1585 Clock_Ip_Get_STM2_CLK_Frequency, /* STM2_CLK */
1586 #endif
1587 #if defined(CLOCK_IP_HAS_STMD_CLK)
1588 Clock_Ip_Get_STMD_CLK_Frequency, /* STMD_CLK */
1589 #endif
1590 #if defined(CLOCK_IP_HAS_STM3_CLK)
1591 Clock_Ip_Get_STM3_CLK_Frequency, /* STM3_CLK */
1592 #endif
1593 #if defined(CLOCK_IP_HAS_SWG_CLK)
1594 Clock_Ip_Get_SWG_CLK_Frequency, /* SWG_CLK */
1595 #endif
1596 #if defined(CLOCK_IP_HAS_SWG0_CLK)
1597 Clock_Ip_Get_SWG0_CLK_Frequency, /* SWG0_CLK */
1598 #endif
1599 #if defined(CLOCK_IP_HAS_SWG1_CLK)
1600 Clock_Ip_Get_SWG1_CLK_Frequency, /* SWG1_CLK */
1601 #endif
1602 Clock_Ip_Get_SWT0_CLK_Frequency, /* SWT0_CLK */
1603 #if defined(CLOCK_IP_HAS_SWT1_CLK)
1604 Clock_Ip_Get_SWT1_CLK_Frequency, /* SWT1_CLK */
1605 #endif
1606 #if defined(CLOCK_IP_HAS_SWT2_CLK)
1607 Clock_Ip_Get_SWT2_CLK_Frequency, /* SWT2_CLK */
1608 #endif
1609 #if defined(CLOCK_IP_HAS_SWT3_CLK)
1610 Clock_Ip_Get_SWT3_CLK_Frequency, /* SWT3_CLK */
1611 #endif
1612 #if defined(CLOCK_IP_HAS_TCM_CM7_0_CLK)
1613 Clock_Ip_Get_TCM_CM7_0_CLK_Frequency, /* TCM_CM7_0_CLK */
1614 #endif
1615 #if defined(CLOCK_IP_HAS_TCM_CM7_1_CLK)
1616 Clock_Ip_Get_TCM_CM7_1_CLK_Frequency, /* TCM_CM7_1_CLK */
1617 #endif
1618 Clock_Ip_Get_TEMPSENSE_CLK_Frequency, /* TEMPSENSE_CLK */
1619 Clock_Ip_Get_TRACE_CLK_Frequency, /* TRACE_CLK */
1620 Clock_Ip_Get_TRGMUX0_CLK_Frequency, /* TRGMUX0_CLK */
1621 #if defined(CLOCK_IP_HAS_TRGMUX1_CLK)
1622 Clock_Ip_Get_TRGMUX1_CLK_Frequency, /* TRGMUX1_CLK */
1623 #endif
1624 #if defined(CLOCK_IP_HAS_TSENSE0_CLK)
1625 Clock_Ip_Get_TSENSE0_CLK_Frequency, /* TSENSE0_CLK */
1626 #endif
1627 #if defined(CLOCK_IP_HAS_USDHC_CLK)
1628 Clock_Ip_Get_USDHC_CLK_Frequency, /* USDHC_CLK */
1629 #endif
1630 Clock_Ip_Get_WKPU0_CLK_Frequency, /* WKPU0_CLK */
1631 #if defined(CLOCK_IP_HAS_XRDC_CLK)
1632 Clock_Ip_Get_XRDC_CLK_Frequency, /* XRDC_CLK */
1633 #endif
1634 };
1635 /* Clock stop constant section data */
1636 #define MCU_STOP_SEC_CONST_UNSPECIFIED
1637 #include "Mcu_MemMap.h"
1638
1639
1640 /* Clock start constant section data */
1641 #define MCU_START_SEC_CONST_32
1642 #include "Mcu_MemMap.h"
1643
1644 static const uint32 Clock_Ip_au32EnableDivider[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED};
1645 static const uint32 Clock_Ip_u32EnableGate[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED};
1646 #ifdef CLOCK_IP_FIRC_DIV_SEL_HSEb_CONFIG_REG_GPR
1647 static const uint32 Clock_Ip_apfTableDividerValue[CLOCK_IP_FIRC_DIV_SEL_VALS_NO] =
1648 {
1649 2U, /* Divider value for 0 hardware value */
1650 2U, /* Divider value for 1 hardware value */
1651 16U, /* Divider value for 2 hardware value */
1652 1U, /* Divider value for 3 hardware value */
1653 };
1654 #endif
1655
1656 /* Clock stop constant section data */
1657 #define MCU_STOP_SEC_CONST_32
1658 #include "Mcu_MemMap.h"
1659 /*==================================================================================================
1660 LOCAL VARIABLES
1661 ==================================================================================================*/
1662
1663
1664
1665 /* Clock start initialized section data */
1666 #define MCU_START_SEC_VAR_INIT_UNSPECIFIED
1667 #include "Mcu_MemMap.h"
1668
1669 static extSignalFreq Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_EXT_SIGNALS_NO] = {
1670 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK)
1671 {EMAC_MII_RX_CLK,0U},
1672 #elif defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK)
1673 {GMAC0_MII_RX_CLK,0U},
1674 #else
1675 {RESERVED_CLK,CLOCK_IP_EXT_SIGNALS_NO},
1676 #endif
1677 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK)
1678 {EMAC_MII_RMII_TX_CLK,0U},
1679 #elif defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK)
1680 {GMAC0_MII_RMII_TX_CLK,0U},
1681 #else
1682 {RESERVED_CLK,CLOCK_IP_EXT_SIGNALS_NO},
1683 #endif
1684 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK)
1685 {LFAST_REF_EXT_CLK,0U},
1686 #else
1687 {RESERVED_CLK,CLOCK_IP_EXT_SIGNALS_NO},
1688 #endif
1689 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK)
1690 {SWG_PAD_CLK,0U},
1691 #else
1692 {RESERVED_CLK,CLOCK_IP_EXT_SIGNALS_NO},
1693 #endif
1694 };
1695
1696 /* Clock stop initialized section data */
1697 #define MCU_STOP_SEC_VAR_INIT_UNSPECIFIED
1698 #include "Mcu_MemMap.h"
1699
1700
1701
1702
1703
1704 /* Clock stop constant section data */
1705 #define MCU_START_SEC_VAR_INIT_32
1706 #include "Mcu_MemMap.h"
1707
1708 /* External oscillators */
1709 static uint32 Clock_Ip_u32fxosc = CLOCK_IP_DEFAULT_FXOSC_FREQUENCY;
1710 #if defined(CLOCK_IP_HAS_SXOSC_CLK)
1711 static uint32 Clock_Ip_u32sxosc = CLOCK_IP_DEFAULT_SXOSC_FREQUENCY;
1712 #endif
1713 static uint32 Clock_Ip_u32PLL_CLKFreq = CLOCK_IP_PLL_CLK_FREQ;
1714 static uint32 Clock_Ip_u32PLL_CLKChecksum = CLOCK_IP_PLL_CLK_CHECKSUM;
1715 #if defined(CLOCK_IP_HAS_PLLAUX_CLK)
1716 static uint32 Clock_Ip_u32PLLAUX_CLKFreq = CLOCK_IP_PLLAUX_CLK_FREQ;
1717 static uint32 Clock_Ip_u32PLLAUX_CLKChecksum = CLOCK_IP_PLLAUX_CLK_CHECKSUM;
1718 #endif
1719
1720 /* Clock stop initialized section data */
1721 #define MCU_STOP_SEC_VAR_INIT_32
1722 #include "Mcu_MemMap.h"
1723
1724 /*==================================================================================================
1725 GLOBAL CONSTANTS
1726 ==================================================================================================*/
1727
1728 /*==================================================================================================
1729 GLOBAL VARIABLES
1730 ==================================================================================================*/
1731
1732 /*==================================================================================================
1733 LOCAL FUNCTIONS
1734 ==================================================================================================*/
1735 /* Clock start section code */
1736 #define MCU_START_SEC_CODE
1737 #include "Mcu_MemMap.h"
1738
1739
1740 /* Return zero frequency */
Clock_Ip_Get_Zero_Frequency(void)1741 static uint32 Clock_Ip_Get_Zero_Frequency(void)
1742 {
1743 return 0U;
1744 }
1745 /* Return FIRC_CLK frequency */
Clock_Ip_Get_FIRC_CLK_Frequency(void)1746 static uint32 Clock_Ip_Get_FIRC_CLK_Frequency(void) {
1747 uint32 Frequency = CLOCK_IP_FIRC_FREQUENCY;
1748 #ifdef CLOCK_IP_FIRC_DIV_SEL_HSEb_CONFIG_REG_GPR
1749 uint32 DividerValue = Clock_Ip_apfTableDividerValue[(IP_CONFIGURATION_GPR->CONFIG_REG_GPR & CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_MASK) >> CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_SHIFT];
1750 Frequency /= DividerValue;
1751 #endif
1752 return Frequency;
1753 }
1754 /* Return FIRC_STANDBY_CLK frequency */
Clock_Ip_Get_FIRC_STANDBY_CLK_Frequency(void)1755 static uint32 Clock_Ip_Get_FIRC_STANDBY_CLK_Frequency(void) {
1756 uint32 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
1757 Frequency &= Clock_Ip_u32EnableGate[((IP_FIRC->STDBY_ENABLE & FIRC_STDBY_ENABLE_STDBY_EN_MASK) >> FIRC_STDBY_ENABLE_STDBY_EN_SHIFT)];
1758 return Frequency;
1759 }
1760 /* Return SIRC_CLK frequency */
Clock_Ip_Get_SIRC_CLK_Frequency(void)1761 static uint32 Clock_Ip_Get_SIRC_CLK_Frequency(void) {
1762 return CLOCK_IP_SIRC_FREQUENCY;
1763 }
1764 /* Return SIRC_STANDBY_CLK frequency */
Clock_Ip_Get_SIRC_STANDBY_CLK_Frequency(void)1765 static uint32 Clock_Ip_Get_SIRC_STANDBY_CLK_Frequency(void) {
1766 uint32 Frequency = Clock_Ip_Get_SIRC_CLK_Frequency();
1767 Frequency &= Clock_Ip_u32EnableGate[((IP_SIRC->MISCELLANEOUS_IN & SIRC_MISCELLANEOUS_IN_STANDBY_ENABLE_MASK) >> SIRC_MISCELLANEOUS_IN_STANDBY_ENABLE_SHIFT)];
1768 return Frequency;
1769 }
1770 /* Return FXOSC_CLK frequency */
Clock_Ip_Get_FXOSC_CLK_Frequency(void)1771 static uint32 Clock_Ip_Get_FXOSC_CLK_Frequency(void) {
1772 uint32 Frequency = Clock_Ip_u32fxosc;
1773
1774 if (((IP_FXOSC->STAT & FXOSC_STAT_OSC_STAT_MASK) >> FXOSC_STAT_OSC_STAT_SHIFT) == 0U)
1775 {
1776 Frequency = 0U;
1777 }
1778 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK53_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK53_SHIFT];
1779 return Frequency;
1780 }
1781 #if defined(CLOCK_IP_HAS_SXOSC_CLK)
1782 /* Return SXOSC_CLK frequency */
Clock_Ip_Get_SXOSC_CLK_Frequency(void)1783 static uint32 Clock_Ip_Get_SXOSC_CLK_Frequency(void) {
1784 uint32 Frequency = Clock_Ip_u32sxosc;
1785
1786 if (((IP_SXOSC->SXOSC_STAT & SXOSC_SXOSC_STAT_OSC_STAT_MASK) >> SXOSC_SXOSC_STAT_OSC_STAT_SHIFT) == 0U)
1787 {
1788 Frequency = 0U;
1789 }
1790 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK51_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK51_SHIFT];
1791 return Frequency;
1792 }
1793 #endif
1794 /* Return PLL_CLK frequency */
Clock_Ip_Get_PLL_CLK_Frequency(void)1795 static uint32 Clock_Ip_Get_PLL_CLK_Frequency(void) {
1796 uint32 PLLDVBuffer = IP_PLL->PLLDV;
1797 uint32 PLLFDBuffer = IP_PLL->PLLFD;
1798
1799 if (Clock_Ip_u32PLL_CLKChecksum != (PLLDVBuffer ^ PLLFDBuffer))
1800 {
1801 Clock_Ip_u32PLL_CLKChecksum = (PLLDVBuffer ^ PLLFDBuffer);
1802 Clock_Ip_u32PLL_CLKFreq = Clock_Ip_PLL_VCO(IP_PLL);
1803 }
1804 return (((IP_PLL->PLLSR & PLL_PLLSR_LOCK_MASK) >> PLL_PLLSR_LOCK_SHIFT) != 0U) ? Clock_Ip_u32PLL_CLKFreq : 0U;
1805 }
1806 #if defined(CLOCK_IP_HAS_PLLAUX_CLK)
1807 /* Return PLLAUX_CLK frequency */
Clock_Ip_Get_PLLAUX_CLK_Frequency(void)1808 static uint32 Clock_Ip_Get_PLLAUX_CLK_Frequency(void) {
1809 if (Clock_Ip_u32PLLAUX_CLKChecksum != (IP_PLL_AUX->PLLDV))
1810 {
1811 Clock_Ip_u32PLLAUX_CLKChecksum = (IP_PLL_AUX->PLLDV);
1812 Clock_Ip_u32PLLAUX_CLKFreq = Clock_Ip_PLL_VCO(IP_PLL_AUX);
1813 }
1814 return (((IP_PLL_AUX->PLLSR & PLL_PLLSR_LOCK_MASK) >> PLL_PLLSR_LOCK_SHIFT) != 0U) ? Clock_Ip_u32PLLAUX_CLKFreq : 0U;
1815 }
1816 #endif
1817 /* Return PLL_POSTDIV_CLK frequency */
Clock_Ip_Get_PLL_POSTDIV_CLK_Frequency(void)1818 static uint32 Clock_Ip_Get_PLL_POSTDIV_CLK_Frequency(void) {
1819 uint32 Frequency = Clock_Ip_Get_PLL_CLK_Frequency();
1820 uint32 DividerValue = (IP_PLL->PLLDV & PLL_PLLDV_ODIV2_MASK) >> PLL_PLLDV_ODIV2_SHIFT;
1821 if ((uint32)0U != DividerValue)
1822 {
1823 Frequency /= DividerValue;
1824 }
1825 else
1826 {
1827 Frequency = (uint32)0U;
1828 }
1829 return Frequency;
1830 }
1831 #if defined(CLOCK_IP_HAS_PLLAUX_POSTDIV_CLK)
1832 /* Return PLLAUX_POSTDIV_CLK frequency */
Clock_Ip_Get_PLLAUX_POSTDIV_CLK_Frequency(void)1833 static uint32 Clock_Ip_Get_PLLAUX_POSTDIV_CLK_Frequency(void) {
1834 uint32 Frequency = Clock_Ip_Get_PLLAUX_CLK_Frequency();
1835 uint32 DividerValue = (IP_PLL_AUX->PLLDV & PLL_PLLDV_ODIV2_MASK) >> PLL_PLLDV_ODIV2_SHIFT;
1836 if ((uint32)0U != DividerValue)
1837 {
1838 Frequency /= DividerValue;
1839 }
1840 else
1841 {
1842 Frequency = (uint32)0U;
1843 }
1844 return Frequency;
1845 }
1846 #endif
1847 /* Return PLL_PHI0 frequency */
Clock_Ip_Get_PLL_PHI0_Frequency(void)1848 static uint32 Clock_Ip_Get_PLL_PHI0_Frequency(void) {
1849 uint32 Frequency = Clock_Ip_Get_PLL_POSTDIV_CLK_Frequency();
1850 Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1851 Frequency /= (((IP_PLL->PLLODIV[0U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1852 return Frequency;
1853 }
1854 /* Return PLL_PHI1 frequency */
Clock_Ip_Get_PLL_PHI1_Frequency(void)1855 static uint32 Clock_Ip_Get_PLL_PHI1_Frequency(void) {
1856 uint32 Frequency = Clock_Ip_Get_PLL_POSTDIV_CLK_Frequency();
1857 Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1858 Frequency /= (((IP_PLL->PLLODIV[1U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1859 return Frequency;
1860 }
1861 #if defined(CLOCK_IP_HAS_PLLAUX_PHI0_CLK)
1862 /* Return PLLAUX_PHI0 frequency */
Clock_Ip_Get_PLLAUX_PHI0_Frequency(void)1863 static uint32 Clock_Ip_Get_PLLAUX_PHI0_Frequency(void) {
1864 uint32 Frequency = Clock_Ip_Get_PLLAUX_POSTDIV_CLK_Frequency();
1865 Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1866 Frequency /= (((IP_PLL_AUX->PLLODIV[0U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1867 return Frequency;
1868 }
1869 #endif
1870 #if defined(CLOCK_IP_HAS_PLLAUX_PHI1_CLK)
1871 /* Return PLLAUX_PHI1 frequency */
Clock_Ip_Get_PLLAUX_PHI1_Frequency(void)1872 static uint32 Clock_Ip_Get_PLLAUX_PHI1_Frequency(void) {
1873 uint32 Frequency = Clock_Ip_Get_PLLAUX_POSTDIV_CLK_Frequency();
1874 Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1875 Frequency /= (((IP_PLL_AUX->PLLODIV[1U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1876 return Frequency;
1877 }
1878 #endif
1879 #if defined(CLOCK_IP_HAS_PLLAUX_PHI2_CLK)
1880 /* Return PLLAUX_PHI2 frequency */
Clock_Ip_Get_PLLAUX_PHI2_Frequency(void)1881 static uint32 Clock_Ip_Get_PLLAUX_PHI2_Frequency(void) {
1882 uint32 Frequency = Clock_Ip_Get_PLLAUX_POSTDIV_CLK_Frequency();
1883 Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[2U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1884 Frequency /= (((IP_PLL_AUX->PLLODIV[2U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1885 return Frequency;
1886 }
1887 #endif
1888 #if defined(CLOCK_IP_HAS_EMAC_MII_RX_CLK)
1889 /* Return emac_mii_rx frequency */
Clock_Ip_Get_emac_mii_rx_Frequency(void)1890 static uint32 Clock_Ip_Get_emac_mii_rx_Frequency(void) {
1891 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_EMAC_MII_RX_CLK_INDEX_ENTRY].Frequency;
1892 }
1893 #endif
1894 #if defined(CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK)
1895 /* Return emac_mii_rmii_tx frequency */
Clock_Ip_Get_emac_mii_rmii_tx_Frequency(void)1896 static uint32 Clock_Ip_Get_emac_mii_rmii_tx_Frequency(void) {
1897 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_EMAC_MII_RMII_TX_CLK_INDEX_ENTRY].Frequency;
1898 }
1899 #endif
1900 #if defined(CLOCK_IP_HAS_GMAC0_MII_RX_CLK)
1901 /* Return gmac0_mii_rx frequency */
Clock_Ip_Get_gmac0_mii_rx_Frequency(void)1902 static uint32 Clock_Ip_Get_gmac0_mii_rx_Frequency(void) {
1903 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_GMAC0_MII_RX_CLK_INDEX_ENTRY].Frequency;
1904 }
1905 #endif
1906 #if defined(CLOCK_IP_HAS_GMAC0_MII_RMII_TX_CLK)
1907 /* Return gmac0_mii_rmii_tx frequency */
Clock_Ip_Get_gmac0_mii_rmii_tx_Frequency(void)1908 static uint32 Clock_Ip_Get_gmac0_mii_rmii_tx_Frequency(void) {
1909 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_GMAC0_MII_RMII_TX_CLK_INDEX_ENTRY].Frequency;
1910 }
1911 #endif
1912 #if defined(CLOCK_IP_HAS_LFAST_REF_EXT_CLK)
1913 /* Return lfast_ext_ref frequency */
Clock_Ip_Get_lfast_ext_ref_Frequency(void)1914 static uint32 Clock_Ip_Get_lfast_ext_ref_Frequency(void) {
1915 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_LFAST_REF_EXT_CLK_INDEX_ENTRY].Frequency;
1916 }
1917 #endif
1918 #if defined(CLOCK_IP_HAS_SWG_PAD_CLK)
1919 /* Return swg_pad frequency */
Clock_Ip_Get_swg_pad_Frequency(void)1920 static uint32 Clock_Ip_Get_swg_pad_Frequency(void) {
1921 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_SWG_PAD_CLK_INDEX_ENTRY].Frequency;
1922 }
1923 #endif
1924 /* Return SCS_CLK frequency */
Clock_Ip_Get_SCS_CLK_Frequency(void)1925 static uint32 Clock_Ip_Get_SCS_CLK_Frequency(void) {
1926
1927 uint32 Frequency;
1928 if (((IP_MC_CGM->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT) != (uint32)8U)
1929 {
1930 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
1931 }
1932 else
1933 {
1934 Frequency = Clock_Ip_Get_PLL_PHI0_Frequency();
1935 }
1936
1937 return Frequency; /* Selector value */
1938 }
1939 /* Return CORE_CLK frequency */
Clock_Ip_Get_CORE_CLK_Frequency(void)1940 static uint32 Clock_Ip_Get_CORE_CLK_Frequency(void) {
1941 uint32 Frequency = Clock_Ip_Get_SCS_CLK_Frequency();
1942 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DE_MASK) >> MC_CGM_MUX_0_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1943 Frequency /= (((IP_MC_CGM->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1944 return Frequency;
1945 }
1946 /* Return AIPS_PLAT_CLK frequency */
Clock_Ip_Get_AIPS_PLAT_CLK_Frequency(void)1947 static uint32 Clock_Ip_Get_AIPS_PLAT_CLK_Frequency(void) {
1948 uint32 Frequency = Clock_Ip_Get_SCS_CLK_Frequency();
1949 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_1 & MC_CGM_MUX_0_DC_1_DE_MASK) >> MC_CGM_MUX_0_DC_1_DE_SHIFT)]; /* Divider enable/disable */
1950 Frequency /= (((IP_MC_CGM->MUX_0_DC_1 & MC_CGM_MUX_0_DC_1_DIV_MASK) >> MC_CGM_MUX_0_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
1951 return Frequency;
1952 }
1953 /* Return AIPS_SLOW_CLK frequency */
Clock_Ip_Get_AIPS_SLOW_CLK_Frequency(void)1954 static uint32 Clock_Ip_Get_AIPS_SLOW_CLK_Frequency(void) {
1955 uint32 Frequency = Clock_Ip_Get_SCS_CLK_Frequency();
1956 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_2 & MC_CGM_MUX_0_DC_2_DE_MASK) >> MC_CGM_MUX_0_DC_2_DE_SHIFT)]; /* Divider enable/disable */
1957 Frequency /= (((IP_MC_CGM->MUX_0_DC_2 & MC_CGM_MUX_0_DC_2_DIV_MASK) >> MC_CGM_MUX_0_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
1958 return Frequency;
1959 }
1960 /* Return HSE_CLK frequency */
Clock_Ip_Get_HSE_CLK_Frequency(void)1961 static uint32 Clock_Ip_Get_HSE_CLK_Frequency(void) {
1962 uint32 Frequency = Clock_Ip_Get_SCS_CLK_Frequency();
1963 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_3 & MC_CGM_MUX_0_DC_3_DE_MASK) >> MC_CGM_MUX_0_DC_3_DE_SHIFT)]; /* Divider enable/disable */
1964 Frequency /= (((IP_MC_CGM->MUX_0_DC_3 & MC_CGM_MUX_0_DC_3_DIV_MASK) >> MC_CGM_MUX_0_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
1965 return Frequency;
1966 }
1967 /* Return DCM_CLK frequency */
Clock_Ip_Get_DCM_CLK_Frequency(void)1968 static uint32 Clock_Ip_Get_DCM_CLK_Frequency(void) {
1969 uint32 Frequency = Clock_Ip_Get_SCS_CLK_Frequency();
1970 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_4 & MC_CGM_MUX_0_DC_4_DE_MASK) >> MC_CGM_MUX_0_DC_4_DE_SHIFT)]; /* Divider enable/disable */
1971 Frequency /= (((IP_MC_CGM->MUX_0_DC_4 & MC_CGM_MUX_0_DC_4_DIV_MASK) >> MC_CGM_MUX_0_DC_4_DIV_SHIFT) + 1U); /* Apply divider value */
1972 return Frequency;
1973 }
1974 #if defined(CLOCK_IP_HAS_LBIST_CLK)
1975 /* Return LBIST_CLK frequency */
Clock_Ip_Get_LBIST_CLK_Frequency(void)1976 static uint32 Clock_Ip_Get_LBIST_CLK_Frequency(void) {
1977 uint32 Frequency = Clock_Ip_Get_SCS_CLK_Frequency();
1978 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_5 & MC_CGM_MUX_0_DC_5_DE_MASK) >> MC_CGM_MUX_0_DC_5_DE_SHIFT)]; /* Divider enable/disable */
1979 Frequency /= (((IP_MC_CGM->MUX_0_DC_5 & MC_CGM_MUX_0_DC_5_DIV_MASK) >> MC_CGM_MUX_0_DC_5_DIV_SHIFT) + 1U); /* Apply divider value */
1980 return Frequency;
1981 }
1982 #endif
1983 #if defined(CLOCK_IP_HAS_QSPI_MEM_CLK)
1984 /* Return QSPI_MEM_CLK frequency */
Clock_Ip_Get_QSPI_MEM_CLK_Frequency(void)1985 static uint32 Clock_Ip_Get_QSPI_MEM_CLK_Frequency(void) {
1986 uint32 Frequency = Clock_Ip_Get_SCS_CLK_Frequency();
1987 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_6 & MC_CGM_MUX_0_DC_6_DE_MASK) >> MC_CGM_MUX_0_DC_6_DE_SHIFT)]; /* Divider enable/disable */
1988 Frequency /= (((IP_MC_CGM->MUX_0_DC_6 & MC_CGM_MUX_0_DC_6_DIV_MASK) >> MC_CGM_MUX_0_DC_6_DIV_SHIFT) + 1U); /* Apply divider value */
1989 return Frequency;
1990 }
1991 #endif
1992 #if defined(CLOCK_IP_HAS_CM7_CORE_CLK)
1993 /* Return CM7_CORE_CLK frequency */
Clock_Ip_Get_CM7_CORE_CLK_Frequency(void)1994 static uint32 Clock_Ip_Get_CM7_CORE_CLK_Frequency(void) {
1995 uint32 Frequency = Clock_Ip_Get_SCS_CLK_Frequency();
1996 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_7 & MC_CGM_MUX_0_DC_7_DE_MASK) >> MC_CGM_MUX_0_DC_7_DE_SHIFT)]; /* Divider enable/disable */
1997 Frequency /= (((IP_MC_CGM->MUX_0_DC_7 & MC_CGM_MUX_0_DC_7_DIV_MASK) >> MC_CGM_MUX_0_DC_7_DIV_SHIFT) + 1U); /* Apply divider value */
1998 return Frequency;
1999 }
2000 #endif
2001 /* Return CLKOUT_RUN_CLK frequency */
Clock_Ip_Get_CLKOUT_RUN_CLK_Frequency(void)2002 static uint32 Clock_Ip_Get_CLKOUT_RUN_CLK_Frequency(void) {
2003 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)](); /* Selector value */
2004 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> MC_CGM_MUX_6_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2005 Frequency /= (((IP_MC_CGM->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2006 return Frequency;
2007 }
2008 /* Return ADC0_CLK frequency */
Clock_Ip_Get_ADC0_CLK_Frequency(void)2009 static uint32 Clock_Ip_Get_ADC0_CLK_Frequency(void) {
2010 #if defined(CLOCK_IP_DERIVATIVE_006)
2011 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2012 #else
2013 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2014 #endif
2015 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK40_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK40_SHIFT];
2016 return Frequency;
2017 }
2018 /* Return ADC1_CLK frequency */
Clock_Ip_Get_ADC1_CLK_Frequency(void)2019 static uint32 Clock_Ip_Get_ADC1_CLK_Frequency(void) {
2020 #if defined(CLOCK_IP_DERIVATIVE_006)
2021 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2022 #else
2023 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2024 #endif
2025 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK41_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK41_SHIFT];
2026 return Frequency;
2027 }
2028 #if defined(CLOCK_IP_HAS_ADC2_CLK)
2029 /* Return ADC2_CLK frequency */
Clock_Ip_Get_ADC2_CLK_Frequency(void)2030 static uint32 Clock_Ip_Get_ADC2_CLK_Frequency(void) {
2031 #if defined(CLOCK_IP_DERIVATIVE_006)
2032 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2033 #else
2034 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2035 #endif
2036 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK42_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK42_SHIFT];
2037 return Frequency;
2038 }
2039 #endif
2040 #if defined(CLOCK_IP_HAS_ADC3_CLK)
2041 /* Return ADC3_CLK frequency */
Clock_Ip_Get_ADC3_CLK_Frequency(void)2042 static uint32 Clock_Ip_Get_ADC3_CLK_Frequency(void) {
2043 #if defined(CLOCK_IP_DERIVATIVE_006)
2044 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2045 #else
2046 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2047 #endif
2048 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK43_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK43_SHIFT];
2049 return Frequency;
2050 }
2051 #endif
2052 #if defined(CLOCK_IP_HAS_ADC4_CLK)
2053 /* Return ADC4_CLK frequency */
Clock_Ip_Get_ADC4_CLK_Frequency(void)2054 static uint32 Clock_Ip_Get_ADC4_CLK_Frequency(void) {
2055 #if defined(CLOCK_IP_DERIVATIVE_006)
2056 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2057 #else
2058 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2059 #endif
2060 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK52_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK52_SHIFT];
2061 return Frequency;
2062 }
2063 #endif
2064 #if defined(CLOCK_IP_HAS_ADC5_CLK)
2065 /* Return ADC5_CLK frequency */
Clock_Ip_Get_ADC5_CLK_Frequency(void)2066 static uint32 Clock_Ip_Get_ADC5_CLK_Frequency(void) {
2067 #if defined(CLOCK_IP_DERIVATIVE_006)
2068 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2069 #else
2070 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2071 #endif
2072 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK53_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK53_SHIFT];
2073 return Frequency;
2074 }
2075 #endif
2076 #if defined(CLOCK_IP_HAS_ADC6_CLK)
2077 /* Return ADC6_CLK frequency */
Clock_Ip_Get_ADC6_CLK_Frequency(void)2078 static uint32 Clock_Ip_Get_ADC6_CLK_Frequency(void) {
2079 #if defined(CLOCK_IP_DERIVATIVE_006)
2080 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2081 #else
2082 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2083 #endif
2084 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK54_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK54_SHIFT];
2085 return Frequency;
2086 }
2087 #endif
2088 #if defined(CLOCK_IP_HAS_ADCBIST_CLK)
2089 /* Return ADCBIST_CLK frequency */
Clock_Ip_Get_ADCBIST_CLK_Frequency(void)2090 static uint32 Clock_Ip_Get_ADCBIST_CLK_Frequency(void) {
2091 #if defined(CLOCK_IP_DERIVATIVE_006)
2092 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2093 #else
2094 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2095 #endif
2096 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB2_STAT & MC_ME_PRTN3_COFB2_STAT_BLOCK65_MASK) >> MC_ME_PRTN3_COFB2_STAT_BLOCK65_SHIFT];
2097 return Frequency;
2098 }
2099 #endif
2100
2101 #if defined(CLOCK_IP_HAS_AXBS_CLK)
2102 /* Return AXBS_CLK frequency */
Clock_Ip_Get_AXBS_CLK_Frequency(void)2103 static uint32 Clock_Ip_Get_AXBS_CLK_Frequency(void) {
2104 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2105 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK0_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK0_SHIFT];
2106 return Frequency;
2107 }
2108 #endif
2109 #if defined(CLOCK_IP_HAS_AXBS0_CLK)
2110 /* Return AXBS0_CLK frequency */
Clock_Ip_Get_AXBS0_CLK_Frequency(void)2111 static uint32 Clock_Ip_Get_AXBS0_CLK_Frequency(void) {
2112 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2113 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK1_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK1_SHIFT];
2114 return Frequency;
2115 }
2116 #endif
2117 #if defined(CLOCK_IP_HAS_AXBS1_CLK)
2118 /* Return AXBS1_CLK frequency */
Clock_Ip_Get_AXBS1_CLK_Frequency(void)2119 static uint32 Clock_Ip_Get_AXBS1_CLK_Frequency(void) {
2120 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2121 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK2_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK2_SHIFT];
2122 return Frequency;
2123 }
2124 #endif
2125 /* Return BCTU0_CLK frequency */
Clock_Ip_Get_BCTU0_CLK_Frequency(void)2126 static uint32 Clock_Ip_Get_BCTU0_CLK_Frequency(void) {
2127 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2128 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK33_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK33_SHIFT];
2129 return Frequency;
2130 }
2131 #if defined(CLOCK_IP_HAS_BCTU1_CLK)
2132 /* Return BCTU1_CLK frequency */
Clock_Ip_Get_BCTU1_CLK_Frequency(void)2133 static uint32 Clock_Ip_Get_BCTU1_CLK_Frequency(void) {
2134 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2135 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK49_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK49_SHIFT];
2136 return Frequency;
2137 }
2138 #endif
2139 /* Return CLKOUT_STANDBY_CLK frequency */
Clock_Ip_Get_CLKOUT_STANDBY_CLK_Frequency(void)2140 static uint32 Clock_Ip_Get_CLKOUT_STANDBY_CLK_Frequency(void) {
2141 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)](); /* Selector value */
2142 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> MC_CGM_MUX_5_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2143 Frequency /= (((IP_MC_CGM->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2144 return Frequency;
2145 }
2146 /* Return CMP0_CLK frequency */
Clock_Ip_Get_CMP0_CLK_Frequency(void)2147 static uint32 Clock_Ip_Get_CMP0_CLK_Frequency(void) {
2148 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
2149 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK92_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK92_SHIFT];
2150 return Frequency;
2151 }
2152 #if defined(CLOCK_IP_HAS_CMP1_CLK)
2153 /* Return CMP1_CLK frequency */
Clock_Ip_Get_CMP1_CLK_Frequency(void)2154 static uint32 Clock_Ip_Get_CMP1_CLK_Frequency(void) {
2155 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
2156 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK93_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK93_SHIFT];
2157 return Frequency;
2158 }
2159 #endif
2160 #if defined(CLOCK_IP_HAS_CMP2_CLK)
2161 /* Return CMP2_CLK frequency */
Clock_Ip_Get_CMP2_CLK_Frequency(void)2162 static uint32 Clock_Ip_Get_CMP2_CLK_Frequency(void) {
2163 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
2164 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK58_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK58_SHIFT];
2165 return Frequency;
2166 }
2167 #endif
2168
2169 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM0_CLK)
2170 /* Return COOLFLUX_D_RAM0_CLK frequency */
Clock_Ip_Get_COOLFLUX_D_RAM0_CLK_Frequency(void)2171 static uint32 Clock_Ip_Get_COOLFLUX_D_RAM0_CLK_Frequency(void) {
2172 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2173 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK58_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK58_SHIFT];
2174 return Frequency;
2175 }
2176 #endif
2177
2178 #if defined(CLOCK_IP_HAS_COOLFLUX_D_RAM1_CLK)
2179 /* Return COOLFLUX_D_RAM1_CLK frequency */
Clock_Ip_Get_COOLFLUX_D_RAM1_CLK_Frequency(void)2180 static uint32 Clock_Ip_Get_COOLFLUX_D_RAM1_CLK_Frequency(void) {
2181 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2182 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK59_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK59_SHIFT];
2183 return Frequency;
2184 }
2185 #endif
2186
2187 #if defined(CLOCK_IP_HAS_COOLFLUX_DSP16L_CLK)
2188 /* Return COOLFLUX_DSP16L_CLK frequency */
Clock_Ip_Get_COOLFLUX_DSP16L_CLK_Frequency(void)2189 static uint32 Clock_Ip_Get_COOLFLUX_DSP16L_CLK_Frequency(void) {
2190 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2191 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK55_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK55_SHIFT];
2192 return Frequency;
2193 }
2194 #endif
2195
2196 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM0_CLK)
2197 /* Return COOLFLUX_I_RAM0_CLK frequency */
Clock_Ip_Get_COOLFLUX_I_RAM0_CLK_Frequency(void)2198 static uint32 Clock_Ip_Get_COOLFLUX_I_RAM0_CLK_Frequency(void) {
2199 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2200 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK56_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK56_SHIFT];
2201 return Frequency;
2202 }
2203 #endif
2204
2205 #if defined(CLOCK_IP_HAS_COOLFLUX_I_RAM1_CLK)
2206 /* Return COOLFLUX_I_RAM1_CLK frequency */
Clock_Ip_Get_COOLFLUX_I_RAM1_CLK_Frequency(void)2207 static uint32 Clock_Ip_Get_COOLFLUX_I_RAM1_CLK_Frequency(void) {
2208 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2209 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK57_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK57_SHIFT];
2210 return Frequency;
2211 }
2212 #endif
2213
2214 /* Return CRC0_CLK frequency */
Clock_Ip_Get_CRC0_CLK_Frequency(void)2215 static uint32 Clock_Ip_Get_CRC0_CLK_Frequency(void) {
2216 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2217 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB3_STAT & MC_ME_PRTN1_COFB3_STAT_BLOCK96_MASK) >> MC_ME_PRTN1_COFB3_STAT_BLOCK96_SHIFT];
2218 return Frequency;
2219 }
2220 /* Return DMAMUX0_CLK frequency */
Clock_Ip_Get_DMAMUX0_CLK_Frequency(void)2221 static uint32 Clock_Ip_Get_DMAMUX0_CLK_Frequency(void) {
2222 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2223 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK32_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK32_SHIFT];
2224 return Frequency;
2225 }
2226 /* Return DMAMUX1_CLK frequency */
Clock_Ip_Get_DMAMUX1_CLK_Frequency(void)2227 static uint32 Clock_Ip_Get_DMAMUX1_CLK_Frequency(void) {
2228 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2229 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK33_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK33_SHIFT];
2230 return Frequency;
2231 }
2232
2233 #if defined(CLOCK_IP_HAS_DMAMUX2_CLK)
2234 /* Return DMAMUX2_CLK frequency */
Clock_Ip_Get_DMAMUX2_CLK_Frequency(void)2235 static uint32 Clock_Ip_Get_DMAMUX2_CLK_Frequency(void) {
2236 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2237 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK40_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK40_SHIFT];
2238 return Frequency;
2239 }
2240 #endif
2241
2242 #if defined(CLOCK_IP_HAS_DMAMUX3_CLK)
2243 /* Return DMAMUX3_CLK frequency */
Clock_Ip_Get_DMAMUX3_CLK_Frequency(void)2244 static uint32 Clock_Ip_Get_DMAMUX3_CLK_Frequency(void) {
2245 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2246 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK41_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK41_SHIFT];
2247 return Frequency;
2248 }
2249 #endif
2250
2251 #if defined(CLOCK_IP_HAS_DSPI_MSC_CLK)
2252 /* Return DSPI_MSC_CLK frequency */
Clock_Ip_Get_DSPI_MSC_CLK_Frequency(void)2253 static uint32 Clock_Ip_Get_DSPI_MSC_CLK_Frequency(void) {
2254 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2255 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB2_STAT & MC_ME_PRTN2_COFB2_STAT_BLOCK66_MASK) >> MC_ME_PRTN2_COFB2_STAT_BLOCK66_SHIFT];
2256 return Frequency;
2257 }
2258 #endif
2259
2260 /* Return EDMA0_CLK frequency */
Clock_Ip_Get_EDMA0_CLK_Frequency(void)2261 static uint32 Clock_Ip_Get_EDMA0_CLK_Frequency(void) {
2262 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2263 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK3_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK3_SHIFT];
2264 return Frequency;
2265 }
2266 /* Return EDMA0_TCD0_CLK frequency */
Clock_Ip_Get_EDMA0_TCD0_CLK_Frequency(void)2267 static uint32 Clock_Ip_Get_EDMA0_TCD0_CLK_Frequency(void) {
2268 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2269 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK4_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK4_SHIFT];
2270 return Frequency;
2271 }
2272 /* Return EDMA0_TCD1_CLK frequency */
Clock_Ip_Get_EDMA0_TCD1_CLK_Frequency(void)2273 static uint32 Clock_Ip_Get_EDMA0_TCD1_CLK_Frequency(void) {
2274 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2275 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK5_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK5_SHIFT];
2276 return Frequency;
2277 }
2278 /* Return EDMA0_TCD2_CLK frequency */
Clock_Ip_Get_EDMA0_TCD2_CLK_Frequency(void)2279 static uint32 Clock_Ip_Get_EDMA0_TCD2_CLK_Frequency(void) {
2280 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2281 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK6_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK6_SHIFT];
2282 return Frequency;
2283 }
2284 /* Return EDMA0_TCD3_CLK frequency */
Clock_Ip_Get_EDMA0_TCD3_CLK_Frequency(void)2285 static uint32 Clock_Ip_Get_EDMA0_TCD3_CLK_Frequency(void) {
2286 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2287 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK7_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK7_SHIFT];
2288 return Frequency;
2289 }
2290 /* Return EDMA0_TCD4_CLK frequency */
Clock_Ip_Get_EDMA0_TCD4_CLK_Frequency(void)2291 static uint32 Clock_Ip_Get_EDMA0_TCD4_CLK_Frequency(void) {
2292 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2293 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK8_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK8_SHIFT];
2294 return Frequency;
2295 }
2296 /* Return EDMA0_TCD5_CLK frequency */
Clock_Ip_Get_EDMA0_TCD5_CLK_Frequency(void)2297 static uint32 Clock_Ip_Get_EDMA0_TCD5_CLK_Frequency(void) {
2298 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2299 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK9_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK9_SHIFT];
2300 return Frequency;
2301 }
2302 /* Return EDMA0_TCD6_CLK frequency */
Clock_Ip_Get_EDMA0_TCD6_CLK_Frequency(void)2303 static uint32 Clock_Ip_Get_EDMA0_TCD6_CLK_Frequency(void) {
2304 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2305 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK10_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK10_SHIFT];
2306 return Frequency;
2307 }
2308 /* Return EDMA0_TCD7_CLK frequency */
Clock_Ip_Get_EDMA0_TCD7_CLK_Frequency(void)2309 static uint32 Clock_Ip_Get_EDMA0_TCD7_CLK_Frequency(void) {
2310 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2311 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK11_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK11_SHIFT];
2312 return Frequency;
2313 }
2314 /* Return EDMA0_TCD8_CLK frequency */
Clock_Ip_Get_EDMA0_TCD8_CLK_Frequency(void)2315 static uint32 Clock_Ip_Get_EDMA0_TCD8_CLK_Frequency(void) {
2316 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2317 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK12_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK12_SHIFT];
2318 return Frequency;
2319 }
2320 /* Return EDMA0_TCD9_CLK frequency */
Clock_Ip_Get_EDMA0_TCD9_CLK_Frequency(void)2321 static uint32 Clock_Ip_Get_EDMA0_TCD9_CLK_Frequency(void) {
2322 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2323 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK13_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK13_SHIFT];
2324 return Frequency;
2325 }
2326 /* Return EDMA0_TCD10_CLK frequency */
Clock_Ip_Get_EDMA0_TCD10_CLK_Frequency(void)2327 static uint32 Clock_Ip_Get_EDMA0_TCD10_CLK_Frequency(void) {
2328 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2329 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK14_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK14_SHIFT];
2330 return Frequency;
2331 }
2332 /* Return EDMA0_TCD11_CLK frequency */
Clock_Ip_Get_EDMA0_TCD11_CLK_Frequency(void)2333 static uint32 Clock_Ip_Get_EDMA0_TCD11_CLK_Frequency(void) {
2334 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2335 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK15_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK15_SHIFT];
2336 return Frequency;
2337 }
2338 #if defined(CLOCK_IP_HAS_EDMA0_TCD12_CLK)
2339 /* Return EDMA0_TCD12_CLK frequency */
Clock_Ip_Get_EDMA0_TCD12_CLK_Frequency(void)2340 static uint32 Clock_Ip_Get_EDMA0_TCD12_CLK_Frequency(void) {
2341 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2342 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK4_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK4_SHIFT];
2343 return Frequency;
2344 }
2345 #endif
2346 #if defined(CLOCK_IP_HAS_EDMA0_TCD13_CLK)
2347 /* Return EDMA0_TCD13_CLK frequency */
Clock_Ip_Get_EDMA0_TCD13_CLK_Frequency(void)2348 static uint32 Clock_Ip_Get_EDMA0_TCD13_CLK_Frequency(void) {
2349 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2350 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK5_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK5_SHIFT];
2351 return Frequency;
2352 }
2353 #endif
2354 #if defined(CLOCK_IP_HAS_EDMA0_TCD14_CLK)
2355 /* Return EDMA0_TCD14_CLK frequency */
Clock_Ip_Get_EDMA0_TCD14_CLK_Frequency(void)2356 static uint32 Clock_Ip_Get_EDMA0_TCD14_CLK_Frequency(void) {
2357 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2358 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK6_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK6_SHIFT];
2359 return Frequency;
2360 }
2361 #endif
2362 #if defined(CLOCK_IP_HAS_EDMA0_TCD15_CLK)
2363 /* Return EDMA0_TCD15_CLK frequency */
Clock_Ip_Get_EDMA0_TCD15_CLK_Frequency(void)2364 static uint32 Clock_Ip_Get_EDMA0_TCD15_CLK_Frequency(void) {
2365 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2366 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK7_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK7_SHIFT];
2367 return Frequency;
2368 }
2369 #endif
2370 #if defined(CLOCK_IP_HAS_EDMA0_TCD16_CLK)
2371 /* Return EDMA0_TCD16_CLK frequency */
Clock_Ip_Get_EDMA0_TCD16_CLK_Frequency(void)2372 static uint32 Clock_Ip_Get_EDMA0_TCD16_CLK_Frequency(void) {
2373 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2374 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK8_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK8_SHIFT];
2375 return Frequency;
2376 }
2377 #endif
2378 #if defined(CLOCK_IP_HAS_EDMA0_TCD17_CLK)
2379 /* Return EDMA0_TCD17_CLK frequency */
Clock_Ip_Get_EDMA0_TCD17_CLK_Frequency(void)2380 static uint32 Clock_Ip_Get_EDMA0_TCD17_CLK_Frequency(void) {
2381 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2382 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK9_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK9_SHIFT];
2383 return Frequency;
2384 }
2385 #endif
2386 #if defined(CLOCK_IP_HAS_EDMA0_TCD18_CLK)
2387 /* Return EDMA0_TCD18_CLK frequency */
Clock_Ip_Get_EDMA0_TCD18_CLK_Frequency(void)2388 static uint32 Clock_Ip_Get_EDMA0_TCD18_CLK_Frequency(void) {
2389 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2390 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK10_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK10_SHIFT];
2391 return Frequency;
2392 }
2393 #endif
2394 #if defined(CLOCK_IP_HAS_EDMA0_TCD19_CLK)
2395 /* Return EDMA0_TCD19_CLK frequency */
Clock_Ip_Get_EDMA0_TCD19_CLK_Frequency(void)2396 static uint32 Clock_Ip_Get_EDMA0_TCD19_CLK_Frequency(void) {
2397 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2398 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK11_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK11_SHIFT];
2399 return Frequency;
2400 }
2401 #endif
2402 #if defined(CLOCK_IP_HAS_EDMA0_TCD20_CLK)
2403 /* Return EDMA0_TCD20_CLK frequency */
Clock_Ip_Get_EDMA0_TCD20_CLK_Frequency(void)2404 static uint32 Clock_Ip_Get_EDMA0_TCD20_CLK_Frequency(void) {
2405 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2406 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK12_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK12_SHIFT];
2407 return Frequency;
2408 }
2409 #endif
2410 #if defined(CLOCK_IP_HAS_EDMA0_TCD21_CLK)
2411 /* Return EDMA0_TCD21_CLK frequency */
Clock_Ip_Get_EDMA0_TCD21_CLK_Frequency(void)2412 static uint32 Clock_Ip_Get_EDMA0_TCD21_CLK_Frequency(void) {
2413 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2414 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK13_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK13_SHIFT];
2415 return Frequency;
2416 }
2417 #endif
2418 #if defined(CLOCK_IP_HAS_EDMA0_TCD22_CLK)
2419 /* Return EDMA0_TCD22_CLK frequency */
Clock_Ip_Get_EDMA0_TCD22_CLK_Frequency(void)2420 static uint32 Clock_Ip_Get_EDMA0_TCD22_CLK_Frequency(void) {
2421 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2422 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK14_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK14_SHIFT];
2423 return Frequency;
2424 }
2425 #endif
2426 #if defined(CLOCK_IP_HAS_EDMA0_TCD23_CLK)
2427 /* Return EDMA0_TCD23_CLK frequency */
Clock_Ip_Get_EDMA0_TCD23_CLK_Frequency(void)2428 static uint32 Clock_Ip_Get_EDMA0_TCD23_CLK_Frequency(void) {
2429 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2430 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK15_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK15_SHIFT];
2431 return Frequency;
2432 }
2433 #endif
2434 #if defined(CLOCK_IP_HAS_EDMA0_TCD24_CLK)
2435 /* Return EDMA0_TCD24_CLK frequency */
Clock_Ip_Get_EDMA0_TCD24_CLK_Frequency(void)2436 static uint32 Clock_Ip_Get_EDMA0_TCD24_CLK_Frequency(void) {
2437 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2438 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK16_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK16_SHIFT];
2439 return Frequency;
2440 }
2441 #endif
2442 #if defined(CLOCK_IP_HAS_EDMA0_TCD25_CLK)
2443 /* Return EDMA0_TCD25_CLK frequency */
Clock_Ip_Get_EDMA0_TCD25_CLK_Frequency(void)2444 static uint32 Clock_Ip_Get_EDMA0_TCD25_CLK_Frequency(void) {
2445 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2446 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK17_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK17_SHIFT];
2447 return Frequency;
2448 }
2449 #endif
2450 #if defined(CLOCK_IP_HAS_EDMA0_TCD26_CLK)
2451 /* Return EDMA0_TCD26_CLK frequency */
Clock_Ip_Get_EDMA0_TCD26_CLK_Frequency(void)2452 static uint32 Clock_Ip_Get_EDMA0_TCD26_CLK_Frequency(void) {
2453 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2454 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK18_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK18_SHIFT];
2455 return Frequency;
2456 }
2457 #endif
2458 #if defined(CLOCK_IP_HAS_EDMA0_TCD27_CLK)
2459 /* Return EDMA0_TCD27_CLK frequency */
Clock_Ip_Get_EDMA0_TCD27_CLK_Frequency(void)2460 static uint32 Clock_Ip_Get_EDMA0_TCD27_CLK_Frequency(void) {
2461 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2462 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK19_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK19_SHIFT];
2463 return Frequency;
2464 }
2465 #endif
2466 #if defined(CLOCK_IP_HAS_EDMA0_TCD28_CLK)
2467 /* Return EDMA0_TCD28_CLK frequency */
Clock_Ip_Get_EDMA0_TCD28_CLK_Frequency(void)2468 static uint32 Clock_Ip_Get_EDMA0_TCD28_CLK_Frequency(void) {
2469 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2470 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK20_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK20_SHIFT];
2471 return Frequency;
2472 }
2473 #endif
2474 #if defined(CLOCK_IP_HAS_EDMA0_TCD29_CLK)
2475 /* Return EDMA0_TCD29_CLK frequency */
Clock_Ip_Get_EDMA0_TCD29_CLK_Frequency(void)2476 static uint32 Clock_Ip_Get_EDMA0_TCD29_CLK_Frequency(void) {
2477 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2478 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK21_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK21_SHIFT];
2479 return Frequency;
2480 }
2481 #endif
2482 #if defined(CLOCK_IP_HAS_EDMA0_TCD30_CLK)
2483 /* Return EDMA0_TCD30_CLK frequency */
Clock_Ip_Get_EDMA0_TCD30_CLK_Frequency(void)2484 static uint32 Clock_Ip_Get_EDMA0_TCD30_CLK_Frequency(void) {
2485 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2486 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK22_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK22_SHIFT];
2487 return Frequency;
2488 }
2489 #endif
2490 #if defined(CLOCK_IP_HAS_EDMA0_TCD31_CLK)
2491 /* Return EDMA0_TCD31_CLK frequency */
Clock_Ip_Get_EDMA0_TCD31_CLK_Frequency(void)2492 static uint32 Clock_Ip_Get_EDMA0_TCD31_CLK_Frequency(void) {
2493 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2494 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK23_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK23_SHIFT];
2495 return Frequency;
2496 }
2497 #endif
2498 #if defined(CLOCK_IP_HAS_EDMA1_CLK)
2499 /* Return EDMA1_CLK frequency */
Clock_Ip_Get_EDMA1_CLK_Frequency(void)2500 static uint32 Clock_Ip_Get_EDMA1_CLK_Frequency(void) {
2501 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2502 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK4_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK4_SHIFT];
2503 return Frequency;
2504 }
2505 #endif
2506 #if defined(CLOCK_IP_HAS_EDMA1_TCD0_CLK)
2507 /* Return EDMA1_TCD0_CLK frequency */
Clock_Ip_Get_EDMA1_TCD0_CLK_Frequency(void)2508 static uint32 Clock_Ip_Get_EDMA1_TCD0_CLK_Frequency(void) {
2509 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2510 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK5_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK5_SHIFT];
2511 return Frequency;
2512 }
2513 #endif
2514 #if defined(CLOCK_IP_HAS_EDMA1_TCD1_CLK)
2515 /* Return EDMA1_TCD1_CLK frequency */
Clock_Ip_Get_EDMA1_TCD1_CLK_Frequency(void)2516 static uint32 Clock_Ip_Get_EDMA1_TCD1_CLK_Frequency(void) {
2517 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2518 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK6_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK6_SHIFT];
2519 return Frequency;
2520 }
2521 #endif
2522 #if defined(CLOCK_IP_HAS_EDMA1_TCD2_CLK)
2523 /* Return EDMA1_TCD2_CLK frequency */
Clock_Ip_Get_EDMA1_TCD2_CLK_Frequency(void)2524 static uint32 Clock_Ip_Get_EDMA1_TCD2_CLK_Frequency(void) {
2525 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2526 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK7_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK7_SHIFT];
2527 return Frequency;
2528 }
2529 #endif
2530 #if defined(CLOCK_IP_HAS_EDMA1_TCD3_CLK)
2531 /* Return EDMA1_TCD3_CLK frequency */
Clock_Ip_Get_EDMA1_TCD3_CLK_Frequency(void)2532 static uint32 Clock_Ip_Get_EDMA1_TCD3_CLK_Frequency(void) {
2533 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2534 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK8_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK8_SHIFT];
2535 return Frequency;
2536 }
2537 #endif
2538 #if defined(CLOCK_IP_HAS_EDMA1_TCD4_CLK)
2539 /* Return EDMA1_TCD4_CLK frequency */
Clock_Ip_Get_EDMA1_TCD4_CLK_Frequency(void)2540 static uint32 Clock_Ip_Get_EDMA1_TCD4_CLK_Frequency(void) {
2541 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2542 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK9_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK9_SHIFT];
2543 return Frequency;
2544 }
2545 #endif
2546 #if defined(CLOCK_IP_HAS_EDMA1_TCD5_CLK)
2547 /* Return EDMA1_TCD5_CLK frequency */
Clock_Ip_Get_EDMA1_TCD5_CLK_Frequency(void)2548 static uint32 Clock_Ip_Get_EDMA1_TCD5_CLK_Frequency(void) {
2549 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2550 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK10_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK10_SHIFT];
2551 return Frequency;
2552 }
2553 #endif
2554 #if defined(CLOCK_IP_HAS_EDMA1_TCD6_CLK)
2555 /* Return EDMA1_TCD6_CLK frequency */
Clock_Ip_Get_EDMA1_TCD6_CLK_Frequency(void)2556 static uint32 Clock_Ip_Get_EDMA1_TCD6_CLK_Frequency(void) {
2557 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2558 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK11_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK11_SHIFT];
2559 return Frequency;
2560 }
2561 #endif
2562 #if defined(CLOCK_IP_HAS_EDMA1_TCD7_CLK)
2563 /* Return EDMA1_TCD7_CLK frequency */
Clock_Ip_Get_EDMA1_TCD7_CLK_Frequency(void)2564 static uint32 Clock_Ip_Get_EDMA1_TCD7_CLK_Frequency(void) {
2565 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2566 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK12_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK12_SHIFT];
2567 return Frequency;
2568 }
2569 #endif
2570 #if defined(CLOCK_IP_HAS_EDMA1_TCD8_CLK)
2571 /* Return EDMA1_TCD8_CLK frequency */
Clock_Ip_Get_EDMA1_TCD8_CLK_Frequency(void)2572 static uint32 Clock_Ip_Get_EDMA1_TCD8_CLK_Frequency(void) {
2573 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2574 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK13_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK13_SHIFT];
2575 return Frequency;
2576 }
2577 #endif
2578 #if defined(CLOCK_IP_HAS_EDMA1_TCD9_CLK)
2579 /* Return EDMA1_TCD9_CLK frequency */
Clock_Ip_Get_EDMA1_TCD9_CLK_Frequency(void)2580 static uint32 Clock_Ip_Get_EDMA1_TCD9_CLK_Frequency(void) {
2581 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2582 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK14_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK14_SHIFT];
2583 return Frequency;
2584 }
2585 #endif
2586 #if defined(CLOCK_IP_HAS_EDMA1_TCD10_CLK)
2587 /* Return EDMA1_TCD10_CLK frequency */
Clock_Ip_Get_EDMA1_TCD10_CLK_Frequency(void)2588 static uint32 Clock_Ip_Get_EDMA1_TCD10_CLK_Frequency(void) {
2589 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2590 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK15_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK15_SHIFT];
2591 return Frequency;
2592 }
2593 #endif
2594 #if defined(CLOCK_IP_HAS_EDMA1_TCD11_CLK)
2595 /* Return EDMA1_TCD11_CLK frequency */
Clock_Ip_Get_EDMA1_TCD11_CLK_Frequency(void)2596 static uint32 Clock_Ip_Get_EDMA1_TCD11_CLK_Frequency(void) {
2597 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2598 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK16_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK16_SHIFT];
2599 return Frequency;
2600 }
2601 #endif
2602 #if defined(CLOCK_IP_HAS_EDMA1_TCD12_CLK)
2603 /* Return EDMA1_TCD12_CLK frequency */
Clock_Ip_Get_EDMA1_TCD12_CLK_Frequency(void)2604 static uint32 Clock_Ip_Get_EDMA1_TCD12_CLK_Frequency(void) {
2605 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2606 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK17_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK17_SHIFT];
2607 return Frequency;
2608 }
2609 #endif
2610 #if defined(CLOCK_IP_HAS_EDMA1_TCD13_CLK)
2611 /* Return EDMA1_TCD13_CLK frequency */
Clock_Ip_Get_EDMA1_TCD13_CLK_Frequency(void)2612 static uint32 Clock_Ip_Get_EDMA1_TCD13_CLK_Frequency(void) {
2613 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2614 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK18_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK18_SHIFT];
2615 return Frequency;
2616 }
2617 #endif
2618 #if defined(CLOCK_IP_HAS_EDMA1_TCD14_CLK)
2619 /* Return EDMA1_TCD14_CLK frequency */
Clock_Ip_Get_EDMA1_TCD14_CLK_Frequency(void)2620 static uint32 Clock_Ip_Get_EDMA1_TCD14_CLK_Frequency(void) {
2621 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2622 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK19_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK19_SHIFT];
2623 return Frequency;
2624 }
2625 #endif
2626 #if defined(CLOCK_IP_HAS_EDMA1_TCD15_CLK)
2627 /* Return EDMA1_TCD15_CLK frequency */
Clock_Ip_Get_EDMA1_TCD15_CLK_Frequency(void)2628 static uint32 Clock_Ip_Get_EDMA1_TCD15_CLK_Frequency(void) {
2629 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2630 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK20_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK20_SHIFT];
2631 return Frequency;
2632 }
2633 #endif
2634 #if defined(CLOCK_IP_HAS_EDMA1_TCD16_CLK)
2635 /* Return EDMA1_TCD16_CLK frequency */
Clock_Ip_Get_EDMA1_TCD16_CLK_Frequency(void)2636 static uint32 Clock_Ip_Get_EDMA1_TCD16_CLK_Frequency(void) {
2637 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2638 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK0_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK0_SHIFT];
2639 return Frequency;
2640 }
2641 #endif
2642 #if defined(CLOCK_IP_HAS_EDMA1_TCD17_CLK)
2643 /* Return EDMA1_TCD17_CLK frequency */
Clock_Ip_Get_EDMA1_TCD17_CLK_Frequency(void)2644 static uint32 Clock_Ip_Get_EDMA1_TCD17_CLK_Frequency(void) {
2645 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2646 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK1_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK1_SHIFT];
2647 return Frequency;
2648 }
2649 #endif
2650 #if defined(CLOCK_IP_HAS_EDMA1_TCD18_CLK)
2651 /* Return EDMA1_TCD18_CLK frequency */
Clock_Ip_Get_EDMA1_TCD18_CLK_Frequency(void)2652 static uint32 Clock_Ip_Get_EDMA1_TCD18_CLK_Frequency(void) {
2653 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2654 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK2_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK2_SHIFT];
2655 return Frequency;
2656 }
2657 #endif
2658 #if defined(CLOCK_IP_HAS_EDMA1_TCD19_CLK)
2659 /* Return EDMA1_TCD19_CLK frequency */
Clock_Ip_Get_EDMA1_TCD19_CLK_Frequency(void)2660 static uint32 Clock_Ip_Get_EDMA1_TCD19_CLK_Frequency(void) {
2661 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2662 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK3_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK3_SHIFT];
2663 return Frequency;
2664 }
2665 #endif
2666 #if defined(CLOCK_IP_HAS_EDMA1_TCD20_CLK)
2667 /* Return EDMA1_TCD20_CLK frequency */
Clock_Ip_Get_EDMA1_TCD20_CLK_Frequency(void)2668 static uint32 Clock_Ip_Get_EDMA1_TCD20_CLK_Frequency(void) {
2669 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2670 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK4_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK4_SHIFT];
2671 return Frequency;
2672 }
2673 #endif
2674 #if defined(CLOCK_IP_HAS_EDMA1_TCD21_CLK)
2675 /* Return EDMA1_TCD21_CLK frequency */
Clock_Ip_Get_EDMA1_TCD21_CLK_Frequency(void)2676 static uint32 Clock_Ip_Get_EDMA1_TCD21_CLK_Frequency(void) {
2677 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2678 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK5_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK5_SHIFT];
2679 return Frequency;
2680 }
2681 #endif
2682 #if defined(CLOCK_IP_HAS_EDMA1_TCD22_CLK)
2683 /* Return EDMA1_TCD22_CLK frequency */
Clock_Ip_Get_EDMA1_TCD22_CLK_Frequency(void)2684 static uint32 Clock_Ip_Get_EDMA1_TCD22_CLK_Frequency(void) {
2685 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2686 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK6_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK6_SHIFT];
2687 return Frequency;
2688 }
2689 #endif
2690 #if defined(CLOCK_IP_HAS_EDMA1_TCD23_CLK)
2691 /* Return EDMA1_TCD23_CLK frequency */
Clock_Ip_Get_EDMA1_TCD23_CLK_Frequency(void)2692 static uint32 Clock_Ip_Get_EDMA1_TCD23_CLK_Frequency(void) {
2693 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2694 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK7_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK7_SHIFT];
2695 return Frequency;
2696 }
2697 #endif
2698 #if defined(CLOCK_IP_HAS_EDMA1_TCD24_CLK)
2699 /* Return EDMA1_TCD24_CLK frequency */
Clock_Ip_Get_EDMA1_TCD24_CLK_Frequency(void)2700 static uint32 Clock_Ip_Get_EDMA1_TCD24_CLK_Frequency(void) {
2701 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2702 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK8_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK8_SHIFT];
2703 return Frequency;
2704 }
2705 #endif
2706 #if defined(CLOCK_IP_HAS_EDMA1_TCD25_CLK)
2707 /* Return EDMA1_TCD25_CLK frequency */
Clock_Ip_Get_EDMA1_TCD25_CLK_Frequency(void)2708 static uint32 Clock_Ip_Get_EDMA1_TCD25_CLK_Frequency(void) {
2709 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2710 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK9_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK9_SHIFT];
2711 return Frequency;
2712 }
2713 #endif
2714 #if defined(CLOCK_IP_HAS_EDMA1_TCD26_CLK)
2715 /* Return EDMA1_TCD26_CLK frequency */
Clock_Ip_Get_EDMA1_TCD26_CLK_Frequency(void)2716 static uint32 Clock_Ip_Get_EDMA1_TCD26_CLK_Frequency(void) {
2717 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2718 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK10_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK10_SHIFT];
2719 return Frequency;
2720 }
2721 #endif
2722 #if defined(CLOCK_IP_HAS_EDMA1_TCD27_CLK)
2723 /* Return EDMA1_TCD27_CLK frequency */
Clock_Ip_Get_EDMA1_TCD27_CLK_Frequency(void)2724 static uint32 Clock_Ip_Get_EDMA1_TCD27_CLK_Frequency(void) {
2725 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2726 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK11_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK11_SHIFT];
2727 return Frequency;
2728 }
2729 #endif
2730 #if defined(CLOCK_IP_HAS_EDMA1_TCD28_CLK)
2731 /* Return EDMA1_TCD28_CLK frequency */
Clock_Ip_Get_EDMA1_TCD28_CLK_Frequency(void)2732 static uint32 Clock_Ip_Get_EDMA1_TCD28_CLK_Frequency(void) {
2733 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2734 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK12_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK12_SHIFT];
2735 return Frequency;
2736 }
2737 #endif
2738 #if defined(CLOCK_IP_HAS_EDMA1_TCD29_CLK)
2739 /* Return EDMA1_TCD29_CLK frequency */
Clock_Ip_Get_EDMA1_TCD29_CLK_Frequency(void)2740 static uint32 Clock_Ip_Get_EDMA1_TCD29_CLK_Frequency(void) {
2741 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2742 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK13_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK13_SHIFT];
2743 return Frequency;
2744 }
2745 #endif
2746 #if defined(CLOCK_IP_HAS_EDMA1_TCD30_CLK)
2747 /* Return EDMA1_TCD30_CLK frequency */
Clock_Ip_Get_EDMA1_TCD30_CLK_Frequency(void)2748 static uint32 Clock_Ip_Get_EDMA1_TCD30_CLK_Frequency(void) {
2749 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2750 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK14_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK14_SHIFT];
2751 return Frequency;
2752 }
2753 #endif
2754 #if defined(CLOCK_IP_HAS_EDMA1_TCD31_CLK)
2755 /* Return EDMA1_TCD31_CLK frequency */
Clock_Ip_Get_EDMA1_TCD31_CLK_Frequency(void)2756 static uint32 Clock_Ip_Get_EDMA1_TCD31_CLK_Frequency(void) {
2757 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2758 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB0_STAT & MC_ME_PRTN3_COFB0_STAT_BLOCK15_MASK) >> MC_ME_PRTN3_COFB0_STAT_BLOCK15_SHIFT];
2759 return Frequency;
2760 }
2761 #endif
2762 #if defined(CLOCK_IP_HAS_EFLEX_PWM0_CLK)
2763 /* Return EFLEX_PWM0_CLK frequency */
Clock_Ip_Get_EFLEX_PWM0_CLK_Frequency(void)2764 static uint32 Clock_Ip_Get_EFLEX_PWM0_CLK_Frequency(void) {
2765 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2766 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK46_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK46_SHIFT];
2767 return Frequency;
2768 }
2769 #endif
2770 #if defined(CLOCK_IP_HAS_EFLEX_PWM1_CLK)
2771 /* Return EFLEX_PWM1_CLK frequency */
Clock_Ip_Get_EFLEX_PWM1_CLK_Frequency(void)2772 static uint32 Clock_Ip_Get_EFLEX_PWM1_CLK_Frequency(void) {
2773 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2774 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK47_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK47_SHIFT];
2775 return Frequency;
2776 }
2777 #endif
2778 #if defined(CLOCK_IP_HAS_EIM_CLK)
2779 /* Return EIM_CLK frequency */
Clock_Ip_Get_EIM_CLK_Frequency(void)2780 static uint32 Clock_Ip_Get_EIM_CLK_Frequency(void) {
2781 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2782 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK22_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK22_SHIFT];
2783 return Frequency;
2784 }
2785 #endif
2786 #if defined(CLOCK_IP_HAS_EIM0_CLK)
2787 /* Return EIM0_CLK frequency */
Clock_Ip_Get_EIM0_CLK_Frequency(void)2788 static uint32 Clock_Ip_Get_EIM0_CLK_Frequency(void) {
2789 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2790 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB2_STAT & MC_ME_PRTN2_COFB2_STAT_BLOCK67_MASK) >> MC_ME_PRTN2_COFB2_STAT_BLOCK67_SHIFT];
2791 return Frequency;
2792 }
2793 #endif
2794 #if defined(CLOCK_IP_HAS_EIM1_CLK)
2795 /* Return EIM1_CLK frequency */
Clock_Ip_Get_EIM1_CLK_Frequency(void)2796 static uint32 Clock_Ip_Get_EIM1_CLK_Frequency(void) {
2797 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2798 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB2_STAT & MC_ME_PRTN2_COFB2_STAT_BLOCK68_MASK) >> MC_ME_PRTN2_COFB2_STAT_BLOCK68_SHIFT];
2799 return Frequency;
2800 }
2801 #endif
2802 #if defined(CLOCK_IP_HAS_EIM2_CLK)
2803 /* Return EIM2_CLK frequency */
Clock_Ip_Get_EIM2_CLK_Frequency(void)2804 static uint32 Clock_Ip_Get_EIM2_CLK_Frequency(void) {
2805 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2806 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB2_STAT & MC_ME_PRTN2_COFB2_STAT_BLOCK69_MASK) >> MC_ME_PRTN2_COFB2_STAT_BLOCK69_SHIFT];
2807 return Frequency;
2808 }
2809 #endif
2810 #if defined(CLOCK_IP_HAS_EIM3_CLK)
2811 /* Return EIM3_CLK frequency */
Clock_Ip_Get_EIM3_CLK_Frequency(void)2812 static uint32 Clock_Ip_Get_EIM3_CLK_Frequency(void) {
2813 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2814 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB2_STAT & MC_ME_PRTN2_COFB2_STAT_BLOCK70_MASK) >> MC_ME_PRTN2_COFB2_STAT_BLOCK70_SHIFT];
2815 return Frequency;
2816 }
2817 #endif
2818 #if defined(CLOCK_IP_HAS_GMAC0_CLK)
2819 /* Return GMAC0_CLK frequency */
Clock_Ip_Get_GMAC0_CLK_Frequency(void)2820 static uint32 Clock_Ip_Get_GMAC0_CLK_Frequency(void) {
2821 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2822 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK33_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK33_SHIFT];
2823 return Frequency;
2824 }
2825 #endif
2826 #if defined(CLOCK_IP_HAS_GMAC1_CLK)
2827 /* Return GMAC1_CLK frequency */
Clock_Ip_Get_GMAC1_CLK_Frequency(void)2828 static uint32 Clock_Ip_Get_GMAC1_CLK_Frequency(void) {
2829 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
2830 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK34_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK34_SHIFT];
2831 return Frequency;
2832 }
2833 #endif
2834 #if defined(CLOCK_IP_HAS_EMAC_RX_CLK)
2835 /* Return EMAC_RX_CLK frequency */
Clock_Ip_Get_EMAC_RX_CLK_Frequency(void)2836 static uint32 Clock_Ip_Get_EMAC_RX_CLK_Frequency(void) {
2837 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)](); /* Selector value */
2838 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2839 Frequency /= (((IP_MC_CGM->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2840 return Frequency;
2841 }
2842 #endif
2843 #if defined(CLOCK_IP_HAS_EMAC0_RX_CLK)
2844 /* Return EMAC0_RX_CLK frequency */
Clock_Ip_Get_EMAC0_RX_CLK_Frequency(void)2845 static uint32 Clock_Ip_Get_EMAC0_RX_CLK_Frequency(void) {
2846 uint32 Frequency = Clock_Ip_Get_EMAC_RX_CLK_Frequency();
2847 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK32_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK32_SHIFT];
2848 return Frequency;
2849 }
2850 #endif
2851 #if defined(CLOCK_IP_HAS_EMAC_TS_CLK)
2852 /* Return EMAC_TS_CLK frequency */
Clock_Ip_Get_EMAC_TS_CLK_Frequency(void)2853 static uint32 Clock_Ip_Get_EMAC_TS_CLK_Frequency(void) {
2854 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)](); /* Selector value */
2855 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> MC_CGM_MUX_9_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2856 Frequency /= (((IP_MC_CGM->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2857 return Frequency;
2858 }
2859 #endif
2860 #if defined(CLOCK_IP_HAS_EMAC0_TS_CLK)
2861 /* Return EMAC0_TS_CLK frequency */
Clock_Ip_Get_EMAC0_TS_CLK_Frequency(void)2862 static uint32 Clock_Ip_Get_EMAC0_TS_CLK_Frequency(void) {
2863 uint32 Frequency = Clock_Ip_Get_EMAC_TS_CLK_Frequency();
2864 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK32_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK32_SHIFT];
2865 return Frequency;
2866 }
2867 #endif
2868 #if defined(CLOCK_IP_HAS_EMAC_TX_CLK)
2869 /* Return EMAC_TX_CLK frequency */
Clock_Ip_Get_EMAC_TX_CLK_Frequency(void)2870 static uint32 Clock_Ip_Get_EMAC_TX_CLK_Frequency(void) {
2871 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)](); /* Selector value */
2872 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC_CGM_MUX_8_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2873 Frequency /= (((IP_MC_CGM->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2874 return Frequency;
2875 }
2876 #endif
2877 #if defined(CLOCK_IP_HAS_EMAC0_TX_CLK)
2878 /* Return EMAC0_TX_CLK frequency */
Clock_Ip_Get_EMAC0_TX_CLK_Frequency(void)2879 static uint32 Clock_Ip_Get_EMAC0_TX_CLK_Frequency(void) {
2880 uint32 Frequency = Clock_Ip_Get_EMAC_TX_CLK_Frequency();
2881 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK32_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK32_SHIFT];
2882 return Frequency;
2883 }
2884 #endif
2885 #if defined(CLOCK_IP_HAS_EMAC_TX_RMII_CLK)
2886 /* Return EMAC_TX_RMII_CLK frequency */
Clock_Ip_Get_EMAC_TX_RMII_CLK_Frequency(void)2887 static uint32 Clock_Ip_Get_EMAC_TX_RMII_CLK_Frequency(void) {
2888 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_12_CSS & MC_CGM_MUX_12_CSS_SELSTAT_MASK) >> MC_CGM_MUX_12_CSS_SELSTAT_SHIFT)](); /* Selector value */
2889 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DE_MASK) >> MC_CGM_MUX_12_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2890 Frequency /= (((IP_MC_CGM->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DIV_MASK) >> MC_CGM_MUX_12_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2891 return Frequency;
2892 }
2893 #endif
2894 /* Return EMIOS0_CLK frequency */
Clock_Ip_Get_EMIOS0_CLK_Frequency(void)2895 static uint32 Clock_Ip_Get_EMIOS0_CLK_Frequency(void) {
2896 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2897 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK34_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK34_SHIFT];
2898 return Frequency;
2899 }
2900 #if defined(CLOCK_IP_HAS_EMIOS1_CLK)
2901 /* Return EMIOS1_CLK frequency */
Clock_Ip_Get_EMIOS1_CLK_Frequency(void)2902 static uint32 Clock_Ip_Get_EMIOS1_CLK_Frequency(void) {
2903 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2904 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK35_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK35_SHIFT];
2905 return Frequency;
2906 }
2907 #endif
2908 #if defined(CLOCK_IP_HAS_EMIOS2_CLK)
2909 /* Return EMIOS2_CLK frequency */
Clock_Ip_Get_EMIOS2_CLK_Frequency(void)2910 static uint32 Clock_Ip_Get_EMIOS2_CLK_Frequency(void) {
2911 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2912 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK36_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK36_SHIFT];
2913 return Frequency;
2914 }
2915 #endif
2916 /* Return ERM0_CLK frequency */
Clock_Ip_Get_ERM0_CLK_Frequency(void)2917 static uint32 Clock_Ip_Get_ERM0_CLK_Frequency(void) {
2918 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
2919 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK23_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK23_SHIFT];
2920 return Frequency;
2921 }
2922 #if defined(CLOCK_IP_HAS_ERM1_CLK)
2923 /* Return ERM1_CLK frequency */
Clock_Ip_Get_ERM1_CLK_Frequency(void)2924 static uint32 Clock_Ip_Get_ERM1_CLK_Frequency(void) {
2925 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
2926 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK3_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK3_SHIFT];
2927 return Frequency;
2928 }
2929 #endif
2930 #if defined(CLOCK_IP_HAS_ETPU_AB_REGISTERS_CLK)
2931 /* Return ETPU_AB_REGISTERS_CLK frequency */
Clock_Ip_Get_ETPU_AB_REGISTERS_CLK_Frequency(void)2932 static uint32 Clock_Ip_Get_ETPU_AB_REGISTERS_CLK_Frequency(void) {
2933 uint32 Frequency = Clock_Ip_Get_CM7_CORE_CLK_Frequency();
2934 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK32_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK32_SHIFT];
2935 return Frequency;
2936 }
2937 #endif
2938 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM1_CLK)
2939 /* Return ETPU_CODE_RAM1_CLK frequency */
Clock_Ip_Get_ETPU_CODE_RAM1_CLK_Frequency(void)2940 static uint32 Clock_Ip_Get_ETPU_CODE_RAM1_CLK_Frequency(void) {
2941 uint32 Frequency = Clock_Ip_Get_CM7_CORE_CLK_Frequency();
2942 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK36_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK36_SHIFT];
2943 return Frequency;
2944 }
2945 #endif
2946 #if defined(CLOCK_IP_HAS_ETPU_CODE_RAM2_CLK)
2947 /* Return ETPU_CODE_RAM2_CLK frequency */
Clock_Ip_Get_ETPU_CODE_RAM2_CLK_Frequency(void)2948 static uint32 Clock_Ip_Get_ETPU_CODE_RAM2_CLK_Frequency(void) {
2949 uint32 Frequency = Clock_Ip_Get_CM7_CORE_CLK_Frequency();
2950 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK37_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK37_SHIFT];
2951 return Frequency;
2952 }
2953 #endif
2954 #if defined(CLOCK_IP_HAS_ETPU_RAM_MIRROR_CLK)
2955 /* Return ETPU_RAM_MIRROR_CLK frequency */
Clock_Ip_Get_ETPU_RAM_MIRROR_CLK_Frequency(void)2956 static uint32 Clock_Ip_Get_ETPU_RAM_MIRROR_CLK_Frequency(void) {
2957 uint32 Frequency = Clock_Ip_Get_CM7_CORE_CLK_Frequency();
2958 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK35_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK35_SHIFT];
2959 return Frequency;
2960 }
2961 #endif
2962 #if defined(CLOCK_IP_HAS_ETPU_RAM_SDM_CLK)
2963 /* Return ETPU_RAM_SDM_CLK frequency */
Clock_Ip_Get_ETPU_RAM_SDM_CLK_Frequency(void)2964 static uint32 Clock_Ip_Get_ETPU_RAM_SDM_CLK_Frequency(void) {
2965 uint32 Frequency = Clock_Ip_Get_CM7_CORE_CLK_Frequency();
2966 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK34_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK34_SHIFT];
2967 return Frequency;
2968 }
2969 #endif
2970 #if defined(CLOCK_IP_HAS_FCCU_CLK)
2971 /* Return FCCU_CLK frequency */
Clock_Ip_Get_FCCU_CLK_Frequency(void)2972 static uint32 Clock_Ip_Get_FCCU_CLK_Frequency(void) {
2973 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
2974 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB3_STAT & MC_ME_PRTN1_COFB3_STAT_BLOCK97_MASK) >> MC_ME_PRTN1_COFB3_STAT_BLOCK97_SHIFT];
2975 return Frequency;
2976 }
2977 #endif
2978 #if defined(CLOCK_IP_HAS_FLASH0_CLK)
2979 /* Return FLASH0_CLK frequency */
Clock_Ip_Get_FLASH0_CLK_Frequency(void)2980 static uint32 Clock_Ip_Get_FLASH0_CLK_Frequency(void) {
2981 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2982 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK26_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK26_SHIFT];
2983 return Frequency;
2984 }
2985 #endif
2986 #if defined(CLOCK_IP_HAS_FLASH0_ALT_CLK)
2987 /* Return FLASH0_ALT_CLK frequency */
Clock_Ip_Get_FLASH0_ALT_CLK_Frequency(void)2988 static uint32 Clock_Ip_Get_FLASH0_ALT_CLK_Frequency(void) {
2989 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2990 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK27_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK27_SHIFT];
2991 return Frequency;
2992 }
2993 #endif
2994 #if defined(CLOCK_IP_HAS_FLASH1_CLK)
2995 /* Return FLASH1_CLK frequency */
Clock_Ip_Get_FLASH1_CLK_Frequency(void)2996 static uint32 Clock_Ip_Get_FLASH1_CLK_Frequency(void) {
2997 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
2998 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK59_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK59_SHIFT];
2999 return Frequency;
3000 }
3001 #endif
3002 #if defined(CLOCK_IP_HAS_FLASH1_ALT_CLK)
3003 /* Return FLASH1_ALT_CLK frequency */
Clock_Ip_Get_FLASH1_ALT_CLK_Frequency(void)3004 static uint32 Clock_Ip_Get_FLASH1_ALT_CLK_Frequency(void) {
3005 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3006 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK60_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK60_SHIFT];
3007 return Frequency;
3008 }
3009 #endif
3010 /* Return FLEXCANA_CLK frequency */
Clock_Ip_Get_FLEXCANA_CLK_Frequency(void)3011 static uint32 Clock_Ip_Get_FLEXCANA_CLK_Frequency(void) {
3012 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)](); /* Selector value */
3013 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DE_MASK) >> MC_CGM_MUX_3_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3014 Frequency /= (((IP_MC_CGM->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3015 return Frequency;
3016 }
3017 /* Return FLEXCAN0_CLK frequency */
Clock_Ip_Get_FLEXCAN0_CLK_Frequency(void)3018 static uint32 Clock_Ip_Get_FLEXCAN0_CLK_Frequency(void) {
3019 uint32 Frequency = Clock_Ip_Get_FLEXCANA_CLK_Frequency();
3020 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK65_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK65_SHIFT];
3021 return Frequency;
3022 }
3023 /* Return FLEXCAN1_CLK frequency */
Clock_Ip_Get_FLEXCAN1_CLK_Frequency(void)3024 static uint32 Clock_Ip_Get_FLEXCAN1_CLK_Frequency(void) {
3025 uint32 Frequency = Clock_Ip_Get_FLEXCANA_CLK_Frequency();
3026 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK66_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK66_SHIFT];
3027 return Frequency;
3028 }
3029 /* Return FLEXCAN2_CLK frequency */
Clock_Ip_Get_FLEXCAN2_CLK_Frequency(void)3030 static uint32 Clock_Ip_Get_FLEXCAN2_CLK_Frequency(void) {
3031 uint32 Frequency = Clock_Ip_Get_FLEXCANA_CLK_Frequency();
3032 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK67_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK67_SHIFT];
3033 return Frequency;
3034 }
3035 #if defined(CLOCK_IP_HAS_FLEXCANB_CLK)
3036 /* Return FLEXCANB_CLK frequency */
Clock_Ip_Get_FLEXCANB_CLK_Frequency(void)3037 static uint32 Clock_Ip_Get_FLEXCANB_CLK_Frequency(void) {
3038 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)](); /* Selector value */
3039 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3040 Frequency /= (((IP_MC_CGM->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3041 return Frequency;
3042 }
3043 #endif
3044 #if defined(CLOCK_IP_HAS_FLEXCAN3_CLK)
3045 /* Return FLEXCAN3_CLK frequency */
Clock_Ip_Get_FLEXCAN3_CLK_Frequency(void)3046 static uint32 Clock_Ip_Get_FLEXCAN3_CLK_Frequency(void) {
3047 uint32 Frequency = Clock_Ip_Get_FLEXCANB_CLK_Frequency();
3048 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK68_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK68_SHIFT];
3049 return Frequency;
3050 }
3051 #endif
3052 #if defined(CLOCK_IP_HAS_FLEXCAN4_CLK)
3053 /* Return FLEXCAN4_CLK frequency */
Clock_Ip_Get_FLEXCAN4_CLK_Frequency(void)3054 static uint32 Clock_Ip_Get_FLEXCAN4_CLK_Frequency(void) {
3055 uint32 Frequency = Clock_Ip_Get_FLEXCANB_CLK_Frequency();
3056 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK69_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK69_SHIFT];
3057 return Frequency;
3058 }
3059 #endif
3060 #if defined(CLOCK_IP_HAS_FLEXCAN5_CLK)
3061 /* Return FLEXCAN5_CLK frequency */
Clock_Ip_Get_FLEXCAN5_CLK_Frequency(void)3062 static uint32 Clock_Ip_Get_FLEXCAN5_CLK_Frequency(void) {
3063 uint32 Frequency = Clock_Ip_Get_FLEXCANB_CLK_Frequency();
3064 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK70_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK70_SHIFT];
3065 return Frequency;
3066 }
3067 #endif
3068 #if defined(CLOCK_IP_HAS_FLEXCAN6_CLK)
3069 /* Return FLEXCAN6_CLK frequency */
Clock_Ip_Get_FLEXCAN6_CLK_Frequency(void)3070 static uint32 Clock_Ip_Get_FLEXCAN6_CLK_Frequency(void) {
3071 uint32 Frequency = Clock_Ip_Get_FLEXCANB_CLK_Frequency();
3072 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK71_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK71_SHIFT];
3073 return Frequency;
3074 }
3075 #endif
3076 #if defined(CLOCK_IP_HAS_FLEXCAN7_CLK)
3077 /* Return FLEXCAN7_CLK frequency */
Clock_Ip_Get_FLEXCAN7_CLK_Frequency(void)3078 static uint32 Clock_Ip_Get_FLEXCAN7_CLK_Frequency(void) {
3079 uint32 Frequency = Clock_Ip_Get_FLEXCANB_CLK_Frequency();
3080 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK72_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK72_SHIFT];
3081 return Frequency;
3082 }
3083 #endif
3084 /* Return FLEXIO0_CLK frequency */
Clock_Ip_Get_FLEXIO0_CLK_Frequency(void)3085 static uint32 Clock_Ip_Get_FLEXIO0_CLK_Frequency(void) {
3086 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3087 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK73_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK73_SHIFT];
3088 return Frequency;
3089 }
3090 #if defined(CLOCK_IP_HAS_HSE_MU0_CLK)
3091 /* Return HSE_MU0_CLK frequency */
Clock_Ip_Get_HSE_MU0_CLK_Frequency(void)3092 static uint32 Clock_Ip_Get_HSE_MU0_CLK_Frequency(void) {
3093 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3094 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB3_STAT & MC_ME_PRTN1_COFB3_STAT_BLOCK99_MASK) >> MC_ME_PRTN1_COFB3_STAT_BLOCK99_SHIFT];
3095 return Frequency;
3096 }
3097 #endif
3098 #if defined(CLOCK_IP_HAS_HSE_MU1_CLK)
3099 /* Return HSE_MU1_CLK frequency */
Clock_Ip_Get_HSE_MU1_CLK_Frequency(void)3100 static uint32 Clock_Ip_Get_HSE_MU1_CLK_Frequency(void) {
3101 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3102 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK59_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK59_SHIFT];
3103 return Frequency;
3104 }
3105 #endif
3106 #if defined(CLOCK_IP_HAS_JDC_CLK)
3107 /* Return JDC_CLK frequency */
Clock_Ip_Get_JDC_CLK_Frequency(void)3108 static uint32 Clock_Ip_Get_JDC_CLK_Frequency(void) {
3109 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3110 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB3_STAT & MC_ME_PRTN1_COFB3_STAT_BLOCK101_MASK) >> MC_ME_PRTN1_COFB3_STAT_BLOCK101_SHIFT];
3111 return Frequency;
3112 }
3113 #endif
3114 #if defined(CLOCK_IP_HAS_IGF0_CLK)
3115 /* Return IGF0_CLK frequency */
Clock_Ip_Get_IGF0_CLK_Frequency(void)3116 static uint32 Clock_Ip_Get_IGF0_CLK_Frequency(void) {
3117 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3118 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK44_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK44_SHIFT];
3119 return Frequency;
3120 }
3121 #endif
3122 /* Return INTM_CLK frequency */
Clock_Ip_Get_INTM_CLK_Frequency(void)3123 static uint32 Clock_Ip_Get_INTM_CLK_Frequency(void) {
3124 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3125 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK31_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK31_SHIFT];
3126 return Frequency;
3127 }
3128 /* Return LCU0_CLK frequency */
Clock_Ip_Get_LCU0_CLK_Frequency(void)3129 static uint32 Clock_Ip_Get_LCU0_CLK_Frequency(void) {
3130 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3131 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK38_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK38_SHIFT];
3132 return Frequency;
3133 }
3134 /* Return LCU1_CLK frequency */
Clock_Ip_Get_LCU1_CLK_Frequency(void)3135 static uint32 Clock_Ip_Get_LCU1_CLK_Frequency(void) {
3136 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3137 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK39_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK39_SHIFT];
3138 return Frequency;
3139 }
3140 #if defined(CLOCK_IP_HAS_LFAST_REF_CLK)
3141 /* Return LFAST_REF_CLK frequency */
Clock_Ip_Get_LFAST_REF_CLK_Frequency(void)3142 static uint32 Clock_Ip_Get_LFAST_REF_CLK_Frequency(void) {
3143 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_15_CSS & MC_CGM_MUX_15_CSS_SELSTAT_MASK) >> MC_CGM_MUX_15_CSS_SELSTAT_SHIFT)](); /* Selector value */
3144 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_15_DC_0 & MC_CGM_MUX_15_DC_0_DE_MASK) >> MC_CGM_MUX_15_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3145 Frequency /= (((IP_MC_CGM->MUX_15_DC_0 & MC_CGM_MUX_15_DC_0_DIV_MASK) >> MC_CGM_MUX_15_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3146 return Frequency;
3147 }
3148 #endif
3149 #if defined(CLOCK_IP_HAS_LPI2C0_CLK)
3150 /* Return LPI2C0_CLK frequency */
Clock_Ip_Get_LPI2C0_CLK_Frequency(void)3151 static uint32 Clock_Ip_Get_LPI2C0_CLK_Frequency(void) {
3152 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3153 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK84_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK84_SHIFT];
3154 return Frequency;
3155 }
3156 #endif
3157 /* Return LPI2C1_CLK frequency */
Clock_Ip_Get_LPI2C1_CLK_Frequency(void)3158 static uint32 Clock_Ip_Get_LPI2C1_CLK_Frequency(void) {
3159 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3160 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK85_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK85_SHIFT];
3161 return Frequency;
3162 }
3163 /* Return LPSPI0_CLK frequency */
Clock_Ip_Get_LPSPI0_CLK_Frequency(void)3164 static uint32 Clock_Ip_Get_LPSPI0_CLK_Frequency(void) {
3165 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3166 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK86_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK86_SHIFT];
3167 return Frequency;
3168 }
3169 /* Return LPSPI1_CLK frequency */
Clock_Ip_Get_LPSPI1_CLK_Frequency(void)3170 static uint32 Clock_Ip_Get_LPSPI1_CLK_Frequency(void) {
3171 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3172 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK87_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK87_SHIFT];
3173 return Frequency;
3174 }
3175 /* Return LPSPI2_CLK frequency */
Clock_Ip_Get_LPSPI2_CLK_Frequency(void)3176 static uint32 Clock_Ip_Get_LPSPI2_CLK_Frequency(void) {
3177 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3178 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK88_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK88_SHIFT];
3179 return Frequency;
3180 }
3181 /* Return LPSPI3_CLK frequency */
Clock_Ip_Get_LPSPI3_CLK_Frequency(void)3182 static uint32 Clock_Ip_Get_LPSPI3_CLK_Frequency(void) {
3183 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3184 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK89_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK89_SHIFT];
3185 return Frequency;
3186 }
3187 #if defined(CLOCK_IP_HAS_LPSPI4_CLK)
3188 /* Return LPSPI4_CLK frequency */
Clock_Ip_Get_LPSPI4_CLK_Frequency(void)3189 static uint32 Clock_Ip_Get_LPSPI4_CLK_Frequency(void) {
3190 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3191 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK47_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK47_SHIFT];
3192 return Frequency;
3193 }
3194 #endif
3195 #if defined(CLOCK_IP_HAS_LPSPI5_CLK)
3196 /* Return LPSPI5_CLK frequency */
Clock_Ip_Get_LPSPI5_CLK_Frequency(void)3197 static uint32 Clock_Ip_Get_LPSPI5_CLK_Frequency(void) {
3198 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3199 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK48_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK48_SHIFT];
3200 return Frequency;
3201 }
3202 #endif
3203 /* Return LPUART0_CLK frequency */
Clock_Ip_Get_LPUART0_CLK_Frequency(void)3204 static uint32 Clock_Ip_Get_LPUART0_CLK_Frequency(void) {
3205 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3206 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK74_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK74_SHIFT];
3207 return Frequency;
3208 }
3209 /* Return LPUART1_CLK frequency */
Clock_Ip_Get_LPUART1_CLK_Frequency(void)3210 static uint32 Clock_Ip_Get_LPUART1_CLK_Frequency(void) {
3211 #if defined(CLOCK_IP_DERIVATIVE_006)
3212 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3213 #else
3214 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3215 #endif
3216 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK75_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK75_SHIFT];
3217 return Frequency;
3218 }
3219 /* Return LPUART2_CLK frequency */
Clock_Ip_Get_LPUART2_CLK_Frequency(void)3220 static uint32 Clock_Ip_Get_LPUART2_CLK_Frequency(void) {
3221 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3222 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK76_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK76_SHIFT];
3223 return Frequency;
3224 }
3225 /* Return LPUART3_CLK frequency */
Clock_Ip_Get_LPUART3_CLK_Frequency(void)3226 static uint32 Clock_Ip_Get_LPUART3_CLK_Frequency(void) {
3227 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3228 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK77_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK77_SHIFT];
3229 return Frequency;
3230 }
3231 #if defined(CLOCK_IP_HAS_LPUART4_CLK)
3232 /* Return LPUART4_CLK frequency */
Clock_Ip_Get_LPUART4_CLK_Frequency(void)3233 static uint32 Clock_Ip_Get_LPUART4_CLK_Frequency(void) {
3234 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3235 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK78_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK78_SHIFT];
3236 return Frequency;
3237 }
3238 #endif
3239 #if defined(CLOCK_IP_HAS_LPUART5_CLK)
3240 /* Return LPUART5_CLK frequency */
Clock_Ip_Get_LPUART5_CLK_Frequency(void)3241 static uint32 Clock_Ip_Get_LPUART5_CLK_Frequency(void) {
3242 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3243 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK79_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK79_SHIFT];
3244 return Frequency;
3245 }
3246 #endif
3247 #if defined(CLOCK_IP_HAS_LPUART6_CLK)
3248 /* Return LPUART6_CLK frequency */
Clock_Ip_Get_LPUART6_CLK_Frequency(void)3249 static uint32 Clock_Ip_Get_LPUART6_CLK_Frequency(void) {
3250 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3251 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK80_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK80_SHIFT];
3252 return Frequency;
3253 }
3254 #endif
3255 #if defined(CLOCK_IP_HAS_LPUART7_CLK)
3256 /* Return LPUART7_CLK frequency */
Clock_Ip_Get_LPUART7_CLK_Frequency(void)3257 static uint32 Clock_Ip_Get_LPUART7_CLK_Frequency(void) {
3258 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3259 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK81_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK81_SHIFT];
3260 return Frequency;
3261 }
3262 #endif
3263 #if defined(CLOCK_IP_HAS_LPUART8_CLK)
3264 /* Return LPUART8_CLK frequency */
Clock_Ip_Get_LPUART8_CLK_Frequency(void)3265 static uint32 Clock_Ip_Get_LPUART8_CLK_Frequency(void) {
3266 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3267 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK35_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK35_SHIFT];
3268 return Frequency;
3269 }
3270 #endif
3271 #if defined(CLOCK_IP_HAS_LPUART9_CLK)
3272 /* Return LPUART9_CLK frequency */
Clock_Ip_Get_LPUART9_CLK_Frequency(void)3273 static uint32 Clock_Ip_Get_LPUART9_CLK_Frequency(void) {
3274 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3275 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK36_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK36_SHIFT];
3276 return Frequency;
3277 }
3278 #endif
3279 #if defined(CLOCK_IP_HAS_LPUART10_CLK)
3280 /* Return LPUART10_CLK frequency */
Clock_Ip_Get_LPUART10_CLK_Frequency(void)3281 static uint32 Clock_Ip_Get_LPUART10_CLK_Frequency(void) {
3282 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3283 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK37_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK37_SHIFT];
3284 return Frequency;
3285 }
3286 #endif
3287 #if defined(CLOCK_IP_HAS_LPUART11_CLK)
3288 /* Return LPUART11_CLK frequency */
Clock_Ip_Get_LPUART11_CLK_Frequency(void)3289 static uint32 Clock_Ip_Get_LPUART11_CLK_Frequency(void) {
3290 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3291 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK38_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK38_SHIFT];
3292 return Frequency;
3293 }
3294 #endif
3295 #if defined(CLOCK_IP_HAS_LPUART12_CLK)
3296 /* Return LPUART12_CLK frequency */
Clock_Ip_Get_LPUART12_CLK_Frequency(void)3297 static uint32 Clock_Ip_Get_LPUART12_CLK_Frequency(void) {
3298 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3299 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK39_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK39_SHIFT];
3300 return Frequency;
3301 }
3302 #endif
3303 #if defined(CLOCK_IP_HAS_LPUART13_CLK)
3304 /* Return LPUART13_CLK frequency */
Clock_Ip_Get_LPUART13_CLK_Frequency(void)3305 static uint32 Clock_Ip_Get_LPUART13_CLK_Frequency(void) {
3306 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3307 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK40_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK40_SHIFT];
3308 return Frequency;
3309 }
3310 #endif
3311 #if defined(CLOCK_IP_HAS_LPUART14_CLK)
3312 /* Return LPUART14_CLK frequency */
Clock_Ip_Get_LPUART14_CLK_Frequency(void)3313 static uint32 Clock_Ip_Get_LPUART14_CLK_Frequency(void) {
3314 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3315 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK41_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK41_SHIFT];
3316 return Frequency;
3317 }
3318 #endif
3319 #if defined(CLOCK_IP_HAS_LPUART15_CLK)
3320 /* Return LPUART15_CLK frequency */
Clock_Ip_Get_LPUART15_CLK_Frequency(void)3321 static uint32 Clock_Ip_Get_LPUART15_CLK_Frequency(void) {
3322 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3323 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK42_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK42_SHIFT];
3324 return Frequency;
3325 }
3326 #endif
3327 #if defined(CLOCK_IP_HAS_LPUART_MSC_CLK)
3328 /* Return LPUART_MSC_CLK frequency */
Clock_Ip_Get_LPUART_MSC_CLK_Frequency(void)3329 static uint32 Clock_Ip_Get_LPUART_MSC_CLK_Frequency(void) {
3330 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3331 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB2_STAT & MC_ME_PRTN2_COFB2_STAT_BLOCK65_MASK) >> MC_ME_PRTN2_COFB2_STAT_BLOCK65_SHIFT];
3332 return Frequency;
3333 }
3334 #endif
3335 /* Return MSCM_CLK frequency */
Clock_Ip_Get_MSCM_CLK_Frequency(void)3336 static uint32 Clock_Ip_Get_MSCM_CLK_Frequency(void) {
3337 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3338 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK24_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK24_SHIFT];
3339 return Frequency;
3340 }
3341 #if defined(CLOCK_IP_HAS_MU2A_CLK)
3342 /* Return MU2A_CLK frequency */
Clock_Ip_Get_MU2A_CLK_Frequency(void)3343 static uint32 Clock_Ip_Get_MU2A_CLK_Frequency(void) {
3344 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3345 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK46_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK46_SHIFT];
3346 return Frequency;
3347 }
3348 #endif
3349 #if defined(CLOCK_IP_HAS_MU2B_CLK)
3350 /* Return MU2B_CLK frequency */
Clock_Ip_Get_MU2B_CLK_Frequency(void)3351 static uint32 Clock_Ip_Get_MU2B_CLK_Frequency(void) {
3352 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3353 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK47_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK47_SHIFT];
3354 return Frequency;
3355 }
3356 #endif
3357 #if defined(CLOCK_IP_HAS_MU3A_CLK)
3358 /* Return MU3A_CLK frequency */
Clock_Ip_Get_MU3A_CLK_Frequency(void)3359 static uint32 Clock_Ip_Get_MU3A_CLK_Frequency(void) {
3360 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3361 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK49_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK49_SHIFT];
3362 return Frequency;
3363 }
3364 #endif
3365 #if defined(CLOCK_IP_HAS_MU3B_CLK)
3366 /* Return MU3B_CLK frequency */
Clock_Ip_Get_MU3B_CLK_Frequency(void)3367 static uint32 Clock_Ip_Get_MU3B_CLK_Frequency(void) {
3368 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3369 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK50_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK50_SHIFT];
3370 return Frequency;
3371 }
3372 #endif
3373 #if defined(CLOCK_IP_HAS_MU4A_CLK)
3374 /* Return MU4A_CLK frequency */
Clock_Ip_Get_MU4A_CLK_Frequency(void)3375 static uint32 Clock_Ip_Get_MU4A_CLK_Frequency(void) {
3376 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3377 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK51_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK51_SHIFT];
3378 return Frequency;
3379 }
3380 #endif
3381 #if defined(CLOCK_IP_HAS_MU4B_CLK)
3382 /* Return MU4B_CLK frequency */
Clock_Ip_Get_MU4B_CLK_Frequency(void)3383 static uint32 Clock_Ip_Get_MU4B_CLK_Frequency(void) {
3384 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3385 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK52_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK52_SHIFT];
3386 return Frequency;
3387 }
3388 #endif
3389 /* Return PIT0_CLK frequency */
Clock_Ip_Get_PIT0_CLK_Frequency(void)3390 static uint32 Clock_Ip_Get_PIT0_CLK_Frequency(void) {
3391 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3392 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK44_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK44_SHIFT];
3393 return Frequency;
3394 }
3395 /* Return PIT1_CLK frequency */
Clock_Ip_Get_PIT1_CLK_Frequency(void)3396 static uint32 Clock_Ip_Get_PIT1_CLK_Frequency(void) {
3397 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3398 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK45_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK45_SHIFT];
3399 return Frequency;
3400 }
3401 #if defined(CLOCK_IP_HAS_PIT2_CLK)
3402 /* Return PIT2_CLK frequency */
Clock_Ip_Get_PIT2_CLK_Frequency(void)3403 static uint32 Clock_Ip_Get_PIT2_CLK_Frequency(void) {
3404 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3405 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK63_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK63_SHIFT];
3406 return Frequency;
3407 }
3408 #endif
3409 #if defined(CLOCK_IP_HAS_PIT3_CLK)
3410 /* Return PIT3_CLK frequency */
Clock_Ip_Get_PIT3_CLK_Frequency(void)3411 static uint32 Clock_Ip_Get_PIT3_CLK_Frequency(void) {
3412 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3413 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK64_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK64_SHIFT];
3414 return Frequency;
3415 }
3416 #endif
3417 #if defined(CLOCK_IP_HAS_PRAMC0_CLK)
3418 /* Return PRAMC0_CLK frequency */
Clock_Ip_Get_PRAMC0_CLK_Frequency(void)3419 static uint32 Clock_Ip_Get_PRAMC0_CLK_Frequency(void) {
3420 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3421 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK25_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK25_SHIFT];
3422 return Frequency;
3423 }
3424 #endif
3425 #if defined(CLOCK_IP_HAS_PRAMC1_CLK)
3426 /* Return PRAMC1_CLK frequency */
Clock_Ip_Get_PRAMC1_CLK_Frequency(void)3427 static uint32 Clock_Ip_Get_PRAMC1_CLK_Frequency(void) {
3428 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3429 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK25_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK25_SHIFT];
3430 return Frequency;
3431 }
3432 #endif
3433 #if defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK)
3434 /* Return QSPI_2XSFIF_CLK frequency */
Clock_Ip_Get_QSPI_2XSFIF_CLK_Frequency(void)3435 static uint32 Clock_Ip_Get_QSPI_2XSFIF_CLK_Frequency(void) {
3436 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_10_CSS & MC_CGM_MUX_10_CSS_SELSTAT_MASK) >> MC_CGM_MUX_10_CSS_SELSTAT_SHIFT)](); /* Selector value */
3437 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DE_MASK) >> MC_CGM_MUX_10_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3438 Frequency /= ((((IP_MC_CGM->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DIV_MASK) >> MC_CGM_MUX_10_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3439 return Frequency;
3440 }
3441 #endif
3442 #if defined(CLOCK_IP_HAS_QSPI0_CLK)
3443 /* Return QSPI0_CLK frequency */
Clock_Ip_Get_QSPI0_CLK_Frequency(void)3444 static uint32 Clock_Ip_Get_QSPI0_CLK_Frequency(void) {
3445 uint32 Frequency = Clock_Ip_Get_QSPI_SFCK_CLK_Frequency();
3446 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK51_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK51_SHIFT];
3447 return Frequency;
3448 }
3449 #endif
3450 #if defined(CLOCK_IP_HAS_QSPI0_RAM_CLK)
3451 /* Return QSPI0_RAM_CLK frequency */
Clock_Ip_Get_QSPI0_RAM_CLK_Frequency(void)3452 static uint32 Clock_Ip_Get_QSPI0_RAM_CLK_Frequency(void) {
3453 uint32 Frequency = Clock_Ip_Get_QSPI_MEM_CLK_Frequency();
3454 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK51_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK51_SHIFT];
3455 return Frequency;
3456 }
3457 #endif
3458 #if defined(CLOCK_IP_HAS_QSPI0_TX_MEM_CLK)
3459 /* Return QSPI0_TX_MEM_CLK frequency */
Clock_Ip_Get_QSPI0_TX_MEM_CLK_Frequency(void)3460 static uint32 Clock_Ip_Get_QSPI0_TX_MEM_CLK_Frequency(void) {
3461 uint32 Frequency = Clock_Ip_Get_QSPI_MEM_CLK_Frequency();
3462 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK51_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK51_SHIFT];
3463 return Frequency;
3464 }
3465 #endif
3466 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) && defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK)
3467 /* Return QSPI_SFCK_CLK frequency */
Clock_Ip_Get_QSPI_SFCK_CLK_Frequency(void)3468 static uint32 Clock_Ip_Get_QSPI_SFCK_CLK_Frequency(void) {
3469 return Clock_Ip_Get_QSPI_2XSFIF_CLK_Frequency() / 2U;
3470 }
3471 #endif
3472 #if defined(CLOCK_IP_HAS_QSPI_SFCK_CLK) && !defined(CLOCK_IP_HAS_QSPI_2XSFIF_CLK)
3473 /* Return QSPI_SFCK_CLK frequency */
Clock_Ip_Get_QSPI_SFCK_CLK_Frequency(void)3474 static uint32 Clock_Ip_Get_QSPI_SFCK_CLK_Frequency(void) {
3475 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_10_CSS & MC_CGM_MUX_10_CSS_SELSTAT_MASK) >> MC_CGM_MUX_10_CSS_SELSTAT_SHIFT)](); /* Selector value */
3476 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DE_MASK) >> MC_CGM_MUX_10_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3477 Frequency /= (((IP_MC_CGM->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DIV_MASK) >> MC_CGM_MUX_10_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3478 return Frequency;
3479 }
3480 #endif
3481 /* Return RTC_CLK frequency */
Clock_Ip_Get_RTC_CLK_Frequency(void)3482 static uint32 Clock_Ip_Get_RTC_CLK_Frequency(void) {
3483 uint32 Frequency = 0;
3484 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
3485 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
3486 Frequency = OsIf_Trusted_Call_Return(Clock_Ip_Get_RTC_CLK_Frequency_TrustedCall);
3487 #else
3488 Frequency = Clock_Ip_Get_RTC_CLK_Frequency_TrustedCall();
3489 #endif
3490 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
3491
3492 return Frequency;
3493 }
3494 /* Return RTC_CLK frequency */
Clock_Ip_Get_RTC_CLK_Frequency_TrustedCall(void)3495 uint32 Clock_Ip_Get_RTC_CLK_Frequency_TrustedCall(void)
3496 {
3497 uint32 Frequency = Clock_Ip_apfFreqTableRTC_CLK[((IP_RTC->RTCC & RTC_RTCC_CLKSEL_MASK) >> RTC_RTCC_CLKSEL_SHIFT)](); /* Selector value */
3498
3499 return Frequency;
3500 }
3501 /* Return RTC0_CLK frequency */
Clock_Ip_Get_RTC0_CLK_Frequency(void)3502 static uint32 Clock_Ip_Get_RTC0_CLK_Frequency(void) {
3503 uint32 Frequency = Clock_Ip_Get_RTC_CLK_Frequency();
3504 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK34_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK34_SHIFT];
3505 return Frequency;
3506 }
3507 #if defined(CLOCK_IP_HAS_SAI0_CLK)
3508 /* Return SAI0_CLK frequency */
Clock_Ip_Get_SAI0_CLK_Frequency(void)3509 static uint32 Clock_Ip_Get_SAI0_CLK_Frequency(void) {
3510 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3511 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK91_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK91_SHIFT];
3512 return Frequency;
3513 }
3514 #endif
3515 #if defined(CLOCK_IP_HAS_SAI1_CLK)
3516 /* Return SAI1_CLK frequency */
Clock_Ip_Get_SAI1_CLK_Frequency(void)3517 static uint32 Clock_Ip_Get_SAI1_CLK_Frequency(void) {
3518 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3519 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK55_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK55_SHIFT];
3520 return Frequency;
3521 }
3522 #endif
3523 #if defined(CLOCK_IP_HAS_SDA_AP_CLK)
3524 /* Return SDA_AP_CLK frequency */
Clock_Ip_Get_SDA_AP_CLK_Frequency(void)3525 static uint32 Clock_Ip_Get_SDA_AP_CLK_Frequency(void) {
3526 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3527 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK21_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK21_SHIFT];
3528 return Frequency;
3529 }
3530 #endif
3531 #if defined(CLOCK_IP_HAS_SDADC0_CLK)
3532 /* Return SDADC0_CLK frequency */
Clock_Ip_Get_SDADC0_CLK_Frequency(void)3533 static uint32 Clock_Ip_Get_SDADC0_CLK_Frequency(void) {
3534 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3535 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK61_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK61_SHIFT];
3536 return Frequency;
3537 }
3538 #endif
3539 #if defined(CLOCK_IP_HAS_SDADC1_CLK)
3540 /* Return SDADC1_CLK frequency */
Clock_Ip_Get_SDADC1_CLK_Frequency(void)3541 static uint32 Clock_Ip_Get_SDADC1_CLK_Frequency(void) {
3542 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3543 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK62_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK62_SHIFT];
3544 return Frequency;
3545 }
3546 #endif
3547 #if defined(CLOCK_IP_HAS_SDADC2_CLK)
3548 /* Return SDADC2_CLK frequency */
Clock_Ip_Get_SDADC2_CLK_Frequency(void)3549 static uint32 Clock_Ip_Get_SDADC2_CLK_Frequency(void) {
3550 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3551 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK63_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK63_SHIFT];
3552 return Frequency;
3553 }
3554 #endif
3555 #if defined(CLOCK_IP_HAS_SDADC3_CLK)
3556 /* Return SDADC3_CLK frequency */
Clock_Ip_Get_SDADC3_CLK_Frequency(void)3557 static uint32 Clock_Ip_Get_SDADC3_CLK_Frequency(void) {
3558 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3559 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB2_STAT & MC_ME_PRTN3_COFB2_STAT_BLOCK64_MASK) >> MC_ME_PRTN3_COFB2_STAT_BLOCK64_SHIFT];
3560 return Frequency;
3561 }
3562 #endif
3563 #if defined(CLOCK_IP_HAS_SEMA42_CLK)
3564 /* Return SEMA42_CLK frequency */
Clock_Ip_Get_SEMA42_CLK_Frequency(void)3565 static uint32 Clock_Ip_Get_SEMA42_CLK_Frequency(void) {
3566 uint32 Frequency = Clock_Ip_Get_AIPS_PLAT_CLK_Frequency();
3567 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK24_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK24_SHIFT];
3568 return Frequency;
3569 }
3570 #endif
3571 #if defined(CLOCK_IP_HAS_SIPI0_CLK)
3572 /* Return SIPI0_CLK frequency */
Clock_Ip_Get_SIPI0_CLK_Frequency(void)3573 static uint32 Clock_Ip_Get_SIPI0_CLK_Frequency(void) {
3574 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3575 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK60_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK60_SHIFT];
3576 return Frequency;
3577 }
3578 #endif
3579 /* Return SIUL2_CLK frequency */
Clock_Ip_Get_SIUL2_CLK_Frequency(void)3580 static uint32 Clock_Ip_Get_SIUL2_CLK_Frequency(void) {
3581 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3582 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK42_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK42_SHIFT];
3583 return Frequency;
3584 }
3585 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_0_CLK)
3586 /* Return SIUL2_PDAC0_0_CLK frequency */
Clock_Ip_Get_SIUL2_PDAC0_0_CLK_Frequency(void)3587 static uint32 Clock_Ip_Get_SIUL2_PDAC0_0_CLK_Frequency(void) {
3588 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3589 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK36_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK36_SHIFT];
3590 return Frequency;
3591 }
3592 #endif
3593 #if defined(CLOCK_IP_HAS_SIUL2_PDAC0_1_CLK)
3594 /* Return SIUL2_PDAC0_1_CLK frequency */
Clock_Ip_Get_SIUL2_PDAC0_1_CLK_Frequency(void)3595 static uint32 Clock_Ip_Get_SIUL2_PDAC0_1_CLK_Frequency(void) {
3596 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3597 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK37_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK37_SHIFT];
3598 return Frequency;
3599 }
3600 #endif
3601 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_0_CLK)
3602 /* Return SIUL2_PDAC1_0_CLK frequency */
Clock_Ip_Get_SIUL2_PDAC1_0_CLK_Frequency(void)3603 static uint32 Clock_Ip_Get_SIUL2_PDAC1_0_CLK_Frequency(void) {
3604 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3605 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK38_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK38_SHIFT];
3606 return Frequency;
3607 }
3608 #endif
3609 #if defined(CLOCK_IP_HAS_SIUL2_PDAC1_1_CLK)
3610 /* Return SIUL2_PDAC1_1_CLK frequency */
Clock_Ip_Get_SIUL2_PDAC1_1_CLK_Frequency(void)3611 static uint32 Clock_Ip_Get_SIUL2_PDAC1_1_CLK_Frequency(void) {
3612 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3613 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK39_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK39_SHIFT];
3614 return Frequency;
3615 }
3616 #endif
3617 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_0_CLK)
3618 /* Return SIUL2_PDAC2_0_CLK frequency */
Clock_Ip_Get_SIUL2_PDAC2_0_CLK_Frequency(void)3619 static uint32 Clock_Ip_Get_SIUL2_PDAC2_0_CLK_Frequency(void) {
3620 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3621 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK40_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK40_SHIFT];
3622 return Frequency;
3623 }
3624 #endif
3625 #if defined(CLOCK_IP_HAS_SIUL2_PDAC2_1_CLK)
3626 /* Return SIUL2_PDAC2_1_CLK frequency */
Clock_Ip_Get_SIUL2_PDAC2_1_CLK_Frequency(void)3627 static uint32 Clock_Ip_Get_SIUL2_PDAC2_1_CLK_Frequency(void) {
3628 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3629 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK41_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK41_SHIFT];
3630 return Frequency;
3631 }
3632 #endif
3633 /* Return STCU0_CLK frequency */
Clock_Ip_Get_STCU0_CLK_Frequency(void)3634 static uint32 Clock_Ip_Get_STCU0_CLK_Frequency(void) {
3635 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3636 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB3_STAT & MC_ME_PRTN1_COFB3_STAT_BLOCK104_MASK) >> MC_ME_PRTN1_COFB3_STAT_BLOCK104_SHIFT];
3637 return Frequency;
3638 }
3639 /* Return STMA_CLK frequency */
Clock_Ip_Get_STMA_CLK_Frequency(void)3640 static uint32 Clock_Ip_Get_STMA_CLK_Frequency(void) {
3641 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)](); /* Selector value */
3642 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3643 Frequency /= (((IP_MC_CGM->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3644 return Frequency;
3645 }
3646 /* Return STM0_CLK frequency */
Clock_Ip_Get_STM0_CLK_Frequency(void)3647 static uint32 Clock_Ip_Get_STM0_CLK_Frequency(void) {
3648 uint32 Frequency = Clock_Ip_Get_STMA_CLK_Frequency();
3649 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK29_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK29_SHIFT];
3650 return Frequency;
3651 }
3652 #if defined(CLOCK_IP_HAS_STMB_CLK)
3653 /* Return STMB_CLK frequency */
Clock_Ip_Get_STMB_CLK_Frequency(void)3654 static uint32 Clock_Ip_Get_STMB_CLK_Frequency(void) {
3655 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)](); /* Selector value */
3656 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3657 Frequency /= (((IP_MC_CGM->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3658 return Frequency;
3659 }
3660 #endif
3661 #if defined(CLOCK_IP_HAS_STM1_CLK)
3662 /* Return STM1_CLK frequency */
Clock_Ip_Get_STM1_CLK_Frequency(void)3663 static uint32 Clock_Ip_Get_STM1_CLK_Frequency(void) {
3664 uint32 Frequency = Clock_Ip_Get_STMB_CLK_Frequency();
3665 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK29_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK29_SHIFT];
3666 return Frequency;
3667 }
3668 #endif
3669 #if defined(CLOCK_IP_HAS_STMC_CLK)
3670 /* Return STMC_CLK frequency */
Clock_Ip_Get_STMC_CLK_Frequency(void)3671 static uint32 Clock_Ip_Get_STMC_CLK_Frequency(void) {
3672 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_13_CSS & MC_CGM_MUX_13_CSS_SELSTAT_MASK) >> MC_CGM_MUX_13_CSS_SELSTAT_SHIFT)](); /* Selector value */
3673 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_13_DC_0 & MC_CGM_MUX_13_DC_0_DE_MASK) >> MC_CGM_MUX_13_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3674 Frequency /= (((IP_MC_CGM->MUX_13_DC_0 & MC_CGM_MUX_13_DC_0_DIV_MASK) >> MC_CGM_MUX_13_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3675 return Frequency;
3676 }
3677 #endif
3678 #if defined(CLOCK_IP_HAS_STM2_CLK)
3679 /* Return STM2_CLK frequency */
Clock_Ip_Get_STM2_CLK_Frequency(void)3680 static uint32 Clock_Ip_Get_STM2_CLK_Frequency(void) {
3681 uint32 Frequency = Clock_Ip_Get_STMC_CLK_Frequency();
3682 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK30_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK30_SHIFT];
3683 return Frequency;
3684 }
3685 #endif
3686 #if defined(CLOCK_IP_HAS_USDHC_CLK)
3687 /* Return USDHC_CLK frequency */
Clock_Ip_Get_USDHC_CLK_Frequency(void)3688 static uint32 Clock_Ip_Get_USDHC_CLK_Frequency(void) {
3689 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_14_CSS & MC_CGM_MUX_14_CSS_SELSTAT_MASK) >> MC_CGM_MUX_14_CSS_SELSTAT_SHIFT)](); /* Selector value */
3690 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_14_DC_0 & MC_CGM_MUX_14_DC_0_DE_MASK) >> MC_CGM_MUX_14_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3691 Frequency /= (((IP_MC_CGM->MUX_14_DC_0 & MC_CGM_MUX_14_DC_0_DIV_MASK) >> MC_CGM_MUX_14_DC_0_DIV_SHIFT) + 1U);
3692 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK57_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK57_SHIFT]; /* Apply divider value */
3693 return Frequency;
3694 }
3695 #endif
3696 #if defined(CLOCK_IP_HAS_SWG_CLK)
3697 /* Return SWG_CLK frequency */
Clock_Ip_Get_SWG_CLK_Frequency(void)3698 static uint32 Clock_Ip_Get_SWG_CLK_Frequency(void) {
3699 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_16_CSS & MC_CGM_MUX_16_CSS_SELSTAT_MASK) >> MC_CGM_MUX_16_CSS_SELSTAT_SHIFT)](); /* Selector value */
3700 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_16_DC_0 & MC_CGM_MUX_16_DC_0_DE_MASK) >> MC_CGM_MUX_16_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3701 Frequency /= (((IP_MC_CGM->MUX_16_DC_0 & MC_CGM_MUX_16_DC_0_DIV_MASK) >> MC_CGM_MUX_16_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3702 return Frequency;
3703 }
3704 #endif
3705 #if defined(CLOCK_IP_HAS_GMAC0_RX_CLK)
3706 /* Return GMAC0_RX_CLK frequency */
Clock_Ip_Get_GMAC0_RX_CLK_Frequency(void)3707 static uint32 Clock_Ip_Get_GMAC0_RX_CLK_Frequency(void) {
3708 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)](); /* Selector value */
3709 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3710 Frequency /= (((IP_MC_CGM->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3711 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK33_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK33_SHIFT];
3712 return Frequency;
3713 }
3714 #endif
3715 #if defined(CLOCK_IP_HAS_GMAC0_TX_CLK)
3716 /* Return GMAC0_TX_CLK frequency */
Clock_Ip_Get_GMAC0_TX_CLK_Frequency(void)3717 static uint32 Clock_Ip_Get_GMAC0_TX_CLK_Frequency(void) {
3718 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)](); /* Selector value */
3719 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC_CGM_MUX_8_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3720 Frequency /= (((IP_MC_CGM->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3721 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK33_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK33_SHIFT];
3722 return Frequency;
3723 }
3724 #endif
3725 #if defined(CLOCK_IP_HAS_GMAC_TS_CLK)
3726 /* Return GMAC_TS_CLK frequency */
Clock_Ip_Get_GMAC_TS_CLK_Frequency(void)3727 static uint32 Clock_Ip_Get_GMAC_TS_CLK_Frequency(void) {
3728 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)](); /* Selector value */
3729 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> MC_CGM_MUX_9_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3730 Frequency /= (((IP_MC_CGM->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3731 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK33_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK33_SHIFT];
3732 return Frequency;
3733 }
3734 #endif
3735 #if defined(CLOCK_IP_HAS_GMAC0_TX_RMII_CLK)
3736 /* Return GMAC0_TX_RMII_CLK frequency */
Clock_Ip_Get_GMAC0_TX_RMII_CLK_Frequency(void)3737 static uint32 Clock_Ip_Get_GMAC0_TX_RMII_CLK_Frequency(void) {
3738 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_12_CSS & MC_CGM_MUX_12_CSS_SELSTAT_MASK) >> MC_CGM_MUX_12_CSS_SELSTAT_SHIFT)](); /* Selector value */
3739 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DE_MASK) >> MC_CGM_MUX_12_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3740 Frequency /= (((IP_MC_CGM->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DIV_MASK) >> MC_CGM_MUX_12_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3741 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK33_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK33_SHIFT];
3742 return Frequency;
3743 }
3744 #endif
3745 #if defined(CLOCK_IP_HAS_GMAC1_RX_CLK)
3746 /* Return GMAC1_RX_CLK frequency */
Clock_Ip_Get_GMAC1_RX_CLK_Frequency(void)3747 static uint32 Clock_Ip_Get_GMAC1_RX_CLK_Frequency(void) {
3748 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_15_CSS & MC_CGM_MUX_15_CSS_SELSTAT_MASK) >> MC_CGM_MUX_15_CSS_SELSTAT_SHIFT)](); /* Selector value */
3749 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_15_DC_0 & MC_CGM_MUX_15_DC_0_DE_MASK) >> MC_CGM_MUX_15_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3750 Frequency /= (((IP_MC_CGM->MUX_15_DC_0 & MC_CGM_MUX_15_DC_0_DIV_MASK) >> MC_CGM_MUX_15_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3751 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK34_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK34_SHIFT];
3752 return Frequency;
3753 }
3754 #endif
3755 #if defined(CLOCK_IP_HAS_GMAC1_TX_CLK)
3756 /* Return GMAC1_TX_CLK frequency */
Clock_Ip_Get_GMAC1_TX_CLK_Frequency(void)3757 static uint32 Clock_Ip_Get_GMAC1_TX_CLK_Frequency(void) {
3758 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_16_CSS & MC_CGM_MUX_16_CSS_SELSTAT_MASK) >> MC_CGM_MUX_16_CSS_SELSTAT_SHIFT)](); /* Selector value */
3759 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_16_DC_0 & MC_CGM_MUX_16_DC_0_DE_MASK) >> MC_CGM_MUX_16_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3760 Frequency /= (((IP_MC_CGM->MUX_16_DC_0 & MC_CGM_MUX_16_DC_0_DIV_MASK) >> MC_CGM_MUX_16_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3761 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK34_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK34_SHIFT];
3762 return Frequency;
3763 }
3764 #endif
3765 #if defined(CLOCK_IP_HAS_GMAC1_RMII_CLK)
3766 /* Return GMAC1_RMII_CLK frequency */
Clock_Ip_Get_GMAC1_RMII_CLK_Frequency(void)3767 static uint32 Clock_Ip_Get_GMAC1_RMII_CLK_Frequency(void) {
3768 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_17_CSS & MC_CGM_MUX_17_CSS_SELSTAT_MASK) >> MC_CGM_MUX_17_CSS_SELSTAT_SHIFT)](); /* Selector value */
3769 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_17_DC_0 & MC_CGM_MUX_17_DC_0_DE_MASK) >> MC_CGM_MUX_17_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3770 Frequency /= (((IP_MC_CGM->MUX_17_DC_0 & MC_CGM_MUX_17_DC_0_DIV_MASK) >> MC_CGM_MUX_17_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3771 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK34_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK34_SHIFT];
3772 return Frequency;
3773 }
3774 #endif
3775 #if defined(CLOCK_IP_HAS_STMD_CLK)
3776 /* Return STMD_CLK frequency */
Clock_Ip_Get_STMD_CLK_Frequency(void)3777 static uint32 Clock_Ip_Get_STMD_CLK_Frequency(void) {
3778 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_18_CSS & MC_CGM_MUX_18_CSS_SELSTAT_MASK) >> MC_CGM_MUX_18_CSS_SELSTAT_SHIFT)](); /* Selector value */
3779 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_18_DC_0 & MC_CGM_MUX_18_DC_0_DE_MASK) >> MC_CGM_MUX_18_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3780 Frequency /= (((IP_MC_CGM->MUX_18_DC_0 & MC_CGM_MUX_18_DC_0_DIV_MASK) >> MC_CGM_MUX_18_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3781 return Frequency;
3782 }
3783 #endif
3784 #if defined(CLOCK_IP_HAS_STM3_CLK)
3785 /* Return STM3_CLK frequency */
Clock_Ip_Get_STM3_CLK_Frequency(void)3786 static uint32 Clock_Ip_Get_STM3_CLK_Frequency(void) {
3787 uint32 Frequency = Clock_Ip_Get_STMD_CLK_Frequency();
3788 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK31_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK31_SHIFT];
3789 return Frequency;
3790 }
3791 #endif
3792
3793 #if defined(CLOCK_IP_HAS_AES_CLK)
3794 /* Return AES_CLK frequency */
Clock_Ip_Get_AES_CLK_Frequency(void)3795 static uint32 Clock_Ip_Get_AES_CLK_Frequency(void) {
3796 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_19_CSS & MC_CGM_MUX_19_CSS_SELSTAT_MASK) >> MC_CGM_MUX_19_CSS_SELSTAT_SHIFT)](); /* Selector value */
3797 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_19_DC_0 & MC_CGM_MUX_19_DC_0_DE_MASK) >> MC_CGM_MUX_19_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3798 Frequency /= (((IP_MC_CGM->MUX_19_DC_0 & MC_CGM_MUX_19_DC_0_DIV_MASK) >> MC_CGM_MUX_19_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3799 return Frequency;
3800 }
3801 #endif
3802 #if defined(CLOCK_IP_HAS_SWG0_CLK)
3803 /* Return SWG0_CLK frequency */
Clock_Ip_Get_SWG0_CLK_Frequency(void)3804 static uint32 Clock_Ip_Get_SWG0_CLK_Frequency(void) {
3805 uint32 Frequency = Clock_Ip_Get_SWG_CLK_Frequency();
3806 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK50_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK50_SHIFT];
3807 return Frequency;
3808 }
3809 #endif
3810 #if defined(CLOCK_IP_HAS_SWG1_CLK)
3811 /* Return SWG1_CLK frequency */
Clock_Ip_Get_SWG1_CLK_Frequency(void)3812 static uint32 Clock_Ip_Get_SWG1_CLK_Frequency(void) {
3813 uint32 Frequency = Clock_Ip_Get_SWG_CLK_Frequency();
3814 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK51_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK51_SHIFT];
3815 return Frequency;
3816 }
3817 #endif
3818 /* Return SWT0_CLK frequency */
Clock_Ip_Get_SWT0_CLK_Frequency(void)3819 static uint32 Clock_Ip_Get_SWT0_CLK_Frequency(void) {
3820 uint32 Frequency = Clock_Ip_Get_SIRC_CLK_Frequency();
3821 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK28_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK28_SHIFT];
3822 return Frequency;
3823 }
3824 #if defined(CLOCK_IP_HAS_SWT1_CLK)
3825 /* Return SWT1_CLK frequency */
Clock_Ip_Get_SWT1_CLK_Frequency(void)3826 static uint32 Clock_Ip_Get_SWT1_CLK_Frequency(void) {
3827 uint32 Frequency = Clock_Ip_Get_SIRC_CLK_Frequency();
3828 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK27_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK27_SHIFT];
3829 return Frequency;
3830 }
3831 #endif
3832 #if defined(CLOCK_IP_HAS_SWT2_CLK)
3833 /* Return SWT2_CLK frequency */
Clock_Ip_Get_SWT2_CLK_Frequency(void)3834 static uint32 Clock_Ip_Get_SWT2_CLK_Frequency(void) {
3835 uint32 Frequency = Clock_Ip_Get_SIRC_CLK_Frequency();
3836 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB0_STAT & MC_ME_PRTN2_COFB0_STAT_BLOCK28_MASK) >> MC_ME_PRTN2_COFB0_STAT_BLOCK28_SHIFT];
3837 return Frequency;
3838 }
3839 #endif
3840 #if defined(CLOCK_IP_HAS_SWT3_CLK)
3841 /* Return SWT3_CLK frequency */
Clock_Ip_Get_SWT3_CLK_Frequency(void)3842 static uint32 Clock_Ip_Get_SWT3_CLK_Frequency(void) {
3843 uint32 Frequency = Clock_Ip_Get_SIRC_CLK_Frequency();
3844 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB0_STAT & MC_ME_PRTN0_COFB0_STAT_BLOCK28_MASK) >> MC_ME_PRTN0_COFB0_STAT_BLOCK28_SHIFT];
3845 return Frequency;
3846 }
3847 #endif
3848 #if defined(CLOCK_IP_HAS_TCM_CM7_0_CLK)
3849 /* Return TCM_CM7_0_CLK frequency */
Clock_Ip_Get_TCM_CM7_0_CLK_Frequency(void)3850 static uint32 Clock_Ip_Get_TCM_CM7_0_CLK_Frequency(void) {
3851 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3852 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK62_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK62_SHIFT];
3853 return Frequency;
3854 }
3855 #endif
3856 #if defined(CLOCK_IP_HAS_TCM_CM7_1_CLK)
3857 /* Return TCM_CM7_1_CLK frequency */
Clock_Ip_Get_TCM_CM7_1_CLK_Frequency(void)3858 static uint32 Clock_Ip_Get_TCM_CM7_1_CLK_Frequency(void) {
3859 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3860 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB1_STAT & MC_ME_PRTN2_COFB1_STAT_BLOCK63_MASK) >> MC_ME_PRTN2_COFB1_STAT_BLOCK63_SHIFT];
3861 return Frequency;
3862 }
3863 #endif
3864 /* Return TEMPSENSE_CLK frequency */
Clock_Ip_Get_TEMPSENSE_CLK_Frequency(void)3865 static uint32 Clock_Ip_Get_TEMPSENSE_CLK_Frequency(void) {
3866 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3867 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB2_STAT & MC_ME_PRTN1_COFB2_STAT_BLOCK95_MASK) >> MC_ME_PRTN1_COFB2_STAT_BLOCK95_SHIFT];
3868 return Frequency;
3869 }
3870 /* Return TRACE_CLK frequency */
Clock_Ip_Get_TRACE_CLK_Frequency(void)3871 static uint32 Clock_Ip_Get_TRACE_CLK_Frequency(void) {
3872 uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_11_CSS & MC_CGM_MUX_11_CSS_SELSTAT_MASK) >> MC_CGM_MUX_11_CSS_SELSTAT_SHIFT)](); /* Selector value */
3873 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_11_DC_0 & MC_CGM_MUX_11_DC_0_DE_MASK) >> MC_CGM_MUX_11_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3874 Frequency /= (((IP_MC_CGM->MUX_11_DC_0 & MC_CGM_MUX_11_DC_0_DIV_MASK) >> MC_CGM_MUX_11_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3875 return Frequency;
3876 }
3877 /* Return TRGMUX0_CLK frequency */
Clock_Ip_Get_TRGMUX0_CLK_Frequency(void)3878 static uint32 Clock_Ip_Get_TRGMUX0_CLK_Frequency(void) {
3879 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3880 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN0_COFB1_STAT & MC_ME_PRTN0_COFB1_STAT_BLOCK32_MASK) >> MC_ME_PRTN0_COFB1_STAT_BLOCK32_SHIFT];
3881 return Frequency;
3882 }
3883 #if defined(CLOCK_IP_HAS_TRGMUX1_CLK)
3884 /* Return TRGMUX1_CLK frequency */
Clock_Ip_Get_TRGMUX1_CLK_Frequency(void)3885 static uint32 Clock_Ip_Get_TRGMUX1_CLK_Frequency(void) {
3886 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3887 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN3_COFB1_STAT & MC_ME_PRTN3_COFB1_STAT_BLOCK48_MASK) >> MC_ME_PRTN3_COFB1_STAT_BLOCK48_SHIFT];
3888 return Frequency;
3889 }
3890 #endif
3891 #if defined(CLOCK_IP_HAS_TSENSE0_CLK)
3892 /* Return TSENSE0_CLK frequency */
Clock_Ip_Get_TSENSE0_CLK_Frequency(void)3893 static uint32 Clock_Ip_Get_TSENSE0_CLK_Frequency(void) {
3894 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3895 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK49_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK49_SHIFT];
3896 return Frequency;
3897 }
3898 #endif
3899 /* Return WKPU0_CLK frequency */
Clock_Ip_Get_WKPU0_CLK_Frequency(void)3900 static uint32 Clock_Ip_Get_WKPU0_CLK_Frequency(void) {
3901 uint32 Frequency = Clock_Ip_Get_AIPS_SLOW_CLK_Frequency();
3902 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK45_MASK) >> MC_ME_PRTN1_COFB1_STAT_BLOCK45_SHIFT];
3903 return Frequency;
3904 }
3905 #if defined(CLOCK_IP_HAS_XRDC_CLK)
3906 /* Return XRDC_CLK frequency */
Clock_Ip_Get_XRDC_CLK_Frequency(void)3907 static uint32 Clock_Ip_Get_XRDC_CLK_Frequency(void) {
3908 uint32 Frequency = Clock_Ip_Get_CORE_CLK_Frequency();
3909 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK30_MASK) >> MC_ME_PRTN1_COFB0_STAT_BLOCK30_SHIFT];
3910 return Frequency;
3911 }
3912 #endif
3913 #if defined(CLOCK_IP_HAS_AES_ACCEL_CLK)
3914 /* Return AES_ACCEL_CLK frequency */
Clock_Ip_Get_AES_ACCEL_CLK_Frequency(void)3915 static uint32 Clock_Ip_Get_AES_ACCEL_CLK_Frequency(void) {
3916 uint32 Frequency = Clock_Ip_Get_AES_CLK_Frequency();
3917 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB3_STAT & MC_ME_PRTN1_COFB3_STAT_BLOCK112_MASK) >> MC_ME_PRTN1_COFB3_STAT_BLOCK112_SHIFT];
3918 return Frequency;
3919 }
3920 #endif
3921 #if defined(CLOCK_IP_HAS_AES_APP0_CLK)
3922 /* Return AES_APP0_CLK frequency */
Clock_Ip_Get_AES_APP0_CLK_Frequency(void)3923 static uint32 Clock_Ip_Get_AES_APP0_CLK_Frequency(void) {
3924 uint32 Frequency = Clock_Ip_Get_AES_CLK_Frequency();
3925 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB3_STAT & MC_ME_PRTN1_COFB3_STAT_BLOCK113_MASK) >> MC_ME_PRTN1_COFB3_STAT_BLOCK113_SHIFT];
3926 return Frequency;
3927 }
3928 #endif
3929 #if defined(CLOCK_IP_HAS_AES_APP1_CLK)
3930 /* Return AES_APP1_CLK frequency */
Clock_Ip_Get_AES_APP1_CLK_Frequency(void)3931 static uint32 Clock_Ip_Get_AES_APP1_CLK_Frequency(void) {
3932 uint32 Frequency = Clock_Ip_Get_AES_CLK_Frequency();
3933 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB3_STAT & MC_ME_PRTN1_COFB3_STAT_BLOCK114_MASK) >> MC_ME_PRTN1_COFB3_STAT_BLOCK114_SHIFT];
3934 return Frequency;
3935 }
3936 #endif
3937 #if defined(CLOCK_IP_HAS_AES_APP2_CLK)
3938 /* Return AES_APP2_CLK frequency */
Clock_Ip_Get_AES_APP2_CLK_Frequency(void)3939 static uint32 Clock_Ip_Get_AES_APP2_CLK_Frequency(void) {
3940 uint32 Frequency = Clock_Ip_Get_AES_CLK_Frequency();
3941 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN1_COFB3_STAT & MC_ME_PRTN1_COFB3_STAT_BLOCK115_MASK) >> MC_ME_PRTN1_COFB3_STAT_BLOCK115_SHIFT];
3942 return Frequency;
3943 }
3944 #endif
3945 #if defined(CLOCK_IP_HAS_AES_APP3_CLK)
3946 /* Return AES_APP3_CLK frequency */
Clock_Ip_Get_AES_APP3_CLK_Frequency(void)3947 static uint32 Clock_Ip_Get_AES_APP3_CLK_Frequency(void) {
3948 uint32 Frequency = Clock_Ip_Get_AES_CLK_Frequency();
3949 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB2_STAT & MC_ME_PRTN2_COFB2_STAT_BLOCK72_MASK) >> MC_ME_PRTN2_COFB2_STAT_BLOCK72_SHIFT];
3950 return Frequency;
3951 }
3952 #endif
3953 #if defined(CLOCK_IP_HAS_AES_APP4_CLK)
3954 /* Return AES_APP4_CLK frequency */
Clock_Ip_Get_AES_APP4_CLK_Frequency(void)3955 static uint32 Clock_Ip_Get_AES_APP4_CLK_Frequency(void) {
3956 uint32 Frequency = Clock_Ip_Get_AES_CLK_Frequency();
3957 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB2_STAT & MC_ME_PRTN2_COFB2_STAT_BLOCK73_MASK) >> MC_ME_PRTN2_COFB2_STAT_BLOCK73_SHIFT];
3958 return Frequency;
3959 }
3960 #endif
3961 #if defined(CLOCK_IP_HAS_AES_APP5_CLK)
3962 /* Return AES_APP5_CLK frequency */
Clock_Ip_Get_AES_APP5_CLK_Frequency(void)3963 static uint32 Clock_Ip_Get_AES_APP5_CLK_Frequency(void) {
3964 uint32 Frequency = Clock_Ip_Get_AES_CLK_Frequency();
3965 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB2_STAT & MC_ME_PRTN2_COFB2_STAT_BLOCK74_MASK) >> MC_ME_PRTN2_COFB2_STAT_BLOCK74_SHIFT];
3966 return Frequency;
3967 }
3968 #endif
3969 #if defined(CLOCK_IP_HAS_AES_APP6_CLK)
3970 /* Return AES_APP6_CLK frequency */
Clock_Ip_Get_AES_APP6_CLK_Frequency(void)3971 static uint32 Clock_Ip_Get_AES_APP6_CLK_Frequency(void) {
3972 uint32 Frequency = Clock_Ip_Get_AES_CLK_Frequency();
3973 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB2_STAT & MC_ME_PRTN2_COFB2_STAT_BLOCK75_MASK) >> MC_ME_PRTN2_COFB2_STAT_BLOCK75_SHIFT];
3974 return Frequency;
3975 }
3976 #endif
3977 #if defined(CLOCK_IP_HAS_AES_APP7_CLK)
3978 /* Return AES_APP7_CLK frequency */
Clock_Ip_Get_AES_APP7_CLK_Frequency(void)3979 static uint32 Clock_Ip_Get_AES_APP7_CLK_Frequency(void) {
3980 uint32 Frequency = Clock_Ip_Get_AES_CLK_Frequency();
3981 Frequency &= Clock_Ip_u32EnableGate[(IP_MC_ME->PRTN2_COFB2_STAT & MC_ME_PRTN2_COFB2_STAT_BLOCK76_MASK) >> MC_ME_PRTN2_COFB2_STAT_BLOCK76_SHIFT];
3982 return Frequency;
3983 }
3984 #endif
3985
3986 /* Return Clock_Ip_PLL_VCO frequency */
3987 #define CLOCK_IP_PLL_VCO_MAX_FREQ (1280000000u)
Clock_Ip_PLL_VCO(const PLL_Type * Base)3988 static uint32 Clock_Ip_PLL_VCO(const PLL_Type *Base)
3989 {
3990 uint32 Fin;
3991 uint32 Rdiv;
3992 uint32 Mfi;
3993 uint32 Mfn;
3994 uint32 Fout = 0U;
3995 uint32 Var1;
3996 uint32 Var2;
3997 uint32 Var3;
3998 uint32 Var4;
3999 uint32 Var5;
4000 boolean Overflow = FALSE;
4001
4002 Fin = Clock_Ip_Get_FXOSC_CLK_Frequency(); /* input freq */
4003 Rdiv = ((Base->PLLDV & PLL_PLLDV_RDIV_MASK) >> PLL_PLLDV_RDIV_SHIFT); /* Rdiv */
4004 Mfi = ((Base->PLLDV & PLL_PLLDV_MFI_MASK) >> PLL_PLLDV_MFI_SHIFT); /* Mfi */
4005 #if defined(CLOCK_IP_HAS_PLLAUX_CLK)
4006 if (IP_PLL_AUX != Base)
4007 {
4008 #endif
4009 Mfn = ((Base->PLLFD & PLL_PLLFD_MFN_MASK) >> PLL_PLLFD_MFN_SHIFT); /* Mfn */
4010 #if defined(CLOCK_IP_HAS_PLLAUX_CLK)
4011 }
4012 else
4013 {
4014
4015 Mfn = 0;
4016 }
4017 #endif
4018 Var1 = Mfi / Rdiv; /* Mfi divided by Rdiv */
4019 Var2 = Mfi - (Var1 * Rdiv); /* Mfi minus Var1 multiplied by Rdiv */
4020 Var3 = (Rdiv << CLOCK_IP_MUL_BY_16384) + (Rdiv << CLOCK_IP_MUL_BY_2048); /* Rdiv multiplied by 18432 */
4021 Var4 = Fin / Var3; /* Fin divide by (Rdiv multiplied by 18432) */
4022 Var5 = Fin - (Var4 * Var3); /* Fin minus Var4 multiplied by (Rdiv mul 18432) */
4023
4024 if (0U != Fin)
4025 {
4026 if (Var1 == ((uint32)(Var1 * Fin) / Fin))
4027 {
4028 Fout = Var1 * Fin; /* Var1 multipied by Fin */
4029 }
4030 else
4031 {
4032 Overflow = TRUE;
4033 }
4034
4035 if ((Var2 == ((uint32)(Fin * Var2) / Fin)) && (CLOCK_IP_PLL_VCO_MAX_FREQ >= Fout))
4036 {
4037 Fout += Fin / Rdiv * Var2; /* Fin divided by Rdiv and multiplied by Var2 */
4038 }
4039 else
4040 {
4041 Overflow = TRUE;
4042 }
4043
4044 if (0U != Var4)
4045 {
4046 if ((Mfn == ((uint32)(Var4 * Mfn) / Var4)) && (CLOCK_IP_PLL_VCO_MAX_FREQ >= Fout))
4047 {
4048 Fout += Var4 * Mfn; /* Mfn multiplied by Var4 */
4049 }
4050 else
4051 {
4052 Overflow = TRUE;
4053 }
4054 }
4055
4056 if (0U != Mfn)
4057 {
4058 if ((Var5 == ((uint32)(Var5 * Mfn) / Mfn)) && (CLOCK_IP_PLL_VCO_MAX_FREQ >= Fout))
4059 {
4060 Fout += Var5 * Mfn / Var3; /* Var5 multiplied by Mfn and divide by (Rdiv mul 18432) */
4061 }
4062 else
4063 {
4064 Overflow = TRUE;
4065 }
4066 }
4067 }
4068
4069 if (TRUE == Overflow)
4070 {
4071 Fout = 0U;
4072 }
4073
4074 return Fout;
4075 }
4076
4077 /* Set frequency value for External Oscillator */
Clock_Ip_SetExternalOscillatorFrequency(Clock_Ip_NameType ExtOscName,uint32 Frequency)4078 void Clock_Ip_SetExternalOscillatorFrequency(Clock_Ip_NameType ExtOscName, uint32 Frequency)
4079 {
4080 switch(ExtOscName)
4081 {
4082 case FXOSC_CLK:
4083 Clock_Ip_u32fxosc = Frequency;
4084 break;
4085 #if defined(CLOCK_IP_HAS_SXOSC_CLK)
4086 case SXOSC_CLK:
4087 Clock_Ip_u32sxosc = Frequency;
4088 break;
4089 #endif
4090 default:
4091 /* Do nothing */
4092 break;
4093 }
4094 }
4095
4096 /* Return frequency value */
Clock_Ip_GetFreq(Clock_Ip_NameType ClockName)4097 uint32 Clock_Ip_GetFreq(Clock_Ip_NameType ClockName)
4098 {
4099 return Clock_Ip_apfFreqTable[ClockName]();
4100 }
4101
4102 /* Clock stop section code */
4103 #define MCU_STOP_SEC_CODE
4104 #include "Mcu_MemMap.h"
4105
4106 #endif /* #if (defined(CLOCK_IP_GET_FREQUENCY_API) && (CLOCK_IP_GET_FREQUENCY_API == STD_ON)) */
4107
4108 /* Clock start section code */
4109 #define MCU_START_SEC_CODE
4110 #include "Mcu_MemMap.h"
4111
4112 /* Set frequency value for External Signal */
Clock_Ip_SetExternalSignalFrequency(Clock_Ip_NameType SignalName,uint32 Frequency)4113 void Clock_Ip_SetExternalSignalFrequency(Clock_Ip_NameType SignalName, uint32 Frequency)
4114 {
4115 #if (defined(CLOCK_IP_GET_FREQUENCY_API) && (CLOCK_IP_GET_FREQUENCY_API == STD_ON))
4116 uint32 Index;
4117 for (Index = 0U; Index < CLOCK_IP_EXT_SIGNALS_NO; Index++)
4118 {
4119 if (SignalName == Clock_Ip_axExtSignalFreqEntries[Index].Name)
4120 {
4121 Clock_Ip_axExtSignalFreqEntries[Index].Frequency = Frequency;
4122 break;
4123 }
4124 }
4125 #else
4126 (void)SignalName;
4127 (void)Frequency;
4128 #endif
4129 }
4130 /* Clock stop section code */
4131 #define MCU_STOP_SEC_CODE
4132 #include "Mcu_MemMap.h"
4133
4134
4135 #ifdef __cplusplus
4136 }
4137 #endif
4138
4139 /** @} */
4140
4141
