1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Port.c
9 * @version 3.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Port.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_PORT_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_PORT_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_PORT_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_PORT_SW_MAJOR_VERSION_C 3
44 #define SCHM_PORT_SW_MINOR_VERSION_C 0
45 #define SCHM_PORT_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_00) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_01) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_02) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_03) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_04) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_05) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_06) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_07) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_08) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_09) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_10) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_11) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_12) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_13) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_14) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_15) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_16) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_17) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_18) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_19) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_20) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_21) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
146 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_22) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
147 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_22) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
148 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_23) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
149 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_23) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
150 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_24) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
151 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_24) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
152 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_25) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
153 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_25) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
154 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_26) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
155 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_26) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
156 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_27) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
157 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_27) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
158
159 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
160 #include "Rte_MemMap.h"
161 /*==================================================================================================
162 * GLOBAL CONSTANTS
163 ==================================================================================================*/
164
165
166 /*==================================================================================================
167 * GLOBAL VARIABLES
168 ==================================================================================================*/
169
170 /*==================================================================================================
171 * LOCAL FUNCTION PROTOTYPES
172 ==================================================================================================*/
173
174 #ifndef _COSMIC_C_S32K3XX_
175 /*================================================================================================*/
176 /**
177 * @brief This function returns the MSR register value (32 bits).
178 * @details This function returns the MSR register value (32 bits).
179 *
180 * @param[in] void No input parameters
181 * @return uint32 msr This function returns the MSR register value (32 bits).
182 *
183 * @pre None
184 * @post None
185 *
186 */
187 uint32 Port_schm_read_msr(void);
188 #endif /*ifndef _COSMIC_C_S32K3XX_*/
189 /*==================================================================================================
190 * LOCAL FUNCTIONS
191 ==================================================================================================*/
192 #define RTE_START_SEC_CODE
193 #include "Rte_MemMap.h"
194
195 #if (defined(_GREENHILLS_C_S32K3XX_) || defined(_CODEWARRIOR_C_S32K3XX_))
196 /*================================================================================================*/
197 /**
198 * @brief This macro returns the MSR register value (32 bits).
199 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
200 *
201 * @pre None
202 * @post None
203 *
204 */
205 #ifdef MCAL_PLATFORM_ARM
206 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Port_schm_read_msr(void)207 ASM_KEYWORD uint32 Port_schm_read_msr(void)
208 {
209 mrs x0, S3_3_c4_c2_1
210 }
211 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Port_schm_read_msr(void)212 ASM_KEYWORD uint32 Port_schm_read_msr(void)
213 {
214 mrs r0, CPSR
215 }
216 #else
Port_schm_read_msr(void)217 ASM_KEYWORD uint32 Port_schm_read_msr(void)
218 {
219 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
220 mrs r0, BASEPRI
221 #else
222 mrs r0, PRIMASK
223 #endif
224 }
225 #endif
226 #else
227 #ifdef MCAL_PLATFORM_S12
Port_schm_read_msr(void)228 ASM_KEYWORD uint32 Port_schm_read_msr(void)
229 {
230 tfr ccr, d6
231 }
232 #else
Port_schm_read_msr(void)233 ASM_KEYWORD uint32 Port_schm_read_msr(void)
234 {
235 mfmsr r3
236 }
237 #endif
238 #endif
239 #endif /*#ifdef GHS||CW*/
240
241 #ifdef _DIABDATA_C_S32K3XX_
242 /**
243 * @brief This function returns the MSR register value (32 bits).
244 * @details This function returns the MSR register value (32 bits).
245 *
246 * @param[in] void No input parameters
247 * @return uint32 msr This function returns the MSR register value (32 bits).
248 *
249 * @pre None
250 * @post None
251 *
252 */
253 #ifdef MCAL_PLATFORM_ARM
Port_schm_read_msr(void)254 uint32 Port_schm_read_msr(void)
255 {
256 register uint32 reg_tmp;
257 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
258 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
259 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
260 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
261 #else
262 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
263 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
264 #else
265 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
266 #endif
267 #endif
268 return (uint32)reg_tmp;
269 }
270 #else
Port_schm_read_msr(void)271 ASM_KEYWORD uint32 Port_schm_read_msr(void)
272 {
273 mfmsr r3
274 }
275 #endif /* MCAL_PLATFORM_ARM */
276
277 #endif /* _DIABDATA_C_S32K3XX_*/
278
279 #ifdef _COSMIC_C_S32K3XX_
280 /*================================================================================================*/
281 /**
282 * @brief This function returns the MSR register value (32 bits).
283 * @details This function returns the MSR register value (32 bits).
284 *
285 * @param[in] void No input parameters
286 * @return uint32 msr This function returns the MSR register value (32 bits).
287 *
288 * @pre None
289 * @post None
290 *
291 */
292
293 #ifdef MCAL_PLATFORM_S12
294 #define Port_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
295 #else
296 #define Port_schm_read_msr() ASM_KEYWORD("mfmsr r3")
297 #endif
298
299 #endif /*Cosmic compiler only*/
300
301
302 #ifdef _HITECH_C_S32K3XX_
303 /*================================================================================================*/
304 /**
305 * @brief This function returns the MSR register value (32 bits).
306 * @details This function returns the MSR register value (32 bits).
307 *
308 * @param[in] void No input parameters
309 * @return uint32 msr This function returns the MSR register value (32 bits).
310 *
311 * @pre None
312 * @post None
313 *
314 */
Port_schm_read_msr(void)315 uint32 Port_schm_read_msr(void)
316 {
317 uint32 result;
318 __asm volatile("mfmsr %0" : "=r" (result) :);
319 return result;
320 }
321
322 #endif /*HighTec compiler only*/
323 /*================================================================================================*/
324 #ifdef _LINARO_C_S32K3XX_
325 /**
326 * @brief This function returns the MSR register value (32 bits).
327 * @details This function returns the MSR register value (32 bits).
328 *
329 * @param[in] void No input parameters
330 * @return uint32 msr This function returns the MSR register value (32 bits).
331 *
332 * @pre None
333 * @post None
334 *
335 */
Port_schm_read_msr(void)336 uint32 Port_schm_read_msr(void)
337 {
338 register uint32 reg_tmp;
339 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
340 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
341 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
342 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
343 #else
344 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
345 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
346 #else
347 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
348 #endif
349 #endif
350 return (uint32)reg_tmp;
351 }
352 #endif /* _LINARO_C_S32K3XX_*/
353 /*================================================================================================*/
354
355 #ifdef _ARM_DS5_C_S32K3XX_
356 /**
357 * @brief This function returns the MSR register value (32 bits).
358 * @details This function returns the MSR register value (32 bits).
359 *
360 * @param[in] void No input parameters
361 * @return uint32 msr This function returns the MSR register value (32 bits).
362 *
363 * @pre None
364 * @post None
365 *
366 */
Port_schm_read_msr(void)367 uint32 Port_schm_read_msr(void)
368 {
369 register uint32 reg_tmp;
370 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
371 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
372 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
373 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
374 #else
375 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
376 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
377 #else
378 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
379 #endif
380 #endif
381 return (uint32)reg_tmp;
382 }
383 #endif /* _ARM_DS5_C_S32K3XX_ */
384
385 #ifdef _IAR_C_S32K3XX_
386 /**
387 * @brief This function returns the MSR register value (32 bits).
388 * @details This function returns the MSR register value (32 bits).
389 *
390 * @param[in] void No input parameters
391 * @return uint32 msr This function returns the MSR register value (32 bits).
392 *
393 * @pre None
394 * @post None
395 *
396 */
Port_schm_read_msr(void)397 uint32 Port_schm_read_msr(void)
398 {
399 register uint32 reg_tmp;
400
401 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
402 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
403 #else
404 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
405 #endif
406
407 return (uint32)reg_tmp;
408 }
409 #endif /* _IAR_C_S32K3XX_ */
410
411 #define RTE_STOP_SEC_CODE
412 #include "Rte_MemMap.h"
413
414 /*==================================================================================================
415 * GLOBAL FUNCTIONS
416 ==================================================================================================*/
417 #define RTE_START_SEC_CODE
418 #include "Rte_MemMap.h"
419
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_00(void)420 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_00(void)
421 {
422 uint32 msr;
423 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
424
425 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId])
426 {
427 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
428 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
429 #else
430 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
431 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
432 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
433 {
434 OsIf_SuspendAllInterrupts();
435 #ifdef _ARM_DS5_C_S32K3XX_
436 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
437 #endif
438 }
439 msr_PORT_EXCLUSIVE_AREA_00[u32CoreId] = msr;
440 }
441 reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId]++;
442 }
443
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_00(void)444 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_00(void)
445 {
446 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
447
448 reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId]--;
449 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
450 {
451 OsIf_ResumeAllInterrupts();
452 #ifdef _ARM_DS5_C_S32K3XX_
453 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
454 #endif
455 }
456 }
457
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_01(void)458 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_01(void)
459 {
460 uint32 msr;
461 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
462
463 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId])
464 {
465 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
466 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
467 #else
468 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
469 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
470 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
471 {
472 OsIf_SuspendAllInterrupts();
473 #ifdef _ARM_DS5_C_S32K3XX_
474 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
475 #endif
476 }
477 msr_PORT_EXCLUSIVE_AREA_01[u32CoreId] = msr;
478 }
479 reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId]++;
480 }
481
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_01(void)482 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_01(void)
483 {
484 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
485
486 reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId]--;
487 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
488 {
489 OsIf_ResumeAllInterrupts();
490 #ifdef _ARM_DS5_C_S32K3XX_
491 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
492 #endif
493 }
494 }
495
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_02(void)496 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_02(void)
497 {
498 uint32 msr;
499 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
500
501 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId])
502 {
503 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
504 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
505 #else
506 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
507 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
508 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
509 {
510 OsIf_SuspendAllInterrupts();
511 #ifdef _ARM_DS5_C_S32K3XX_
512 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
513 #endif
514 }
515 msr_PORT_EXCLUSIVE_AREA_02[u32CoreId] = msr;
516 }
517 reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId]++;
518 }
519
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_02(void)520 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_02(void)
521 {
522 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
523
524 reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId]--;
525 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
526 {
527 OsIf_ResumeAllInterrupts();
528 #ifdef _ARM_DS5_C_S32K3XX_
529 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
530 #endif
531 }
532 }
533
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_03(void)534 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_03(void)
535 {
536 uint32 msr;
537 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
538
539 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId])
540 {
541 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
542 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
543 #else
544 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
545 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
546 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
547 {
548 OsIf_SuspendAllInterrupts();
549 #ifdef _ARM_DS5_C_S32K3XX_
550 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
551 #endif
552 }
553 msr_PORT_EXCLUSIVE_AREA_03[u32CoreId] = msr;
554 }
555 reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId]++;
556 }
557
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_03(void)558 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_03(void)
559 {
560 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
561
562 reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId]--;
563 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
564 {
565 OsIf_ResumeAllInterrupts();
566 #ifdef _ARM_DS5_C_S32K3XX_
567 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
568 #endif
569 }
570 }
571
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_04(void)572 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_04(void)
573 {
574 uint32 msr;
575 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
576
577 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId])
578 {
579 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
580 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
581 #else
582 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
583 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
584 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
585 {
586 OsIf_SuspendAllInterrupts();
587 #ifdef _ARM_DS5_C_S32K3XX_
588 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
589 #endif
590 }
591 msr_PORT_EXCLUSIVE_AREA_04[u32CoreId] = msr;
592 }
593 reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId]++;
594 }
595
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_04(void)596 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_04(void)
597 {
598 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
599
600 reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId]--;
601 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
602 {
603 OsIf_ResumeAllInterrupts();
604 #ifdef _ARM_DS5_C_S32K3XX_
605 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
606 #endif
607 }
608 }
609
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_05(void)610 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_05(void)
611 {
612 uint32 msr;
613 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
614
615 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId])
616 {
617 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
618 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
619 #else
620 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
621 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
622 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
623 {
624 OsIf_SuspendAllInterrupts();
625 #ifdef _ARM_DS5_C_S32K3XX_
626 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
627 #endif
628 }
629 msr_PORT_EXCLUSIVE_AREA_05[u32CoreId] = msr;
630 }
631 reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId]++;
632 }
633
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_05(void)634 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_05(void)
635 {
636 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
637
638 reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId]--;
639 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
640 {
641 OsIf_ResumeAllInterrupts();
642 #ifdef _ARM_DS5_C_S32K3XX_
643 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
644 #endif
645 }
646 }
647
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_06(void)648 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_06(void)
649 {
650 uint32 msr;
651 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
652
653 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId])
654 {
655 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
656 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
657 #else
658 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
659 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
660 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
661 {
662 OsIf_SuspendAllInterrupts();
663 #ifdef _ARM_DS5_C_S32K3XX_
664 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
665 #endif
666 }
667 msr_PORT_EXCLUSIVE_AREA_06[u32CoreId] = msr;
668 }
669 reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId]++;
670 }
671
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_06(void)672 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_06(void)
673 {
674 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
675
676 reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId]--;
677 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
678 {
679 OsIf_ResumeAllInterrupts();
680 #ifdef _ARM_DS5_C_S32K3XX_
681 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
682 #endif
683 }
684 }
685
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_07(void)686 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_07(void)
687 {
688 uint32 msr;
689 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
690
691 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId])
692 {
693 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
694 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
695 #else
696 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
697 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
698 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
699 {
700 OsIf_SuspendAllInterrupts();
701 #ifdef _ARM_DS5_C_S32K3XX_
702 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
703 #endif
704 }
705 msr_PORT_EXCLUSIVE_AREA_07[u32CoreId] = msr;
706 }
707 reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId]++;
708 }
709
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_07(void)710 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_07(void)
711 {
712 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
713
714 reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId]--;
715 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
716 {
717 OsIf_ResumeAllInterrupts();
718 #ifdef _ARM_DS5_C_S32K3XX_
719 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
720 #endif
721 }
722 }
723
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_08(void)724 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_08(void)
725 {
726 uint32 msr;
727 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
728
729 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId])
730 {
731 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
732 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
733 #else
734 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
735 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
736 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
737 {
738 OsIf_SuspendAllInterrupts();
739 #ifdef _ARM_DS5_C_S32K3XX_
740 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
741 #endif
742 }
743 msr_PORT_EXCLUSIVE_AREA_08[u32CoreId] = msr;
744 }
745 reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId]++;
746 }
747
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_08(void)748 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_08(void)
749 {
750 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
751
752 reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId]--;
753 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
754 {
755 OsIf_ResumeAllInterrupts();
756 #ifdef _ARM_DS5_C_S32K3XX_
757 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
758 #endif
759 }
760 }
761
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_09(void)762 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_09(void)
763 {
764 uint32 msr;
765 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
766
767 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId])
768 {
769 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
770 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
771 #else
772 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
773 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
774 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
775 {
776 OsIf_SuspendAllInterrupts();
777 #ifdef _ARM_DS5_C_S32K3XX_
778 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
779 #endif
780 }
781 msr_PORT_EXCLUSIVE_AREA_09[u32CoreId] = msr;
782 }
783 reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId]++;
784 }
785
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_09(void)786 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_09(void)
787 {
788 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
789
790 reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId]--;
791 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
792 {
793 OsIf_ResumeAllInterrupts();
794 #ifdef _ARM_DS5_C_S32K3XX_
795 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
796 #endif
797 }
798 }
799
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_10(void)800 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_10(void)
801 {
802 uint32 msr;
803 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
804
805 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId])
806 {
807 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
808 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
809 #else
810 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
811 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
812 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
813 {
814 OsIf_SuspendAllInterrupts();
815 #ifdef _ARM_DS5_C_S32K3XX_
816 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
817 #endif
818 }
819 msr_PORT_EXCLUSIVE_AREA_10[u32CoreId] = msr;
820 }
821 reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId]++;
822 }
823
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_10(void)824 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_10(void)
825 {
826 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
827
828 reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId]--;
829 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
830 {
831 OsIf_ResumeAllInterrupts();
832 #ifdef _ARM_DS5_C_S32K3XX_
833 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
834 #endif
835 }
836 }
837
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_11(void)838 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_11(void)
839 {
840 uint32 msr;
841 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
842
843 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId])
844 {
845 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
846 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
847 #else
848 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
849 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
850 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
851 {
852 OsIf_SuspendAllInterrupts();
853 #ifdef _ARM_DS5_C_S32K3XX_
854 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
855 #endif
856 }
857 msr_PORT_EXCLUSIVE_AREA_11[u32CoreId] = msr;
858 }
859 reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId]++;
860 }
861
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_11(void)862 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_11(void)
863 {
864 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
865
866 reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId]--;
867 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
868 {
869 OsIf_ResumeAllInterrupts();
870 #ifdef _ARM_DS5_C_S32K3XX_
871 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
872 #endif
873 }
874 }
875
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_12(void)876 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_12(void)
877 {
878 uint32 msr;
879 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
880
881 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId])
882 {
883 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
884 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
885 #else
886 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
887 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
888 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
889 {
890 OsIf_SuspendAllInterrupts();
891 #ifdef _ARM_DS5_C_S32K3XX_
892 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
893 #endif
894 }
895 msr_PORT_EXCLUSIVE_AREA_12[u32CoreId] = msr;
896 }
897 reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId]++;
898 }
899
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_12(void)900 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_12(void)
901 {
902 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
903
904 reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId]--;
905 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
906 {
907 OsIf_ResumeAllInterrupts();
908 #ifdef _ARM_DS5_C_S32K3XX_
909 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
910 #endif
911 }
912 }
913
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_13(void)914 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_13(void)
915 {
916 uint32 msr;
917 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
918
919 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId])
920 {
921 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
922 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
923 #else
924 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
925 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
926 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
927 {
928 OsIf_SuspendAllInterrupts();
929 #ifdef _ARM_DS5_C_S32K3XX_
930 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
931 #endif
932 }
933 msr_PORT_EXCLUSIVE_AREA_13[u32CoreId] = msr;
934 }
935 reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId]++;
936 }
937
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_13(void)938 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_13(void)
939 {
940 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
941
942 reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId]--;
943 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
944 {
945 OsIf_ResumeAllInterrupts();
946 #ifdef _ARM_DS5_C_S32K3XX_
947 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
948 #endif
949 }
950 }
951
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_14(void)952 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_14(void)
953 {
954 uint32 msr;
955 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
956
957 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId])
958 {
959 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
960 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
961 #else
962 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
963 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
964 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
965 {
966 OsIf_SuspendAllInterrupts();
967 #ifdef _ARM_DS5_C_S32K3XX_
968 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
969 #endif
970 }
971 msr_PORT_EXCLUSIVE_AREA_14[u32CoreId] = msr;
972 }
973 reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId]++;
974 }
975
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_14(void)976 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_14(void)
977 {
978 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
979
980 reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId]--;
981 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
982 {
983 OsIf_ResumeAllInterrupts();
984 #ifdef _ARM_DS5_C_S32K3XX_
985 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
986 #endif
987 }
988 }
989
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_15(void)990 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_15(void)
991 {
992 uint32 msr;
993 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
994
995 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId])
996 {
997 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
998 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
999 #else
1000 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1001 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1002 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1003 {
1004 OsIf_SuspendAllInterrupts();
1005 #ifdef _ARM_DS5_C_S32K3XX_
1006 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1007 #endif
1008 }
1009 msr_PORT_EXCLUSIVE_AREA_15[u32CoreId] = msr;
1010 }
1011 reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId]++;
1012 }
1013
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_15(void)1014 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_15(void)
1015 {
1016 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1017
1018 reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId]--;
1019 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
1020 {
1021 OsIf_ResumeAllInterrupts();
1022 #ifdef _ARM_DS5_C_S32K3XX_
1023 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1024 #endif
1025 }
1026 }
1027
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_16(void)1028 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_16(void)
1029 {
1030 uint32 msr;
1031 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1032
1033 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId])
1034 {
1035 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1036 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1037 #else
1038 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1039 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1040 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1041 {
1042 OsIf_SuspendAllInterrupts();
1043 #ifdef _ARM_DS5_C_S32K3XX_
1044 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1045 #endif
1046 }
1047 msr_PORT_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1048 }
1049 reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId]++;
1050 }
1051
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_16(void)1052 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_16(void)
1053 {
1054 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1055
1056 reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId]--;
1057 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1058 {
1059 OsIf_ResumeAllInterrupts();
1060 #ifdef _ARM_DS5_C_S32K3XX_
1061 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1062 #endif
1063 }
1064 }
1065
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_17(void)1066 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_17(void)
1067 {
1068 uint32 msr;
1069 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1070
1071 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId])
1072 {
1073 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1074 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1075 #else
1076 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1077 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1078 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1079 {
1080 OsIf_SuspendAllInterrupts();
1081 #ifdef _ARM_DS5_C_S32K3XX_
1082 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1083 #endif
1084 }
1085 msr_PORT_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1086 }
1087 reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId]++;
1088 }
1089
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_17(void)1090 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_17(void)
1091 {
1092 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1093
1094 reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId]--;
1095 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1096 {
1097 OsIf_ResumeAllInterrupts();
1098 #ifdef _ARM_DS5_C_S32K3XX_
1099 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1100 #endif
1101 }
1102 }
1103
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_18(void)1104 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_18(void)
1105 {
1106 uint32 msr;
1107 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1108
1109 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId])
1110 {
1111 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1112 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1113 #else
1114 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1115 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1116 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1117 {
1118 OsIf_SuspendAllInterrupts();
1119 #ifdef _ARM_DS5_C_S32K3XX_
1120 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1121 #endif
1122 }
1123 msr_PORT_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1124 }
1125 reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId]++;
1126 }
1127
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_18(void)1128 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_18(void)
1129 {
1130 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1131
1132 reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId]--;
1133 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1134 {
1135 OsIf_ResumeAllInterrupts();
1136 #ifdef _ARM_DS5_C_S32K3XX_
1137 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1138 #endif
1139 }
1140 }
1141
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_19(void)1142 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_19(void)
1143 {
1144 uint32 msr;
1145 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1146
1147 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId])
1148 {
1149 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1150 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1151 #else
1152 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1153 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1154 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1155 {
1156 OsIf_SuspendAllInterrupts();
1157 #ifdef _ARM_DS5_C_S32K3XX_
1158 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1159 #endif
1160 }
1161 msr_PORT_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1162 }
1163 reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId]++;
1164 }
1165
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_19(void)1166 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_19(void)
1167 {
1168 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1169
1170 reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId]--;
1171 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1172 {
1173 OsIf_ResumeAllInterrupts();
1174 #ifdef _ARM_DS5_C_S32K3XX_
1175 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1176 #endif
1177 }
1178 }
1179
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_20(void)1180 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_20(void)
1181 {
1182 uint32 msr;
1183 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1184
1185 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId])
1186 {
1187 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1188 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1189 #else
1190 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1191 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1192 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1193 {
1194 OsIf_SuspendAllInterrupts();
1195 #ifdef _ARM_DS5_C_S32K3XX_
1196 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1197 #endif
1198 }
1199 msr_PORT_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1200 }
1201 reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId]++;
1202 }
1203
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_20(void)1204 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_20(void)
1205 {
1206 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1207
1208 reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId]--;
1209 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1210 {
1211 OsIf_ResumeAllInterrupts();
1212 #ifdef _ARM_DS5_C_S32K3XX_
1213 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1214 #endif
1215 }
1216 }
1217
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_21(void)1218 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_21(void)
1219 {
1220 uint32 msr;
1221 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1222
1223 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId])
1224 {
1225 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1226 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1227 #else
1228 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1229 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1230 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1231 {
1232 OsIf_SuspendAllInterrupts();
1233 #ifdef _ARM_DS5_C_S32K3XX_
1234 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1235 #endif
1236 }
1237 msr_PORT_EXCLUSIVE_AREA_21[u32CoreId] = msr;
1238 }
1239 reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId]++;
1240 }
1241
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_21(void)1242 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_21(void)
1243 {
1244 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1245
1246 reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId]--;
1247 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
1248 {
1249 OsIf_ResumeAllInterrupts();
1250 #ifdef _ARM_DS5_C_S32K3XX_
1251 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1252 #endif
1253 }
1254 }
1255
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_22(void)1256 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_22(void)
1257 {
1258 uint32 msr;
1259 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1260
1261 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId])
1262 {
1263 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1264 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1265 #else
1266 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1267 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1268 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1269 {
1270 OsIf_SuspendAllInterrupts();
1271 #ifdef _ARM_DS5_C_S32K3XX_
1272 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1273 #endif
1274 }
1275 msr_PORT_EXCLUSIVE_AREA_22[u32CoreId] = msr;
1276 }
1277 reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId]++;
1278 }
1279
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_22(void)1280 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_22(void)
1281 {
1282 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1283
1284 reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId]--;
1285 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
1286 {
1287 OsIf_ResumeAllInterrupts();
1288 #ifdef _ARM_DS5_C_S32K3XX_
1289 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1290 #endif
1291 }
1292 }
1293
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_23(void)1294 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_23(void)
1295 {
1296 uint32 msr;
1297 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1298
1299 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId])
1300 {
1301 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1302 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1303 #else
1304 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1305 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1306 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1307 {
1308 OsIf_SuspendAllInterrupts();
1309 #ifdef _ARM_DS5_C_S32K3XX_
1310 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1311 #endif
1312 }
1313 msr_PORT_EXCLUSIVE_AREA_23[u32CoreId] = msr;
1314 }
1315 reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId]++;
1316 }
1317
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_23(void)1318 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_23(void)
1319 {
1320 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1321
1322 reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId]--;
1323 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
1324 {
1325 OsIf_ResumeAllInterrupts();
1326 #ifdef _ARM_DS5_C_S32K3XX_
1327 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1328 #endif
1329 }
1330 }
1331
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_24(void)1332 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_24(void)
1333 {
1334 uint32 msr;
1335 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1336
1337 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId])
1338 {
1339 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1340 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1341 #else
1342 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1343 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1344 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1345 {
1346 OsIf_SuspendAllInterrupts();
1347 #ifdef _ARM_DS5_C_S32K3XX_
1348 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1349 #endif
1350 }
1351 msr_PORT_EXCLUSIVE_AREA_24[u32CoreId] = msr;
1352 }
1353 reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId]++;
1354 }
1355
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_24(void)1356 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_24(void)
1357 {
1358 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1359
1360 reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId]--;
1361 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId])) /*if interrupts were enabled*/
1362 {
1363 OsIf_ResumeAllInterrupts();
1364 #ifdef _ARM_DS5_C_S32K3XX_
1365 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1366 #endif
1367 }
1368 }
1369
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_25(void)1370 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_25(void)
1371 {
1372 uint32 msr;
1373 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1374
1375 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId])
1376 {
1377 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1378 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1379 #else
1380 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1381 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1382 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1383 {
1384 OsIf_SuspendAllInterrupts();
1385 #ifdef _ARM_DS5_C_S32K3XX_
1386 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1387 #endif
1388 }
1389 msr_PORT_EXCLUSIVE_AREA_25[u32CoreId] = msr;
1390 }
1391 reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId]++;
1392 }
1393
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_25(void)1394 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_25(void)
1395 {
1396 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1397
1398 reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId]--;
1399 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId])) /*if interrupts were enabled*/
1400 {
1401 OsIf_ResumeAllInterrupts();
1402 #ifdef _ARM_DS5_C_S32K3XX_
1403 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1404 #endif
1405 }
1406 }
1407
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_26(void)1408 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_26(void)
1409 {
1410 uint32 msr;
1411 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1412
1413 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId])
1414 {
1415 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1416 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1417 #else
1418 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1419 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1420 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1421 {
1422 OsIf_SuspendAllInterrupts();
1423 #ifdef _ARM_DS5_C_S32K3XX_
1424 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1425 #endif
1426 }
1427 msr_PORT_EXCLUSIVE_AREA_26[u32CoreId] = msr;
1428 }
1429 reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId]++;
1430 }
1431
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_26(void)1432 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_26(void)
1433 {
1434 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1435
1436 reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId]--;
1437 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId])) /*if interrupts were enabled*/
1438 {
1439 OsIf_ResumeAllInterrupts();
1440 #ifdef _ARM_DS5_C_S32K3XX_
1441 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1442 #endif
1443 }
1444 }
1445
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_27(void)1446 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_27(void)
1447 {
1448 uint32 msr;
1449 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1450
1451 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId])
1452 {
1453 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1454 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1455 #else
1456 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1457 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1458 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1459 {
1460 OsIf_SuspendAllInterrupts();
1461 #ifdef _ARM_DS5_C_S32K3XX_
1462 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1463 #endif
1464 }
1465 msr_PORT_EXCLUSIVE_AREA_27[u32CoreId] = msr;
1466 }
1467 reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId]++;
1468 }
1469
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_27(void)1470 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_27(void)
1471 {
1472 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1473
1474 reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId]--;
1475 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId])) /*if interrupts were enabled*/
1476 {
1477 OsIf_ResumeAllInterrupts();
1478 #ifdef _ARM_DS5_C_S32K3XX_
1479 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1480 #endif
1481 }
1482 }
1483
1484
1485 #ifdef MCAL_TESTING_ENVIRONMENT
1486 /**
1487 @brief This function checks that all entered exclusive areas were also exited.
1488 @details This function checks that all entered exclusive areas were also exited. The check
1489 is done by verifying that all reentry_guard_* static variables are back to the
1490 zero value.
1491
1492 @param[in] void No input parameters
1493 @return void This function does not return a value. Test asserts are used instead.
1494
1495 @pre None
1496 @post None
1497
1498 @remarks Covers
1499 @remarks Implements
1500 */
SchM_Check_port(void)1501 void SchM_Check_port(void)
1502 {
1503 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1504
1505 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId]);
1506 reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_00 for the next test in the suite*/
1507
1508 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId]);
1509 reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_01 for the next test in the suite*/
1510
1511 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId]);
1512 reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_02 for the next test in the suite*/
1513
1514 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId]);
1515 reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_03 for the next test in the suite*/
1516
1517 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId]);
1518 reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_04 for the next test in the suite*/
1519
1520 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId]);
1521 reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_05 for the next test in the suite*/
1522
1523 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId]);
1524 reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_06 for the next test in the suite*/
1525
1526 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId]);
1527 reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_07 for the next test in the suite*/
1528
1529 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId]);
1530 reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_08 for the next test in the suite*/
1531
1532 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId]);
1533 reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_09 for the next test in the suite*/
1534
1535 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId]);
1536 reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_10 for the next test in the suite*/
1537
1538 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId]);
1539 reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_11 for the next test in the suite*/
1540
1541 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId]);
1542 reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_12 for the next test in the suite*/
1543
1544 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId]);
1545 reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_13 for the next test in the suite*/
1546
1547 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId]);
1548 reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_14 for the next test in the suite*/
1549
1550 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId]);
1551 reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_15 for the next test in the suite*/
1552
1553 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId]);
1554 reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_16 for the next test in the suite*/
1555
1556 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId]);
1557 reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_17 for the next test in the suite*/
1558
1559 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId]);
1560 reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_18 for the next test in the suite*/
1561
1562 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId]);
1563 reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_19 for the next test in the suite*/
1564
1565 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId]);
1566 reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_20 for the next test in the suite*/
1567
1568 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId]);
1569 reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_21 for the next test in the suite*/
1570
1571 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId]);
1572 reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_22 for the next test in the suite*/
1573
1574 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId]);
1575 reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_23 for the next test in the suite*/
1576
1577 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId]);
1578 reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_24 for the next test in the suite*/
1579
1580 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId]);
1581 reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_25 for the next test in the suite*/
1582
1583 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId]);
1584 reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_26 for the next test in the suite*/
1585
1586 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId]);
1587 reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_27 for the next test in the suite*/
1588
1589
1590 }
1591 #endif /*MCAL_TESTING_ENVIRONMENT*/
1592
1593 #define RTE_STOP_SEC_CODE
1594 #include "Rte_MemMap.h"
1595
1596 #ifdef __cplusplus
1597 }
1598 #endif
1599
1600 /** @} */
1601
