1 /*
2 * Copyright 2021-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup RTE_MODULE
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Std_Types.h"
25 #include "Mcal.h"
26 #include "OsIf.h"
27 #include "SchM_Port.h"
28 #ifdef MCAL_TESTING_ENVIRONMENT
29 #include "EUnit.h" /* EUnit Test Suite */
30 #endif
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define SCHM_PORT_AR_RELEASE_MAJOR_VERSION_C 4
36 #define SCHM_PORT_AR_RELEASE_MINOR_VERSION_C 7
37 #define SCHM_PORT_AR_RELEASE_REVISION_VERSION_C 0
38 #define SCHM_PORT_SW_MAJOR_VERSION_C 0
39 #define SCHM_PORT_SW_MINOR_VERSION_C 9
40 #define SCHM_PORT_SW_PATCH_VERSION_C 0
41
42 /*==================================================================================================
43 * LOCAL CONSTANTS
44 ==================================================================================================*/
45 #ifdef MCAL_PLATFORM_ARM
46 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
47 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
48 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
49 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
50 #else
51 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
52 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
53 #else
54 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
55 #endif
56 #endif
57 #else
58 #ifdef MCAL_PLATFORM_S12
59 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
60 #else
61 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
62 #endif
63 #endif
64 /*==================================================================================================
65 * LOCAL MACROS
66 ==================================================================================================*/
67 #ifdef MCAL_PLATFORM_ARM
68 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
69 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
70 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
71 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
72 #else
73 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
74 #endif
75 #else
76 #ifdef MCAL_PLATFORM_S12
77 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
78 #else
79 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
80 #endif
81 #endif
82
83 /*==================================================================================================
84 * FILE VERSION CHECKS
85 ==================================================================================================*/
86
87 /*==================================================================================================
88 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
89 ==================================================================================================*/
90
91
92 /*==================================================================================================
93 * LOCAL VARIABLES
94 ==================================================================================================*/
95 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
96 #include "Rte_MemMap.h"
97 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_00) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
98 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
99 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_01) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
100 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
101 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_02) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
102 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_03) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_04) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_05) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_06) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_07) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_08) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_09) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_10) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_11) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_12) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_13) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_14) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_15) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_16) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_17) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_18) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_19) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_20) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_21) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_22) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_22) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_23) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_23) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_24) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
146 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_24) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
147 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_25) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
148 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_25) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
149 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_26) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
150 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_26) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
151 VAR_SEC_NOCACHE(msr_PORT_EXCLUSIVE_AREA_27) static volatile uint32 msr_PORT_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
152 VAR_SEC_NOCACHE(reentry_guard_PORT_EXCLUSIVE_AREA_27) static volatile uint32 reentry_guard_PORT_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
153
154 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
155 #include "Rte_MemMap.h"
156 /*==================================================================================================
157 * GLOBAL CONSTANTS
158 ==================================================================================================*/
159
160
161 /*==================================================================================================
162 * GLOBAL VARIABLES
163 ==================================================================================================*/
164
165 /*==================================================================================================
166 * LOCAL FUNCTION PROTOTYPES
167 ==================================================================================================*/
168
169 #ifndef _COSMIC_C_S32ZE_
170 /*================================================================================================*/
171 /**
172 * @brief This function returns the MSR register value (32 bits).
173 * @details This function returns the MSR register value (32 bits).
174 *
175 * @param[in] void No input parameters
176 * @return uint32 msr This function returns the MSR register value (32 bits).
177 *
178 * @pre None
179 * @post None
180 *
181 */
182 uint32 Port_schm_read_msr(void);
183 #endif /*ifndef _COSMIC_C_S32ZE_*/
184 /*==================================================================================================
185 * LOCAL FUNCTIONS
186 ==================================================================================================*/
187 #define RTE_START_SEC_CODE
188 #include "Rte_MemMap.h"
189
190 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
191 /*================================================================================================*/
192 /**
193 * @brief This macro returns the MSR register value (32 bits).
194 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
195 *
196 * @pre None
197 * @post None
198 *
199 */
200 #ifdef MCAL_PLATFORM_ARM
201 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Port_schm_read_msr(void)202 ASM_KEYWORD uint32 Port_schm_read_msr(void)
203 {
204 mrs x0, S3_3_c4_c2_1
205 }
206 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Port_schm_read_msr(void)207 ASM_KEYWORD uint32 Port_schm_read_msr(void)
208 {
209 mrs r0, CPSR
210 }
211 #else
Port_schm_read_msr(void)212 ASM_KEYWORD uint32 Port_schm_read_msr(void)
213 {
214 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
215 mrs r0, BASEPRI
216 #else
217 mrs r0, PRIMASK
218 #endif
219 }
220 #endif
221 #else
222 #ifdef MCAL_PLATFORM_S12
Port_schm_read_msr(void)223 ASM_KEYWORD uint32 Port_schm_read_msr(void)
224 {
225 tfr ccr, d6
226 }
227 #else
Port_schm_read_msr(void)228 ASM_KEYWORD uint32 Port_schm_read_msr(void)
229 {
230 mfmsr r3
231 }
232 #endif
233 #endif
234 #endif /*#ifdef GHS||CW*/
235
236 #ifdef _DIABDATA_C_S32ZE_
237 /**
238 * @brief This function returns the MSR register value (32 bits).
239 * @details This function returns the MSR register value (32 bits).
240 *
241 * @param[in] void No input parameters
242 * @return uint32 msr This function returns the MSR register value (32 bits).
243 *
244 * @pre None
245 * @post None
246 *
247 */
248 #ifdef MCAL_PLATFORM_ARM
Port_schm_read_msr(void)249 uint32 Port_schm_read_msr(void)
250 {
251 register uint32 reg_tmp;
252 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
253 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
254 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
255 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
256 #else
257 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
258 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
259 #else
260 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
261 #endif
262 #endif
263 return (uint32)reg_tmp;
264 }
265 #else
Port_schm_read_msr(void)266 ASM_KEYWORD uint32 Port_schm_read_msr(void)
267 {
268 mfmsr r3
269 }
270 #endif /* MCAL_PLATFORM_ARM */
271
272 #endif /* _DIABDATA_C_S32ZE_*/
273
274 #ifdef _COSMIC_C_S32ZE_
275 /*================================================================================================*/
276 /**
277 * @brief This function returns the MSR register value (32 bits).
278 * @details This function returns the MSR register value (32 bits).
279 *
280 * @param[in] void No input parameters
281 * @return uint32 msr This function returns the MSR register value (32 bits).
282 *
283 * @pre None
284 * @post None
285 *
286 */
287
288 #ifdef MCAL_PLATFORM_S12
289 #define Port_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
290 #else
291 #define Port_schm_read_msr() ASM_KEYWORD("mfmsr r3")
292 #endif
293
294 #endif /*Cosmic compiler only*/
295
296
297 #ifdef _HITECH_C_S32ZE_
298 /*================================================================================================*/
299 /**
300 * @brief This function returns the MSR register value (32 bits).
301 * @details This function returns the MSR register value (32 bits).
302 *
303 * @param[in] void No input parameters
304 * @return uint32 msr This function returns the MSR register value (32 bits).
305 *
306 * @pre None
307 * @post None
308 *
309 */
Port_schm_read_msr(void)310 uint32 Port_schm_read_msr(void)
311 {
312 uint32 result;
313 __asm volatile("mfmsr %0" : "=r" (result) :);
314 return result;
315 }
316
317 #endif /*HighTec compiler only*/
318 /*================================================================================================*/
319 #ifdef _LINARO_C_S32ZE_
320 /**
321 * @brief This function returns the MSR register value (32 bits).
322 * @details This function returns the MSR register value (32 bits).
323 *
324 * @param[in] void No input parameters
325 * @return uint32 msr This function returns the MSR register value (32 bits).
326 *
327 * @pre None
328 * @post None
329 *
330 */
Port_schm_read_msr(void)331 uint32 Port_schm_read_msr(void)
332 {
333 register uint32 reg_tmp;
334 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
335 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
336 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
337 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
338 #else
339 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
340 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
341 #else
342 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
343 #endif
344 #endif
345 return (uint32)reg_tmp;
346 }
347 #endif /* _LINARO_C_S32ZE_*/
348 /*================================================================================================*/
349
350 #ifdef _ARM_DS5_C_S32ZE_
351 /**
352 * @brief This function returns the MSR register value (32 bits).
353 * @details This function returns the MSR register value (32 bits).
354 *
355 * @param[in] void No input parameters
356 * @return uint32 msr This function returns the MSR register value (32 bits).
357 *
358 * @pre None
359 * @post None
360 *
361 */
Port_schm_read_msr(void)362 uint32 Port_schm_read_msr(void)
363 {
364 register uint32 reg_tmp;
365 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
366 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
367 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
368 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
369 #else
370 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
371 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
372 #else
373 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
374 #endif
375 #endif
376 return (uint32)reg_tmp;
377 }
378 #endif /* _ARM_DS5_C_S32ZE_ */
379
380 #ifdef _IAR_C_S32ZE_
381 /**
382 * @brief This function returns the MSR register value (32 bits).
383 * @details This function returns the MSR register value (32 bits).
384 *
385 * @param[in] void No input parameters
386 * @return uint32 msr This function returns the MSR register value (32 bits).
387 *
388 * @pre None
389 * @post None
390 *
391 */
Port_schm_read_msr(void)392 uint32 Port_schm_read_msr(void)
393 {
394 register uint32 reg_tmp;
395
396 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
397 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
398 #else
399 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
400 #endif
401
402 return (uint32)reg_tmp;
403 }
404 #endif /* _IAR_C_S32ZE_ */
405
406 #define RTE_STOP_SEC_CODE
407 #include "Rte_MemMap.h"
408
409 /*==================================================================================================
410 * GLOBAL FUNCTIONS
411 ==================================================================================================*/
412 #define RTE_START_SEC_CODE
413 #include "Rte_MemMap.h"
414
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_00(void)415 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_00(void)
416 {
417 uint32 msr;
418 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
419
420 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId])
421 {
422 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
423 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
424 #else
425 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
426 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
427 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
428 {
429 OsIf_SuspendAllInterrupts();
430 #ifdef _ARM_DS5_C_S32ZE_
431 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
432 #endif
433 }
434 msr_PORT_EXCLUSIVE_AREA_00[u32CoreId] = msr;
435 }
436 reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId]++;
437 }
438
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_00(void)439 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_00(void)
440 {
441 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
442
443 reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId]--;
444 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
445 {
446 OsIf_ResumeAllInterrupts();
447 #ifdef _ARM_DS5_C_S32ZE_
448 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
449 #endif
450 }
451 }
452
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_01(void)453 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_01(void)
454 {
455 uint32 msr;
456 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
457
458 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId])
459 {
460 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
461 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
462 #else
463 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
464 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
465 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
466 {
467 OsIf_SuspendAllInterrupts();
468 #ifdef _ARM_DS5_C_S32ZE_
469 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
470 #endif
471 }
472 msr_PORT_EXCLUSIVE_AREA_01[u32CoreId] = msr;
473 }
474 reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId]++;
475 }
476
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_01(void)477 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_01(void)
478 {
479 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
480
481 reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId]--;
482 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
483 {
484 OsIf_ResumeAllInterrupts();
485 #ifdef _ARM_DS5_C_S32ZE_
486 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
487 #endif
488 }
489 }
490
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_02(void)491 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_02(void)
492 {
493 uint32 msr;
494 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
495
496 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId])
497 {
498 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
499 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
500 #else
501 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
502 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
503 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
504 {
505 OsIf_SuspendAllInterrupts();
506 #ifdef _ARM_DS5_C_S32ZE_
507 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
508 #endif
509 }
510 msr_PORT_EXCLUSIVE_AREA_02[u32CoreId] = msr;
511 }
512 reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId]++;
513 }
514
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_02(void)515 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_02(void)
516 {
517 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
518
519 reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId]--;
520 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
521 {
522 OsIf_ResumeAllInterrupts();
523 #ifdef _ARM_DS5_C_S32ZE_
524 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
525 #endif
526 }
527 }
528
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_03(void)529 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_03(void)
530 {
531 uint32 msr;
532 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
533
534 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId])
535 {
536 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
537 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
538 #else
539 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
540 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
541 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
542 {
543 OsIf_SuspendAllInterrupts();
544 #ifdef _ARM_DS5_C_S32ZE_
545 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
546 #endif
547 }
548 msr_PORT_EXCLUSIVE_AREA_03[u32CoreId] = msr;
549 }
550 reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId]++;
551 }
552
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_03(void)553 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_03(void)
554 {
555 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
556
557 reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId]--;
558 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
559 {
560 OsIf_ResumeAllInterrupts();
561 #ifdef _ARM_DS5_C_S32ZE_
562 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
563 #endif
564 }
565 }
566
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_04(void)567 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_04(void)
568 {
569 uint32 msr;
570 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
571
572 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId])
573 {
574 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
575 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
576 #else
577 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
578 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
579 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
580 {
581 OsIf_SuspendAllInterrupts();
582 #ifdef _ARM_DS5_C_S32ZE_
583 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
584 #endif
585 }
586 msr_PORT_EXCLUSIVE_AREA_04[u32CoreId] = msr;
587 }
588 reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId]++;
589 }
590
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_04(void)591 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_04(void)
592 {
593 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
594
595 reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId]--;
596 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
597 {
598 OsIf_ResumeAllInterrupts();
599 #ifdef _ARM_DS5_C_S32ZE_
600 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
601 #endif
602 }
603 }
604
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_05(void)605 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_05(void)
606 {
607 uint32 msr;
608 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
609
610 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId])
611 {
612 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
613 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
614 #else
615 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
616 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
617 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
618 {
619 OsIf_SuspendAllInterrupts();
620 #ifdef _ARM_DS5_C_S32ZE_
621 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
622 #endif
623 }
624 msr_PORT_EXCLUSIVE_AREA_05[u32CoreId] = msr;
625 }
626 reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId]++;
627 }
628
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_05(void)629 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_05(void)
630 {
631 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
632
633 reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId]--;
634 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
635 {
636 OsIf_ResumeAllInterrupts();
637 #ifdef _ARM_DS5_C_S32ZE_
638 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
639 #endif
640 }
641 }
642
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_06(void)643 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_06(void)
644 {
645 uint32 msr;
646 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
647
648 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId])
649 {
650 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
651 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
652 #else
653 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
654 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
655 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
656 {
657 OsIf_SuspendAllInterrupts();
658 #ifdef _ARM_DS5_C_S32ZE_
659 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
660 #endif
661 }
662 msr_PORT_EXCLUSIVE_AREA_06[u32CoreId] = msr;
663 }
664 reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId]++;
665 }
666
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_06(void)667 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_06(void)
668 {
669 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
670
671 reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId]--;
672 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
673 {
674 OsIf_ResumeAllInterrupts();
675 #ifdef _ARM_DS5_C_S32ZE_
676 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
677 #endif
678 }
679 }
680
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_07(void)681 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_07(void)
682 {
683 uint32 msr;
684 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
685
686 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId])
687 {
688 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
689 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
690 #else
691 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
692 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
693 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
694 {
695 OsIf_SuspendAllInterrupts();
696 #ifdef _ARM_DS5_C_S32ZE_
697 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
698 #endif
699 }
700 msr_PORT_EXCLUSIVE_AREA_07[u32CoreId] = msr;
701 }
702 reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId]++;
703 }
704
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_07(void)705 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_07(void)
706 {
707 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
708
709 reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId]--;
710 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
711 {
712 OsIf_ResumeAllInterrupts();
713 #ifdef _ARM_DS5_C_S32ZE_
714 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
715 #endif
716 }
717 }
718
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_08(void)719 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_08(void)
720 {
721 uint32 msr;
722 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
723
724 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId])
725 {
726 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
727 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
728 #else
729 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
730 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
731 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
732 {
733 OsIf_SuspendAllInterrupts();
734 #ifdef _ARM_DS5_C_S32ZE_
735 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
736 #endif
737 }
738 msr_PORT_EXCLUSIVE_AREA_08[u32CoreId] = msr;
739 }
740 reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId]++;
741 }
742
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_08(void)743 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_08(void)
744 {
745 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
746
747 reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId]--;
748 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
749 {
750 OsIf_ResumeAllInterrupts();
751 #ifdef _ARM_DS5_C_S32ZE_
752 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
753 #endif
754 }
755 }
756
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_09(void)757 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_09(void)
758 {
759 uint32 msr;
760 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
761
762 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId])
763 {
764 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
765 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
766 #else
767 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
768 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
769 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
770 {
771 OsIf_SuspendAllInterrupts();
772 #ifdef _ARM_DS5_C_S32ZE_
773 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
774 #endif
775 }
776 msr_PORT_EXCLUSIVE_AREA_09[u32CoreId] = msr;
777 }
778 reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId]++;
779 }
780
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_09(void)781 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_09(void)
782 {
783 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
784
785 reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId]--;
786 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
787 {
788 OsIf_ResumeAllInterrupts();
789 #ifdef _ARM_DS5_C_S32ZE_
790 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
791 #endif
792 }
793 }
794
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_10(void)795 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_10(void)
796 {
797 uint32 msr;
798 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
799
800 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId])
801 {
802 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
803 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
804 #else
805 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
806 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
807 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
808 {
809 OsIf_SuspendAllInterrupts();
810 #ifdef _ARM_DS5_C_S32ZE_
811 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
812 #endif
813 }
814 msr_PORT_EXCLUSIVE_AREA_10[u32CoreId] = msr;
815 }
816 reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId]++;
817 }
818
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_10(void)819 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_10(void)
820 {
821 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
822
823 reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId]--;
824 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
825 {
826 OsIf_ResumeAllInterrupts();
827 #ifdef _ARM_DS5_C_S32ZE_
828 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
829 #endif
830 }
831 }
832
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_11(void)833 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_11(void)
834 {
835 uint32 msr;
836 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
837
838 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId])
839 {
840 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
841 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
842 #else
843 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
844 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
845 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
846 {
847 OsIf_SuspendAllInterrupts();
848 #ifdef _ARM_DS5_C_S32ZE_
849 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
850 #endif
851 }
852 msr_PORT_EXCLUSIVE_AREA_11[u32CoreId] = msr;
853 }
854 reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId]++;
855 }
856
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_11(void)857 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_11(void)
858 {
859 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
860
861 reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId]--;
862 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
863 {
864 OsIf_ResumeAllInterrupts();
865 #ifdef _ARM_DS5_C_S32ZE_
866 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
867 #endif
868 }
869 }
870
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_12(void)871 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_12(void)
872 {
873 uint32 msr;
874 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
875
876 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId])
877 {
878 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
879 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
880 #else
881 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
882 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
883 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
884 {
885 OsIf_SuspendAllInterrupts();
886 #ifdef _ARM_DS5_C_S32ZE_
887 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
888 #endif
889 }
890 msr_PORT_EXCLUSIVE_AREA_12[u32CoreId] = msr;
891 }
892 reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId]++;
893 }
894
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_12(void)895 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_12(void)
896 {
897 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
898
899 reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId]--;
900 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
901 {
902 OsIf_ResumeAllInterrupts();
903 #ifdef _ARM_DS5_C_S32ZE_
904 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
905 #endif
906 }
907 }
908
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_13(void)909 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_13(void)
910 {
911 uint32 msr;
912 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
913
914 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId])
915 {
916 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
917 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
918 #else
919 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
920 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
921 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
922 {
923 OsIf_SuspendAllInterrupts();
924 #ifdef _ARM_DS5_C_S32ZE_
925 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
926 #endif
927 }
928 msr_PORT_EXCLUSIVE_AREA_13[u32CoreId] = msr;
929 }
930 reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId]++;
931 }
932
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_13(void)933 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_13(void)
934 {
935 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
936
937 reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId]--;
938 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
939 {
940 OsIf_ResumeAllInterrupts();
941 #ifdef _ARM_DS5_C_S32ZE_
942 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
943 #endif
944 }
945 }
946
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_14(void)947 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_14(void)
948 {
949 uint32 msr;
950 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
951
952 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId])
953 {
954 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
955 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
956 #else
957 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
958 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
959 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
960 {
961 OsIf_SuspendAllInterrupts();
962 #ifdef _ARM_DS5_C_S32ZE_
963 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
964 #endif
965 }
966 msr_PORT_EXCLUSIVE_AREA_14[u32CoreId] = msr;
967 }
968 reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId]++;
969 }
970
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_14(void)971 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_14(void)
972 {
973 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
974
975 reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId]--;
976 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
977 {
978 OsIf_ResumeAllInterrupts();
979 #ifdef _ARM_DS5_C_S32ZE_
980 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
981 #endif
982 }
983 }
984
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_15(void)985 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_15(void)
986 {
987 uint32 msr;
988 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
989
990 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId])
991 {
992 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
993 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
994 #else
995 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
996 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
997 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
998 {
999 OsIf_SuspendAllInterrupts();
1000 #ifdef _ARM_DS5_C_S32ZE_
1001 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1002 #endif
1003 }
1004 msr_PORT_EXCLUSIVE_AREA_15[u32CoreId] = msr;
1005 }
1006 reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId]++;
1007 }
1008
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_15(void)1009 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_15(void)
1010 {
1011 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1012
1013 reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId]--;
1014 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
1015 {
1016 OsIf_ResumeAllInterrupts();
1017 #ifdef _ARM_DS5_C_S32ZE_
1018 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1019 #endif
1020 }
1021 }
1022
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_16(void)1023 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_16(void)
1024 {
1025 uint32 msr;
1026 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1027
1028 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId])
1029 {
1030 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1031 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1032 #else
1033 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1034 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1035 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1036 {
1037 OsIf_SuspendAllInterrupts();
1038 #ifdef _ARM_DS5_C_S32ZE_
1039 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1040 #endif
1041 }
1042 msr_PORT_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1043 }
1044 reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId]++;
1045 }
1046
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_16(void)1047 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_16(void)
1048 {
1049 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1050
1051 reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId]--;
1052 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1053 {
1054 OsIf_ResumeAllInterrupts();
1055 #ifdef _ARM_DS5_C_S32ZE_
1056 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1057 #endif
1058 }
1059 }
1060
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_17(void)1061 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_17(void)
1062 {
1063 uint32 msr;
1064 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1065
1066 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId])
1067 {
1068 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1069 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1070 #else
1071 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1072 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1073 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1074 {
1075 OsIf_SuspendAllInterrupts();
1076 #ifdef _ARM_DS5_C_S32ZE_
1077 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1078 #endif
1079 }
1080 msr_PORT_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1081 }
1082 reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId]++;
1083 }
1084
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_17(void)1085 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_17(void)
1086 {
1087 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1088
1089 reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId]--;
1090 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1091 {
1092 OsIf_ResumeAllInterrupts();
1093 #ifdef _ARM_DS5_C_S32ZE_
1094 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1095 #endif
1096 }
1097 }
1098
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_18(void)1099 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_18(void)
1100 {
1101 uint32 msr;
1102 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1103
1104 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId])
1105 {
1106 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1107 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1108 #else
1109 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1110 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1111 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1112 {
1113 OsIf_SuspendAllInterrupts();
1114 #ifdef _ARM_DS5_C_S32ZE_
1115 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1116 #endif
1117 }
1118 msr_PORT_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1119 }
1120 reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId]++;
1121 }
1122
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_18(void)1123 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_18(void)
1124 {
1125 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1126
1127 reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId]--;
1128 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1129 {
1130 OsIf_ResumeAllInterrupts();
1131 #ifdef _ARM_DS5_C_S32ZE_
1132 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1133 #endif
1134 }
1135 }
1136
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_19(void)1137 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_19(void)
1138 {
1139 uint32 msr;
1140 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1141
1142 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId])
1143 {
1144 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1145 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1146 #else
1147 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1148 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1149 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1150 {
1151 OsIf_SuspendAllInterrupts();
1152 #ifdef _ARM_DS5_C_S32ZE_
1153 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1154 #endif
1155 }
1156 msr_PORT_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1157 }
1158 reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId]++;
1159 }
1160
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_19(void)1161 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_19(void)
1162 {
1163 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1164
1165 reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId]--;
1166 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1167 {
1168 OsIf_ResumeAllInterrupts();
1169 #ifdef _ARM_DS5_C_S32ZE_
1170 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1171 #endif
1172 }
1173 }
1174
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_20(void)1175 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_20(void)
1176 {
1177 uint32 msr;
1178 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1179
1180 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId])
1181 {
1182 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1183 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1184 #else
1185 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1186 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1187 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1188 {
1189 OsIf_SuspendAllInterrupts();
1190 #ifdef _ARM_DS5_C_S32ZE_
1191 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1192 #endif
1193 }
1194 msr_PORT_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1195 }
1196 reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId]++;
1197 }
1198
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_20(void)1199 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_20(void)
1200 {
1201 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1202
1203 reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId]--;
1204 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1205 {
1206 OsIf_ResumeAllInterrupts();
1207 #ifdef _ARM_DS5_C_S32ZE_
1208 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1209 #endif
1210 }
1211 }
1212
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_21(void)1213 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_21(void)
1214 {
1215 uint32 msr;
1216 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1217
1218 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId])
1219 {
1220 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1221 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1222 #else
1223 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1224 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1225 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1226 {
1227 OsIf_SuspendAllInterrupts();
1228 #ifdef _ARM_DS5_C_S32ZE_
1229 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1230 #endif
1231 }
1232 msr_PORT_EXCLUSIVE_AREA_21[u32CoreId] = msr;
1233 }
1234 reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId]++;
1235 }
1236
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_21(void)1237 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_21(void)
1238 {
1239 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1240
1241 reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId]--;
1242 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
1243 {
1244 OsIf_ResumeAllInterrupts();
1245 #ifdef _ARM_DS5_C_S32ZE_
1246 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1247 #endif
1248 }
1249 }
1250
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_22(void)1251 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_22(void)
1252 {
1253 uint32 msr;
1254 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1255
1256 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId])
1257 {
1258 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1259 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1260 #else
1261 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1262 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1263 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1264 {
1265 OsIf_SuspendAllInterrupts();
1266 #ifdef _ARM_DS5_C_S32ZE_
1267 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1268 #endif
1269 }
1270 msr_PORT_EXCLUSIVE_AREA_22[u32CoreId] = msr;
1271 }
1272 reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId]++;
1273 }
1274
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_22(void)1275 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_22(void)
1276 {
1277 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1278
1279 reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId]--;
1280 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
1281 {
1282 OsIf_ResumeAllInterrupts();
1283 #ifdef _ARM_DS5_C_S32ZE_
1284 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1285 #endif
1286 }
1287 }
1288
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_23(void)1289 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_23(void)
1290 {
1291 uint32 msr;
1292 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1293
1294 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId])
1295 {
1296 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1297 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1298 #else
1299 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1300 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1301 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1302 {
1303 OsIf_SuspendAllInterrupts();
1304 #ifdef _ARM_DS5_C_S32ZE_
1305 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1306 #endif
1307 }
1308 msr_PORT_EXCLUSIVE_AREA_23[u32CoreId] = msr;
1309 }
1310 reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId]++;
1311 }
1312
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_23(void)1313 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_23(void)
1314 {
1315 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1316
1317 reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId]--;
1318 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
1319 {
1320 OsIf_ResumeAllInterrupts();
1321 #ifdef _ARM_DS5_C_S32ZE_
1322 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1323 #endif
1324 }
1325 }
1326
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_24(void)1327 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_24(void)
1328 {
1329 uint32 msr;
1330 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1331
1332 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId])
1333 {
1334 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1335 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1336 #else
1337 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1338 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1339 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1340 {
1341 OsIf_SuspendAllInterrupts();
1342 #ifdef _ARM_DS5_C_S32ZE_
1343 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1344 #endif
1345 }
1346 msr_PORT_EXCLUSIVE_AREA_24[u32CoreId] = msr;
1347 }
1348 reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId]++;
1349 }
1350
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_24(void)1351 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_24(void)
1352 {
1353 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1354
1355 reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId]--;
1356 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId])) /*if interrupts were enabled*/
1357 {
1358 OsIf_ResumeAllInterrupts();
1359 #ifdef _ARM_DS5_C_S32ZE_
1360 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1361 #endif
1362 }
1363 }
1364
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_25(void)1365 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_25(void)
1366 {
1367 uint32 msr;
1368 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1369
1370 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId])
1371 {
1372 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1373 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1374 #else
1375 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1376 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1377 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1378 {
1379 OsIf_SuspendAllInterrupts();
1380 #ifdef _ARM_DS5_C_S32ZE_
1381 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1382 #endif
1383 }
1384 msr_PORT_EXCLUSIVE_AREA_25[u32CoreId] = msr;
1385 }
1386 reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId]++;
1387 }
1388
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_25(void)1389 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_25(void)
1390 {
1391 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1392
1393 reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId]--;
1394 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId])) /*if interrupts were enabled*/
1395 {
1396 OsIf_ResumeAllInterrupts();
1397 #ifdef _ARM_DS5_C_S32ZE_
1398 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1399 #endif
1400 }
1401 }
1402
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_26(void)1403 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_26(void)
1404 {
1405 uint32 msr;
1406 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1407
1408 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId])
1409 {
1410 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1411 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1412 #else
1413 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1414 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1415 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1416 {
1417 OsIf_SuspendAllInterrupts();
1418 #ifdef _ARM_DS5_C_S32ZE_
1419 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1420 #endif
1421 }
1422 msr_PORT_EXCLUSIVE_AREA_26[u32CoreId] = msr;
1423 }
1424 reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId]++;
1425 }
1426
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_26(void)1427 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_26(void)
1428 {
1429 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1430
1431 reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId]--;
1432 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId])) /*if interrupts were enabled*/
1433 {
1434 OsIf_ResumeAllInterrupts();
1435 #ifdef _ARM_DS5_C_S32ZE_
1436 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1437 #endif
1438 }
1439 }
1440
SchM_Enter_Port_PORT_EXCLUSIVE_AREA_27(void)1441 void SchM_Enter_Port_PORT_EXCLUSIVE_AREA_27(void)
1442 {
1443 uint32 msr;
1444 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1445
1446 if(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId])
1447 {
1448 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1449 msr = OsIf_Trusted_Call_Return(Port_schm_read_msr);
1450 #else
1451 msr = Port_schm_read_msr(); /*read MSR (to store interrupts state)*/
1452 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1453 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1454 {
1455 OsIf_SuspendAllInterrupts();
1456 #ifdef _ARM_DS5_C_S32ZE_
1457 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1458 #endif
1459 }
1460 msr_PORT_EXCLUSIVE_AREA_27[u32CoreId] = msr;
1461 }
1462 reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId]++;
1463 }
1464
SchM_Exit_Port_PORT_EXCLUSIVE_AREA_27(void)1465 void SchM_Exit_Port_PORT_EXCLUSIVE_AREA_27(void)
1466 {
1467 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1468
1469 reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId]--;
1470 if ((ISR_ON(msr_PORT_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId])) /*if interrupts were enabled*/
1471 {
1472 OsIf_ResumeAllInterrupts();
1473 #ifdef _ARM_DS5_C_S32ZE_
1474 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1475 #endif
1476 }
1477 }
1478
1479
1480 #ifdef MCAL_TESTING_ENVIRONMENT
1481 /**
1482 @brief This function checks that all entered exclusive areas were also exited.
1483 @details This function checks that all entered exclusive areas were also exited. The check
1484 is done by verifying that all reentry_guard_* static variables are back to the
1485 zero value.
1486
1487 @param[in] void No input parameters
1488 @return void This function does not return a value. Test asserts are used instead.
1489
1490 @pre None
1491 @post None
1492
1493 @remarks Covers
1494 @remarks Implements
1495 */
SchM_Check_port(void)1496 void SchM_Check_port(void)
1497 {
1498 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1499
1500 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId]);
1501 reentry_guard_PORT_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_00 for the next test in the suite*/
1502
1503 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId]);
1504 reentry_guard_PORT_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_01 for the next test in the suite*/
1505
1506 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId]);
1507 reentry_guard_PORT_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_02 for the next test in the suite*/
1508
1509 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId]);
1510 reentry_guard_PORT_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_03 for the next test in the suite*/
1511
1512 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId]);
1513 reentry_guard_PORT_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_04 for the next test in the suite*/
1514
1515 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId]);
1516 reentry_guard_PORT_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_05 for the next test in the suite*/
1517
1518 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId]);
1519 reentry_guard_PORT_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_06 for the next test in the suite*/
1520
1521 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId]);
1522 reentry_guard_PORT_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_07 for the next test in the suite*/
1523
1524 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId]);
1525 reentry_guard_PORT_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_08 for the next test in the suite*/
1526
1527 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId]);
1528 reentry_guard_PORT_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_09 for the next test in the suite*/
1529
1530 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId]);
1531 reentry_guard_PORT_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_10 for the next test in the suite*/
1532
1533 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId]);
1534 reentry_guard_PORT_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_11 for the next test in the suite*/
1535
1536 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId]);
1537 reentry_guard_PORT_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_12 for the next test in the suite*/
1538
1539 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId]);
1540 reentry_guard_PORT_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_13 for the next test in the suite*/
1541
1542 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId]);
1543 reentry_guard_PORT_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_14 for the next test in the suite*/
1544
1545 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId]);
1546 reentry_guard_PORT_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_15 for the next test in the suite*/
1547
1548 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId]);
1549 reentry_guard_PORT_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_16 for the next test in the suite*/
1550
1551 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId]);
1552 reentry_guard_PORT_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_17 for the next test in the suite*/
1553
1554 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId]);
1555 reentry_guard_PORT_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_18 for the next test in the suite*/
1556
1557 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId]);
1558 reentry_guard_PORT_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_19 for the next test in the suite*/
1559
1560 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId]);
1561 reentry_guard_PORT_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_20 for the next test in the suite*/
1562
1563 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId]);
1564 reentry_guard_PORT_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_21 for the next test in the suite*/
1565
1566 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId]);
1567 reentry_guard_PORT_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_22 for the next test in the suite*/
1568
1569 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId]);
1570 reentry_guard_PORT_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_23 for the next test in the suite*/
1571
1572 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId]);
1573 reentry_guard_PORT_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_24 for the next test in the suite*/
1574
1575 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId]);
1576 reentry_guard_PORT_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_25 for the next test in the suite*/
1577
1578 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId]);
1579 reentry_guard_PORT_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_26 for the next test in the suite*/
1580
1581 EU_ASSERT(0UL == reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId]);
1582 reentry_guard_PORT_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_PORT_EXCLUSIVE_AREA_27 for the next test in the suite*/
1583
1584
1585 }
1586 #endif /*MCAL_TESTING_ENVIRONMENT*/
1587
1588 #define RTE_STOP_SEC_CODE
1589 #include "Rte_MemMap.h"
1590
1591 #ifdef __cplusplus
1592 }
1593 #endif
1594
1595 /** @} */
1596
