| /Zephyr-latest/dts/arm/st/f0/ |
| D | stm32f0.dtsi | 108 rctl: reset-controller { label
109 compatible = "st,stm32-rcc-rctl";
177 resets = <&rctl STM32_RESET(APB2, 14U)>;
237 resets = <&rctl STM32_RESET(APB2, 11U)>;
254 resets = <&rctl STM32_RESET(APB1, 1U)>;
276 resets = <&rctl STM32_RESET(APB1, 8U)>;
298 resets = <&rctl STM32_RESET(APB2, 17U)>;
320 resets = <&rctl STM32_RESET(APB2, 18U)>;
|
| D | stm32f042.dtsi | 28 resets = <&rctl STM32_RESET(APB1, 17U)>;
55 resets = <&rctl STM32_RESET(APB2, 16U)>;
|
| /Zephyr-latest/dts/arm/st/l4/ |
| D | stm32l451.dtsi | 94 resets = <&rctl STM32_RESET(APB1L, 18U)>;
103 resets = <&rctl STM32_RESET(APB1L, 19U)>;
112 resets = <&rctl STM32_RESET(APB1L, 1U)>;
152 resets = <&rctl STM32_RESET(APB2, 10U)>;
|
| D | stm32l431.dtsi | 84 resets = <&rctl STM32_RESET(APB1L, 18U)>;
93 resets = <&rctl STM32_RESET(APB1L, 5U)>;
119 resets = <&rctl STM32_RESET(APB2, 10U)>;
|
| D | stm32l4.dtsi | 141 rctl: reset-controller { label
142 compatible = "st,stm32-rcc-rctl";
219 resets = <&rctl STM32_RESET(APB2, 14U)>;
228 resets = <&rctl STM32_RESET(APB1L, 17U)>;
237 resets = <&rctl STM32_RESET(APB1H, 0U)>;
291 resets = <&rctl STM32_RESET(APB2, 11U)>;
308 resets = <&rctl STM32_RESET(APB1L, 0U)>;
330 resets = <&rctl STM32_RESET(APB1L, 4U)>;
346 resets = <&rctl STM32_RESET(APB2, 16U)>;
368 resets = <&rctl STM32_RESET(APB2, 17U)>;
|
| D | stm32l422.dtsi | 17 resets = <&rctl STM32_RESET(AHB2, 16U)>;
|
| D | stm32l462.dtsi | 17 resets = <&rctl STM32_RESET(AHB2, 16U)>;
|
| D | stm32l486.dtsi | 17 resets = <&rctl STM32_RESET(AHB2, 16U)>;
|
| D | stm32l4a6.dtsi | 17 resets = <&rctl STM32_RESET(AHB2, 16U)>;
|
| D | stm32l4q5.dtsi | 17 resets = <&rctl STM32_RESET(AHB2, 16U)>;
|
| D | stm32l4s5.dtsi | 17 resets = <&rctl STM32_RESET(AHB2, 16U)>;
|
| /Zephyr-latest/dts/arm/st/g0/ |
| D | stm32g0b0.dtsi | 27 resets = <&rctl STM32_RESET(APB1L, 8U)>;
36 resets = <&rctl STM32_RESET(APB1L, 9U)>;
45 resets = <&rctl STM32_RESET(APB1L, 2U)>;
|
| D | stm32g0_crypt.dtsi | 17 resets = <&rctl STM32_RESET(AHB1, 16U)>;
|
| /Zephyr-latest/dts/arm/gd/gd32f3x0/ |
| D | gd32f350.dtsi | 16 resets = <&rctl GD32_RESET_DAC>;
|
| /Zephyr-latest/dts/arm/st/wba/ |
| D | stm32wba.dtsi | 146 rctl: reset-controller { label
147 compatible = "st,stm32-rcc-rctl";
238 resets = <&rctl STM32_RESET(APB2, 14U)>;
247 resets = <&rctl STM32_RESET(APB1L, 17U)>;
256 resets = <&rctl STM32_RESET(APB7, 6U)>;
309 resets = <&rctl STM32_RESET(APB2, 11U)>;
331 resets = <&rctl STM32_RESET(APB1L, 0U)>;
353 resets = <&rctl STM32_RESET(APB1L, 1U)>;
375 resets = <&rctl STM32_RESET(APB2, 17U)>;
396 resets = <&rctl STM32_RESET(APB2, 18U)>;
|
| /Zephyr-latest/dts/arm/st/h5/ |
| D | stm32h5.dtsi | 155 rctl: reset-controller { label
156 compatible = "st,stm32-rcc-rctl";
255 resets = <&rctl STM32_RESET(APB2, 14U)>;
264 resets = <&rctl STM32_RESET(APB1L, 17U)>;
273 resets = <&rctl STM32_RESET(APB1L, 18U)>;
282 resets = <&rctl STM32_RESET(APB3, 6U)>;
341 resets = <&rctl STM32_RESET(APB2, 11U)>;
357 resets = <&rctl STM32_RESET(APB1L, 0U)>;
378 resets = <&rctl STM32_RESET(APB1L, 1U)>;
399 resets = <&rctl STM32_RESET(APB1L, 4U)>;
[all …]
|
| D | stm32h563.dtsi | 18 resets = <&rctl STM32_RESET(AHB4, 12U)>;
|
| /Zephyr-latest/dts/arm/st/g4/ |
| D | stm32g491.dtsi | 28 resets = <&rctl STM32_RESET(APB2, 20U)>;
76 resets = <&rctl STM32_RESET(APB1L, 20U)>;
|
| /Zephyr-latest/dts/arm/st/f4/ |
| D | stm32f423.dtsi | 17 resets = <&rctl STM32_RESET(AHB2, 4U)>;
|
| D | stm32f417.dtsi | 17 resets = <&rctl STM32_RESET(AHB2, 4U)>;
|
| D | stm32f415.dtsi | 17 resets = <&rctl STM32_RESET(AHB2, 4U)>;
|
| /Zephyr-latest/dts/arm/st/l5/ |
| D | stm32l562.dtsi | 17 resets = <&rctl STM32_RESET(AHB2, 16U)>;
|
| /Zephyr-latest/dts/arm/st/h7/ |
| D | stm32h730.dtsi | 17 resets = <&rctl STM32_RESET(AHB2, 4U)>;
|
| D | stm32h723.dtsi | 31 resets = <&rctl STM32_RESET(APB2, 6U)>;
40 resets = <&rctl STM32_RESET(APB2, 7U)>;
92 resets = <&rctl STM32_RESET(APB3, 4U)>;
143 resets = <&rctl STM32_RESET(APB1H, 24U)>;
165 resets = <&rctl STM32_RESET(APB1H, 25U)>;
|
| /Zephyr-latest/dts/arm/st/u0/ |
| D | stm32u083.dtsi | 17 resets = <&rctl STM32_RESET(APB1L, 12U)>;
|
