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/Zephyr-latest/boards/ezurio/bl653_dvk/
Dbl653_dvk.dts135 #io-channel-cells = <1>;
/Zephyr-latest/boards/ezurio/bl654_dvk/
Dbl654_dvk.dts133 #io-channel-cells = <1>;
/Zephyr-latest/boards/nordic/nrf52833dk/
Dnrf52833dk_nrf52820.dts102 channel-gpios = <&gpio0 13 PWM_POLARITY_INVERTED>;
/Zephyr-latest/dts/arm/st/f1/
Dstm32f105.dtsi61 #io-channel-cells = <1>;
/Zephyr-latest/boards/espressif/esp32s3_eye/
Desp32s3_eye_procpu.dts179 channel@0 {
/Zephyr-latest/drivers/pcie/endpoint/
Dpcie_ep_iproc.c484 .pl330_tx_chan_id = DT_INST_DMAS_CELL_BY_NAME(0, txdma, channel),
485 .pl330_rx_chan_id = DT_INST_DMAS_CELL_BY_NAME(0, rxdma, channel),
/Zephyr-latest/boards/nxp/mimxrt685_evk/
Dmimxrt685_evk_mimxrt685s_cm33.dts191 /* I2S receive channel */
203 /* I2S transmit channel */
/Zephyr-latest/dts/riscv/ite/
Dit82xx2.dtsi912 channel-switch-sel = <I2C_CHA_LOCATE>;
927 channel-switch-sel = <I2C_CHB_LOCATE>;
942 channel-switch-sel = <I2C_CHC_LOCATE>;
957 channel-switch-sel = <I2C_CHD_LOCATE>;
972 channel-switch-sel = <I2C_CHE_LOCATE>;
987 channel-switch-sel = <I2C_CHF_LOCATE>;
/Zephyr-latest/drivers/serial/
DKconfig.nrfx45 and hardware assisted required TIMER peripheral instance and PPI channel
/Zephyr-latest/dts/arm/adi/max32/
Dmax78002.dtsi72 channel-count = <17>;
/Zephyr-latest/dts/arm/gd/gd32f3x0/
Dgd32f3x0.dtsi92 #io-channel-cells = <1>;
/Zephyr-latest/dts/arm/gd/gd32l23x/
Dgd32l23x.dtsi104 #io-channel-cells = <1>;
/Zephyr-latest/boards/st/b_g474e_dpow1/
Db_g474e_dpow1.dts144 channel@8 {
/Zephyr-latest/drivers/adc/
DKconfig26 # just the channel identifier is sufficient.
/Zephyr-latest/boards/sipeed/longan_nano/doc/
Dindex.rst32 - 2 x ADC(10 channel)
/Zephyr-latest/modules/segger/
DKconfig49 prompt "Mode for pre-initialized terminal channel (buffer 0)"
/Zephyr-latest/boards/ite/it82xx2_evb/
Dit82xx2_evb.dts164 channel = <IT8XXX2_TACH_CHANNEL_A>;
/Zephyr-latest/boards/ite/it8xxx2_evb/
Dit8xxx2_evb.dts149 channel = <IT8XXX2_TACH_CHANNEL_A>;
/Zephyr-latest/samples/drivers/ipm/ipm_imx/
DREADME.rst20 or a single 128-bit channel respectively.
/Zephyr-latest/boards/phytec/phyboard_lyra/doc/
Dphyboard_lyra_am62xx_a53.rst65 This board configuration uses a single serial communication channel with the
/Zephyr-latest/boards/arm/fvp_baser_aemv8r/doc/
Daarch32.rst60 This board configuration uses a single serial communication channel with the
/Zephyr-latest/dts/arm/st/l4/
Dstm32l451.dtsi135 #io-channel-cells = <1>;
/Zephyr-latest/dts/arm/nuvoton/
Dm46x.dtsi576 #io-channel-cells = <1>;
589 #io-channel-cells = <1>;
602 #io-channel-cells = <1>;
/Zephyr-latest/boards/st/nucleo_wl55jc/doc/
Dnucleo_wl55jc.rst143 - 2x 16-bit 1-channel timer
144 - 1x 16-bit 4-channel timer (supporting motor control)
145 - 1x 32-bit 4-channel timer
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo3_blue.dtsi335 channel-count = <10>;
338 #io-channel-cells = <1>;

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