1.. zephyr:board:: nucleo_wl55jc 2 3Overview 4******** 5 6The NUCLEO-WL55JC STM32WL Nucleo-64 board provides an affordable and flexible 7way for users to try out new concepts and build prototypes with the STM32WL 8Series microcontroller, choosing from the various combinations of performance, 9power consumption, and features. 10 11- STM32WL55JC microcontroller multiprotocol LPWAN dual-core 32-bit 12 (Arm® Cortex®-M4/M0+ at 48 MHz) in UFBGA73 package featuring: 13 14 - Ultra-low-power MCU 15 - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®, 16 (G)FSK, (G)MSK, and BPSK modulations 17 - 256-Kbyte Flash memory and 64-Kbyte SRAM 18 19- 3 user LEDs 20- 3 user buttons and 1 reset push-button 21- 32.768 kHz LSE crystal oscillator 22- 32 MHz HSE on-board oscillator 23- Board connectors: 24 25 - USB with Micro-B 26 - MIPI debug connector 27 - ARDUINO Uno V3 expansion connector 28 - ST morpho extension pin headers for full access to all STM32WL I/Os 29 30- Delivered with SMA antenna 31- Flexible power-supply options: ST-LINK, USB VBUS, or external sources 32- On-board STLINK-V3 debugger/programmer with USB re-enumeration capability: 33 mass storage, Virtual COM port, and debug port 34- Comprehensive free software libraries and examples available with the 35 STM32CubeWL MCU Package 36- Support of a wide choice of Integrated Development Environments (IDEs) 37 including IAR Embedded Workbench®, MDK-ARM, and STM32CubeIDE 38- Suitable for rapid prototyping of end nodes based on LoRaWAN, Sigfox, wM-Bus, 39 and many other proprietary protocols 40- Fully open hardware platform 41 42 43More information about the board can be found at the `Nucleo WL55JC website`_. 44 45Hardware 46******** 47 48The STM32WL55JC long-range wireless and ultra-low-power devices embed a powerful 49and ultra-low-power LPWAN-compliant radio solution, enabling the following 50modulations: LoRa®, (G)FSK, (G)MSK, and BPSK 51It provides the following hardware capabilities: 52 53- Radio 54 55 - Frequency range: 150 MHz to 960 MHz 56 - Modulation: LoRa®, (G)FSK, (G)MSK and BPSK 57 - RX sensitivity: –123 dBm for 2-FSK(at 1.2 Kbit/s), –148 dBm for LoRa® 58 (at 10.4 kHz, spreading factor 12) 59 - Transmitter high output power, programmable up to +22 dBm 60 - Transmitter low output power, programmable up to +15 dBm 61 - Compliant with the following radio frequency regulations such as 62 ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 Part 15, 24, 90, 101 63 and the Japanese ARIB STD-T30, T-67, T-108 64 - Compatible with standardized or proprietary protocols such as LoRaWAN®, 65 Sigfox™, W-MBus and more (fully open wireless system-on-chip) 66 67- Core 68 69 - 32-bit Arm® Cortex®-M4 CPU 70 71 - Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state 72 execution from Flash memory, frequency up to 48 MHz, MPU 73 and DSP instructions 74 - 1.25 DMIPS/MHz (Dhrystone 2.1) 75 76 - 32-bit Arm®Cortex®-M0+ CPU 77 78 - Frequency up to 48 MHz, MPU 79 - 0.95 DMIPS/MHz (Dhrystone 2.1) 80 81- Security and identification 82 83 - Hardware encryption AES 256-bit 84 - True random number generator (RNG) 85 - Sector protection against read/write operations (PCROP, RDP, WRP) 86 - CRC calculation unit 87 - Unique device identifier (64-bit UID compliant with IEEE 802-2001 standard) 88 - 96-bit unique die identifier 89 - Hardware public key accelerator (PKA) 90 - Key management services 91 - Secure sub-GHz MAC layer 92 - Secure firmware update (SFU) 93 - Secure firmware install (SFI) 94 95- Supply and reset management 96 97 - High-efficiency embedded SMPS step-down converter 98 - SMPS to LDO smart switch 99 - Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds 100 - Ultra-low-power POR/PDR 101 - Programmable voltage detector (PVD) 102 - VBAT mode with RTC and 20x32-byte backup registers 103 104- Clock sources 105 106 - 32 MHz crystal oscillator 107 - TCXO support: programmable supply voltage 108 - 32 kHz oscillator for RTC with calibration 109 - High-speed internal 16 MHz factory trimmed RC (± 1 %) 110 - Internal low-power 32 kHz RC 111 - Internal multi-speed low-power 100 kHz to 48 MHz RC 112 - PLL for CPU, ADC and audio clocks 113 114- Memories 115 116 - 256-Kbyte Flash memory 117 - 64-Kbyte RAM 118 - 20x32-bit backup register 119 - Bootloader supporting USART and SPI interfaces 120 - OTA (over-the-air) firmware update capable 121 - Sector protection against read/write operations 122 123- Rich analog peripherals (down to 1.62 V) 124 125 - 12-bit ADC 2.5 Msps, up to 16 bits with hardware oversampling, 126 conversion range up to 3.6 V 127 - 12-bit DAC, low-power sample-and-hold 128 - 2x ultra-low-power comparators 129 130- System peripherals 131 132 - Mailbox and semaphores for communication between Cortex®-M4 and Cortex®-M0+ 133 firmware 134 135- Controllers 136 137 - 2x DMA controller (7 channels each) supporting ADC, DAC, SPI, I2C, LPUART, 138 USART, AES and timers 139 - 2x USART (ISO 7816, IrDA, SPI) 140 - 1x LPUART (low-power) 141 - 2x SPI 16 Mbit/s (1 over 2 supporting I2S) 142 - 3x I2C (SMBus/PMBus™) 143 - 2x 16-bit 1-channel timer 144 - 1x 16-bit 4-channel timer (supporting motor control) 145 - 1x 32-bit 4-channel timer 146 - 3x 16-bit ultra-low-power timer 147 - 1x RTC with 32-bit sub-second wakeup counter 148 - 1x independent SysTick 149 - 1x independent watchdog 150 - 1x window watchdog 151 152- Up to 43 I/Os, most 5 V-tolerant 153- Development support 154 - Serial-wire debug (SWD), JTAG 155 - Dual CPU cross trigger capabilities 156 157 158More information about STM32WL55JC can be found here: 159 160- `STM32WL55JC on www.st.com`_ 161- `STM32WL55JC datasheet`_ 162- `STM32WL55JC reference manual`_ 163 164Supported Features 165================== 166 167The Zephyr nucleo_wl55jc board configuration supports the following hardware 168features: 169 170+-----------+------------+-------------------------------------+ 171| Interface | Controller | Driver/Component | 172+===========+============+=====================================+ 173| AES | on-chip | crypto | 174+-----------+------------+-------------------------------------+ 175| CLOCK | on-chip | reset and clock_control | 176+-----------+------------+-------------------------------------+ 177| FLASH | on-chip | flash | 178+-----------+------------+-------------------------------------+ 179| GPIO | on-chip | gpio | 180+-----------+------------+-------------------------------------+ 181| I2C | on-chip | i2c | 182+-----------+------------+-------------------------------------+ 183| MPU | on-chip | arch/arm | 184+-----------+------------+-------------------------------------+ 185| NVIC | on-chip | arch/arm | 186+-----------+------------+-------------------------------------+ 187| PINMUX | on-chip | pinmux | 188+-----------+------------+-------------------------------------+ 189| RADIO | on-chip | LoRa | 190+-----------+------------+-------------------------------------+ 191| RNG | on-chip | entropy | 192+-----------+------------+-------------------------------------+ 193| SPI | on-chip | spi | 194+-----------+------------+-------------------------------------+ 195| UART | on-chip | serial port-polling; | 196| | | serial port-interrupt | 197+-----------+------------+-------------------------------------+ 198| ADC | on-chip | ADC Controller | 199+-----------+------------+-------------------------------------+ 200| DAC | on-chip | DAC Controller | 201+-----------+------------+-------------------------------------+ 202| die-temp | on-chip | die temperature sensor | 203+-----------+------------+-------------------------------------+ 204| RTC | on-chip | rtc | 205+-----------+------------+-------------------------------------+ 206 207Other hardware features are not yet supported on this Zephyr port. 208 209The default configuration can be found in: 210 211- :zephyr_file:`boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig` 212- :zephyr_file:`boards/st/nucleo_wl55jc/nucleo_wl55jc.dts` 213 214 215Connections and IOs 216=================== 217 218Nucleo WL55JC Board has 4 GPIO controllers. These controllers are responsible 219for pin muxing, input/output, pull-up, etc. 220 221Default Zephyr Peripheral Mapping: 222---------------------------------- 223 224.. rst-class:: rst-columns 225 226- LPUART_1 TX/RX : PA3/PA2 (ST-Link Virtual Port Com) 227- I2C_2_SCL : PA12 (Arduino I2C) 228- I2C_2_SDA : PA11 (Arduino I2C) 229- SPI_1_NSS : PA4 (arduino_spi) 230- SPI_1_SCK : PA5 (arduino_spi) 231- SPI_1_MISO : PA6 (arduino_spi) 232- SPI_1_MOSI : PA7 (arduino_spi) 233- ADC1_IN5 : PB1 (Arduino pin A0) 234- DAC1_OUT1 : PA10 (Arduino pin A2) 235 236System Clock 237------------ 238 239Nucleo WL55JC System Clock could be driven by internal or external oscillator, 240as well as main PLL clock. By default System clock is driven by HSE clock at 24132MHz. 242 243Serial Port 244----------- 245 246Nucleo WL55JC board has 2 (LP)U(S)ARTs. The Zephyr console output is assigned 247to LPUART_1. 248Default settings are 115200 8N1. 249 250 251Programming and Debugging 252************************* 253 254Nucleo WL55JC board includes an STLINK-V3 embedded debug tool interface. 255 256Applications for the ``nucleo_wl55jc`` board configuration can be built the 257usual way (see :ref:`build_an_application`). 258 259Flashing 260======== 261 262The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, 263so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required. 264 265Alternatively, OpenOCD can also be used to flash the board using 266the ``--runner`` (or ``-r``) option: 267 268.. code-block:: console 269 270 $ west flash --runner openocd 271 272 273Flashing an application to Nucleo WL55JC 274---------------------------------------- 275 276Connect the Nucleo WL55JC to your host computer using the USB port. 277Then build and flash an application. Here is an example for the 278:zephyr:code-sample:`hello_world` application. 279 280Run a serial host program to connect with your Nucleo board: 281 282.. code-block:: console 283 284 $ minicom -D /dev/ttyUSB0 285 286Then build and flash the application. 287 288.. zephyr-app-commands:: 289 :zephyr-app: samples/hello_world 290 :board: nucleo_wl55jc 291 :goals: build flash 292 293You should see the following message on the console: 294 295.. code-block:: console 296 297 Hello World! arm 298 299.. Note: 300 301 Nucleo WL55JC board is provided with a stock firmware which demonstrates 302 sleep mode. Unfortunately, default openocd configuration, which is debug 303 compatible, doesn't allow flashing when SoC is in sleep mode. 304 As a consequence, when flashing Nucleo WL55JC board over a stock firmware, 305 please update board's openocd.cfg configuration file to select sleep mode 306 compatible configuration. 307 308Debugging 309========= 310 311You can debug an application in the usual way. Here is an example for the 312:zephyr:code-sample:`blinky` application. 313 314.. zephyr-app-commands:: 315 :zephyr-app: samples/basic/blinky 316 :board: nucleo_wl55jc 317 :maybe-skip-config: 318 :goals: debug 319 320.. _Nucleo WL55JC website: 321 https://www.st.com/en/evaluation-tools/nucleo-wl55jc.html 322 323.. _STM32WL55JC on www.st.com: 324 https://www.st.com/en/microcontrollers-microprocessors/stm32wl55jc.html 325 326.. _STM32WL55JC datasheet: 327 https://www.st.com/resource/en/datasheet/stm32wl55jc.pdf 328 329.. _STM32WL55JC reference manual: 330 https://www.st.com/resource/en/reference_manual/dm00451556-stm32wl5x-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf 331 332.. _STM32CubeProgrammer: 333 https://www.st.com/en/development-tools/stm32cubeprog.html 334