1/*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <adi/max32/max32xxx.dtsi>
9#include <zephyr/dt-bindings/dma/max78002_dma.h>
10
11&clk_ipo {
12	clock-frequency = <DT_FREQ_M(120)>;
13};
14
15&clk_inro {
16	clock-frequency = <DT_FREQ_K(30)>;
17};
18
19/delete-node/ &clk_erfo;
20
21/* MAX78002 extra clocks. */
22/ {
23	clocks {
24		clk_ipll: clk_ipll {
25			compatible = "fixed-clock";
26			#clock-cells = <0>;
27			clock-frequency = <DT_FREQ_M(100)>;
28			status = "disabled";
29		};
30
31		clk_ebo: clk_ebo {
32			compatible = "fixed-clock";
33			#clock-cells = <0>;
34			clock-frequency = <DT_FREQ_M(25)>;
35			status = "disabled";
36		};
37	};
38};
39
40&flash0 {
41	reg = <0x10000000 DT_SIZE_K(2560)>;
42	erase-block-size = <16384>;
43};
44
45&pinctrl {
46	reg = <0x40008000 0x2200>;
47
48	gpio2: gpio@40080400 {
49		reg = <0x40080400 0x200>;
50		compatible = "adi,max32-gpio";
51		gpio-controller;
52		#gpio-cells = <2>;
53		interrupts = <26 0>;
54		clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
55		status = "disabled";
56	};
57
58	gpio3: gpio@40080600 {
59		reg = <0x40080600 0x200>; // Address and size are dummy.
60		compatible = "adi,max32-gpio";
61		gpio-controller;
62		#gpio-cells = <2>;
63		interrupts = <54 0>;
64		status = "disabled";
65	};
66};
67
68&adc {
69	compatible = "adi,max32-adc-sar", "adi,max32-adc";
70	clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
71	clock-divider = <16>;
72	channel-count = <17>;
73	track-count = <4>;
74	idle-count = <0>;
75	vref-mv = <1250>;
76	resolution = <12>;
77};
78
79/* MAX78002 extra peripherals. */
80/ {
81	soc {
82		sram1: memory@20008000 {
83			compatible = "mmio-sram";
84			reg = <0x20008000 DT_SIZE_K(32)>;
85		};
86
87		sram2: memory@20010000 {
88			compatible = "mmio-sram";
89			reg = <0x20010000 DT_SIZE_K(64)>;
90		};
91
92		sram3: memory@20020000 {
93			compatible = "mmio-sram";
94			reg = <0x20020000 DT_SIZE_K(64)>;
95		};
96
97		sram4: memory@20030000 {
98			compatible = "mmio-sram";
99			reg = <0x20030000 DT_SIZE_K(64)>;
100		};
101
102		sram5: memory@20040000 {
103			compatible = "mmio-sram";
104			reg = <0x20040000 DT_SIZE_K(64)>;
105		};
106
107		sram6: memory@20050000 {
108			compatible = "mmio-sram";
109			reg = <0x20050000 DT_SIZE_K(48)>;
110		};
111
112		sram7: memory@2005c000 {
113			compatible = "mmio-sram";
114			reg = <0x2005c000 DT_SIZE_K(16)>;
115		};
116
117		uart3: serial@40081400 {
118			compatible = "adi,max32-uart";
119			reg = <0x40081400 0x400>;
120			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 4>;
121			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
122			interrupts = <88 0>;
123			status = "disabled";
124		};
125
126		spi0: spi@400be000 {
127			compatible = "adi,max32-spi";
128			reg = <0x400be000 0x1000>;
129			#address-cells = <1>;
130			#size-cells = <0>;
131			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 16>;
132			interrupts = <56 0>;
133			status = "disabled";
134		};
135
136		spi1: spi@40046000 {
137			compatible = "adi,max32-spi";
138			reg = <0x40046000 0x2000>;
139			#address-cells = <1>;
140			#size-cells = <0>;
141			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
142			interrupts = <16 0>;
143			status = "disabled";
144		};
145
146		dma0: dma@40028000 {
147			compatible = "adi,max32-dma";
148			reg = <0x40028000 0x1000>;
149			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
150			interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
151			dma-channels = <4>;
152			status = "disabled";
153			#dma-cells = <2>;
154		};
155
156		wdt1: watchdog@40080800  {
157			compatible = "adi,max32-watchdog";
158			reg = <0x40080800 0x400>;
159			interrupts = <57 0>;
160			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>;
161			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
162			status = "disabled";
163		};
164
165		lptimer0: timer@40080c00 {
166			compatible = "adi,max32-timer";
167			reg = <0x40080c00 0x400>;
168			interrupts = <9 0>;
169			status = "disabled";
170			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
171			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
172			prescaler = <1>;
173			pwm {
174				compatible = "adi,max32-pwm";
175				status = "disabled";
176				#pwm-cells = <3>;
177			};
178			counter {
179				compatible = "adi,max32-counter";
180				status = "disabled";
181			};
182		};
183
184		lptimer1: timer@40081000 {
185			compatible = "adi,max32-timer";
186			reg = <0x40081000 0x400>;
187			interrupts = <10 0>;
188			status = "disabled";
189			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 3>;
190			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
191			prescaler = <1>;
192			pwm {
193				compatible = "adi,max32-pwm";
194				status = "disabled";
195				#pwm-cells = <3>;
196			};
197			counter {
198				compatible = "adi,max32-counter";
199				status = "disabled";
200			};
201		};
202
203		w1: w1@4003d000 {
204			compatible = "adi,max32-w1";
205			reg = <0x4003d000 0x1000>;
206			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 13>;
207			interrupts = <67 0>;
208			status = "disabled";
209		};
210	};
211};
212