1/* 2 * Copyright (c) 2023 ITE Corporation. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <ite/it8xxx2.dtsi> 8 9/ { 10 soc { 11 sram0: memory@80100000 { 12 compatible = "mmio-sram"; 13 reg = <0x80100000 DT_SIZE_K(256)>; 14 }; 15 16 intc: interrupt-controller@f03f00 { 17 compatible = "ite,it8xxx2-intc-v2"; 18 #address-cells = <0>; 19 #interrupt-cells = <2>; 20 interrupt-controller; 21 reg = <0x00f03f00 0x0100>; 22 }; 23 24 twd0: watchdog@f01f80 { 25 compatible = "ite,it8xxx2-watchdog"; 26 reg = <0x00f01f80 0x000f>; 27 interrupts = <IT8XXX2_IRQ_TIMER1 IRQ_TYPE_EDGE_RISING /* Warning timer */ 28 IT8XXX2_IRQ_TIMER2 IRQ_TYPE_EDGE_RISING>; /* One shot timer */ 29 interrupt-parent = <&intc>; 30 }; 31 32 gpiogcr: gpio-gcr@f03e00 { 33 compatible = "ite,it8xxx2-gpiogcr"; 34 reg = <0x00f03e00 0x2f>; 35 }; 36 37 gpioa: gpio@f01601 { 38 compatible = "ite,it8xxx2-gpio-v2"; 39 reg = <0x00f01601 1 /* GPDR (set) */ 40 0x00f01618 1 /* GPDMR (get) */ 41 0x00f01630 1 /* GPOTR */ 42 0x00f01648 1 /* P18SCR */ 43 0x00f01660 8>; /* GPCR */ 44 ngpios = <8>; 45 gpio-controller; 46 interrupts = <IT8XXX2_IRQ_WU91 IRQ_TYPE_LEVEL_HIGH 47 IT8XXX2_IRQ_WU92 IRQ_TYPE_LEVEL_HIGH 48 IT8XXX2_IRQ_WU93 IRQ_TYPE_LEVEL_HIGH 49 IT8XXX2_IRQ_WU80 IRQ_TYPE_LEVEL_HIGH 50 IT8XXX2_IRQ_WU81 IRQ_TYPE_LEVEL_HIGH 51 IT8XXX2_IRQ_WU82 IRQ_TYPE_LEVEL_HIGH 52 IT8XXX2_IRQ_WU83 IRQ_TYPE_LEVEL_HIGH 53 IT8XXX2_IRQ_WU100 IRQ_TYPE_LEVEL_HIGH>; 54 interrupt-parent = <&intc>; 55 wuc-base = <0xf01b20 0xf01b20 0xf01b20 0xf01b1c 56 0xf01b1c 0xf01b1c 0xf01b1c 0xf01b24>; 57 wuc-mask = <BIT(3) BIT(4) BIT(5) BIT(0) 58 BIT(1) BIT(2) BIT(3) BIT(4) >; 59 has-volt-sel = <1 1 1 1 1 1 1 1>; 60 #gpio-cells = <2>; 61 }; 62 63 gpiob: gpio@f01602 { 64 compatible = "ite,it8xxx2-gpio-v2"; 65 reg = <0x00f01602 1 /* GPDR (set) */ 66 0x00f01619 1 /* GPDMR (get) */ 67 0x00f01631 1 /* GPOTR */ 68 0x00f01649 1 /* P18SCR */ 69 0x00f01668 8>; /* GPCR */ 70 ngpios = <7>; 71 gpio-controller; 72 interrupts = <IT8XXX2_IRQ_WU101 IRQ_TYPE_LEVEL_HIGH 73 IT8XXX2_IRQ_WU102 IRQ_TYPE_LEVEL_HIGH 74 IT8XXX2_IRQ_WU84 IRQ_TYPE_LEVEL_HIGH 75 IT8XXX2_IRQ_WU103 IRQ_TYPE_LEVEL_HIGH 76 IT8XXX2_IRQ_WU94 IRQ_TYPE_LEVEL_HIGH 77 IT8XXX2_IRQ_WU104 IRQ_TYPE_LEVEL_HIGH 78 IT8XXX2_IRQ_WU105 IRQ_TYPE_LEVEL_HIGH 79 NO_FUNC 0>; 80 interrupt-parent = <&intc>; 81 wuc-base = <0xf01b24 0xf01b24 0xf01b1c 0xf01b24 82 0xf01b20 0xf01b28 0xf01b28 NO_FUNC >; 83 wuc-mask = <BIT(5) BIT(6) BIT(4) BIT(7) 84 BIT(6) BIT(0) BIT(1) 0 >; 85 has-volt-sel = <1 1 1 1 1 1 1 0>; 86 #gpio-cells = <2>; 87 }; 88 89 gpioc: gpio@f01603 { 90 compatible = "ite,it8xxx2-gpio-v2"; 91 reg = <0x00f01603 1 /* GPDR (set) */ 92 0x00f0161a 1 /* GPDMR (get) */ 93 0x00f01632 1 /* GPOTR */ 94 0x00f0164a 1 /* P18SCR */ 95 0x00f01670 8>; /* GPCR */ 96 ngpios = <8>; 97 gpio-controller; 98 interrupts = <IT8XXX2_IRQ_WU85 IRQ_TYPE_LEVEL_HIGH 99 IT8XXX2_IRQ_WU107 IRQ_TYPE_LEVEL_HIGH 100 IT8XXX2_IRQ_WU95 IRQ_TYPE_LEVEL_HIGH 101 IT8XXX2_IRQ_WU108 IRQ_TYPE_LEVEL_HIGH 102 IT8XXX2_IRQ_WU22 IRQ_TYPE_LEVEL_HIGH 103 IT8XXX2_IRQ_WU109 IRQ_TYPE_LEVEL_HIGH 104 IT8XXX2_IRQ_WU23 IRQ_TYPE_LEVEL_HIGH 105 IT8XXX2_IRQ_WU86 IRQ_TYPE_LEVEL_HIGH>; 106 interrupt-parent = <&intc>; 107 wuc-base = <0xf01b1c 0xf01b28 0xf01b20 0xf01b28 108 0xf01b04 0xf01b28 0xf01b04 0xf01b1c>; 109 wuc-mask = <BIT(5) BIT(3) BIT(7) BIT(4) 110 BIT(2) BIT(5) BIT(3) BIT(6) >; 111 has-volt-sel = <1 1 1 1 1 1 1 1>; 112 #gpio-cells = <2>; 113 }; 114 115 gpiod: gpio@f01604 { 116 compatible = "ite,it8xxx2-gpio-v2"; 117 reg = <0x00f01604 1 /* GPDR (set) */ 118 0x00f0161b 1 /* GPDMR (get) */ 119 0x00f01633 1 /* GPOTR */ 120 0x00f0164b 1 /* P18SCR */ 121 0x00f01678 8>; /* GPCR */ 122 ngpios = <8>; 123 gpio-controller; 124 interrupts = <IT8XXX2_IRQ_WU20 IRQ_TYPE_LEVEL_HIGH 125 IT8XXX2_IRQ_WU21 IRQ_TYPE_LEVEL_HIGH 126 IT8XXX2_IRQ_WU24 IRQ_TYPE_LEVEL_HIGH 127 IT8XXX2_IRQ_WU110 IRQ_TYPE_LEVEL_HIGH 128 IT8XXX2_IRQ_WU111 IRQ_TYPE_LEVEL_HIGH 129 IT8XXX2_IRQ_WU112 IRQ_TYPE_LEVEL_HIGH 130 IT8XXX2_IRQ_WU113 IRQ_TYPE_LEVEL_HIGH 131 IT8XXX2_IRQ_WU87 IRQ_TYPE_LEVEL_HIGH>; 132 interrupt-parent = <&intc>; 133 wuc-base = <0xf01b04 0xf01b04 0xf01b04 0xf01b28 134 0xf01b28 0xf01b2c 0xf01b2c 0xf01b1c>; 135 wuc-mask = <BIT(0) BIT(1) BIT(4) BIT(6) 136 BIT(7) BIT(0) BIT(1) BIT(7) >; 137 has-volt-sel = <1 1 1 1 1 1 1 1>; 138 #gpio-cells = <2>; 139 }; 140 141 gpioe: gpio@f01605 { 142 compatible = "ite,it8xxx2-gpio-v2"; 143 reg = <0x00f01605 1 /* GPDR (set) */ 144 0x00f0161c 1 /* GPDMR (get) */ 145 0x00f01634 1 /* GPOTR */ 146 0x00f0164c 1 /* P18SCR */ 147 0x00f01680 8>; /* GPCR */ 148 ngpios = <8>; 149 gpio-controller; 150 interrupts = <IT8XXX2_IRQ_WU70 IRQ_TYPE_LEVEL_HIGH 151 IT8XXX2_IRQ_WU71 IRQ_TYPE_LEVEL_HIGH 152 IT8XXX2_IRQ_WU72 IRQ_TYPE_LEVEL_HIGH 153 IT8XXX2_IRQ_WU73 IRQ_TYPE_LEVEL_HIGH 154 IT8XXX2_IRQ_WU114 IRQ_TYPE_LEVEL_HIGH 155 IT8XXX2_IRQ_WU40 IRQ_TYPE_LEVEL_HIGH 156 IT8XXX2_IRQ_WU45 IRQ_TYPE_LEVEL_HIGH 157 IT8XXX2_IRQ_WU46 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-parent = <&intc>; 159 wuc-base = <0xf01b18 0xf01b18 0xf01b18 0xf01b18 160 0xf01b2c 0xf01b0c 0xf01b0c 0xf01b0c>; 161 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 162 BIT(2) BIT(0) BIT(5) BIT(6) >; 163 has-volt-sel = <1 1 1 1 1 1 1 1>; 164 #gpio-cells = <2>; 165 }; 166 167 gpiof: gpio@f01606 { 168 compatible = "ite,it8xxx2-gpio-v2"; 169 reg = <0x00f01606 1 /* GPDR (set) */ 170 0x00f0161d 1 /* GPDMR (get) */ 171 0x00f01635 1 /* GPOTR */ 172 0x00f0164d 1 /* P18SCR */ 173 0x00f01688 8>; /* GPCR */ 174 ngpios = <8>; 175 gpio-controller; 176 interrupts = <IT8XXX2_IRQ_WU96 IRQ_TYPE_LEVEL_HIGH 177 IT8XXX2_IRQ_WU97 IRQ_TYPE_LEVEL_HIGH 178 IT8XXX2_IRQ_WU98 IRQ_TYPE_LEVEL_HIGH 179 IT8XXX2_IRQ_WU99 IRQ_TYPE_LEVEL_HIGH 180 IT8XXX2_IRQ_WU64 IRQ_TYPE_LEVEL_HIGH 181 IT8XXX2_IRQ_WU65 IRQ_TYPE_LEVEL_HIGH 182 IT8XXX2_IRQ_WU66 IRQ_TYPE_LEVEL_HIGH 183 IT8XXX2_IRQ_WU67 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-parent = <&intc>; 185 wuc-base = <0xf01b24 0xf01b24 0xf01b24 0xf01b24 186 0xf01b14 0xf01b14 0xf01b14 0xf01b14>; 187 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 188 BIT(4) BIT(5) BIT(6) BIT(7) >; 189 has-volt-sel = <1 1 1 1 1 1 1 1>; 190 #gpio-cells = <2>; 191 }; 192 193 gpiog: gpio@f01607 { 194 compatible = "ite,it8xxx2-gpio-v2"; 195 reg = <0x00f01607 1 /* GPDR (set) */ 196 0x00f0161e 1 /* GPDMR (get) */ 197 0x00f01636 1 /* GPOTR */ 198 0x00f0164e 1 /* P18SCR */ 199 0x00f01690 8>; /* GPCR */ 200 ngpios = <8>; 201 gpio-controller; 202 interrupts = <IT8XXX2_IRQ_WU115 IRQ_TYPE_LEVEL_HIGH 203 IT8XXX2_IRQ_WU116 IRQ_TYPE_LEVEL_HIGH 204 IT8XXX2_IRQ_WU117 IRQ_TYPE_LEVEL_HIGH 205 IT8XXX2_IRQ_WU123 IRQ_TYPE_LEVEL_HIGH 206 IT8XXX2_IRQ_WU124 IRQ_TYPE_LEVEL_HIGH 207 IT8XXX2_IRQ_WU125 IRQ_TYPE_LEVEL_HIGH 208 IT8XXX2_IRQ_WU118 IRQ_TYPE_LEVEL_HIGH 209 IT8XXX2_IRQ_WU126 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-parent = <&intc>; 211 wuc-base = <0xf01b2c 0xf01b2c 0xf01b2c 0xf01b30 212 0xf01b30 0xf01b30 0xf01b2c 0xf01b30>; 213 wuc-mask = <BIT(3) BIT(4) BIT(5) BIT(3) 214 BIT(4) BIT(5) BIT(6) BIT(6) >; 215 has-volt-sel = <1 1 1 0 0 0 1 0>; 216 #gpio-cells = <2>; 217 }; 218 219 gpioh: gpio@f01608 { 220 compatible = "ite,it8xxx2-gpio-v2"; 221 reg = <0x00f01608 1 /* GPDR (set) */ 222 0x00f0161f 1 /* GPDMR (get) */ 223 0x00f01637 1 /* GPOTR */ 224 0x00f0164f 1 /* P18SCR */ 225 0x00f01698 8>; /* GPCR */ 226 ngpios = <7>; 227 gpio-controller; 228 interrupts = <IT8XXX2_IRQ_WU60 IRQ_TYPE_LEVEL_HIGH 229 IT8XXX2_IRQ_WU61 IRQ_TYPE_LEVEL_HIGH 230 IT8XXX2_IRQ_WU62 IRQ_TYPE_LEVEL_HIGH 231 IT8XXX2_IRQ_WU63 IRQ_TYPE_LEVEL_HIGH 232 IT8XXX2_IRQ_WU88 IRQ_TYPE_LEVEL_HIGH 233 IT8XXX2_IRQ_WU89 IRQ_TYPE_LEVEL_HIGH 234 IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH 235 NO_FUNC 0>; 236 interrupt-parent = <&intc>; 237 wuc-base = <0xf01b14 0xf01b14 0xf01b14 0xf01b14 238 0xf01b20 0xf01b20 0xf01b20 NO_FUNC >; 239 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 240 BIT(0) BIT(1) BIT(2) 0 >; 241 has-volt-sel = <1 1 1 1 1 1 1 0>; 242 #gpio-cells = <2>; 243 }; 244 245 gpioi: gpio@f01609 { 246 compatible = "ite,it8xxx2-gpio-v2"; 247 reg = <0x00f01609 1 /* GPDR (set) */ 248 0x00f01620 1 /* GPDMR (get) */ 249 0x00f01638 1 /* GPOTR */ 250 0x00f01650 1 /* P18SCR */ 251 0x00f016a0 8>; /* GPCR */ 252 ngpios = <8>; 253 gpio-controller; 254 interrupts = <IT8XXX2_IRQ_WU119 IRQ_TYPE_LEVEL_HIGH 255 IT8XXX2_IRQ_WU120 IRQ_TYPE_LEVEL_HIGH 256 IT8XXX2_IRQ_WU121 IRQ_TYPE_LEVEL_HIGH 257 IT8XXX2_IRQ_WU122 IRQ_TYPE_LEVEL_HIGH 258 IT8XXX2_IRQ_WU74 IRQ_TYPE_LEVEL_HIGH 259 IT8XXX2_IRQ_WU75 IRQ_TYPE_LEVEL_HIGH 260 IT8XXX2_IRQ_WU76 IRQ_TYPE_LEVEL_HIGH 261 IT8XXX2_IRQ_WU77 IRQ_TYPE_LEVEL_HIGH>; 262 interrupt-parent = <&intc>; 263 wuc-base = <0xf01b2c 0xf01b30 0xf01b30 0xf01b30 264 0xf01b18 0xf01b18 0xf01b18 0xf01b18>; 265 wuc-mask = <BIT(7) BIT(0) BIT(1) BIT(2) 266 BIT(4) BIT(5) BIT(6) BIT(7) >; 267 has-volt-sel = <1 1 1 1 1 1 1 1>; 268 #gpio-cells = <2>; 269 }; 270 271 gpioj: gpio@f0160a { 272 compatible = "ite,it8xxx2-gpio-v2"; 273 reg = <0x00f0160a 1 /* GPDR (set) */ 274 0x00f01621 1 /* GPDMR (get) */ 275 0x00f01639 1 /* GPOTR */ 276 0x00f01651 1 /* P18SCR */ 277 0x00f016a8 8>; /* GPCR */ 278 ngpios = <8>; 279 gpio-controller; 280 interrupts = <IT8XXX2_IRQ_WU128 IRQ_TYPE_LEVEL_HIGH 281 IT8XXX2_IRQ_WU129 IRQ_TYPE_LEVEL_HIGH 282 IT8XXX2_IRQ_WU130 IRQ_TYPE_LEVEL_HIGH 283 IT8XXX2_IRQ_WU131 IRQ_TYPE_LEVEL_HIGH 284 IT8XXX2_IRQ_WU132 IRQ_TYPE_LEVEL_HIGH 285 IT8XXX2_IRQ_WU133 IRQ_TYPE_LEVEL_HIGH 286 IT8XXX2_IRQ_WU134 IRQ_TYPE_LEVEL_HIGH 287 IT8XXX2_IRQ_WU135 IRQ_TYPE_LEVEL_HIGH>; 288 interrupt-parent = <&intc>; 289 wuc-base = <0xf01b34 0xf01b34 0xf01b34 0xf01b34 290 0xf01b34 0xf01b34 0xf01b34 0xf01b34 >; 291 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 292 BIT(4) BIT(5) BIT(6) BIT(7)>; 293 has-volt-sel = <1 1 1 1 1 1 1 1>; 294 #gpio-cells = <2>; 295 }; 296 297 gpiok: gpio@f0160b { 298 compatible = "ite,it8xxx2-gpio-v2"; 299 reg = <0x00f0160b 1 /* GPDR (set) */ 300 0x00f01622 1 /* GPDMR (get) */ 301 0x00f0163a 1 /* GPOTR */ 302 0x00f01652 1 /* P18SCR */ 303 0x00f016b0 8>; /* GPCR */ 304 ngpios = <8>; 305 gpio-controller; 306 interrupts = <IT8XXX2_IRQ_WU50 IRQ_TYPE_LEVEL_HIGH 307 IT8XXX2_IRQ_WU51 IRQ_TYPE_LEVEL_HIGH 308 IT8XXX2_IRQ_WU52 IRQ_TYPE_LEVEL_HIGH 309 IT8XXX2_IRQ_WU53 IRQ_TYPE_LEVEL_HIGH 310 IT8XXX2_IRQ_WU54 IRQ_TYPE_LEVEL_HIGH 311 IT8XXX2_IRQ_WU55 IRQ_TYPE_LEVEL_HIGH 312 IT8XXX2_IRQ_WU56 IRQ_TYPE_LEVEL_HIGH 313 IT8XXX2_IRQ_WU57 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-parent = <&intc>; 315 wuc-base = <0xf01b10 0xf01b10 0xf01b10 0xf01b10 316 0xf01b10 0xf01b10 0xf01b10 0xf01b10>; 317 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 318 BIT(4) BIT(5) BIT(6) BIT(7) >; 319 has-volt-sel = <1 1 1 1 1 1 1 1>; 320 #gpio-cells = <2>; 321 }; 322 323 gpiol: gpio@f0160c { 324 compatible = "ite,it8xxx2-gpio-v2"; 325 reg = <0x00f0160c 1 /* GPDR (set) */ 326 0x00f01623 1 /* GPDMR (get) */ 327 0x00f0163b 1 /* GPOTR */ 328 0x00f01653 1 /* P18SCR */ 329 0x00f016b8 8>; /* GPCR */ 330 ngpios = <8>; 331 gpio-controller; 332 interrupts = <IT8XXX2_IRQ_WU136 IRQ_TYPE_LEVEL_HIGH 333 IT8XXX2_IRQ_WU137 IRQ_TYPE_LEVEL_HIGH 334 IT8XXX2_IRQ_WU138 IRQ_TYPE_LEVEL_HIGH 335 IT8XXX2_IRQ_WU139 IRQ_TYPE_LEVEL_HIGH 336 IT8XXX2_IRQ_WU140 IRQ_TYPE_LEVEL_HIGH 337 IT8XXX2_IRQ_WU141 IRQ_TYPE_LEVEL_HIGH 338 IT8XXX2_IRQ_WU142 IRQ_TYPE_LEVEL_HIGH 339 IT8XXX2_IRQ_WU143 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-parent = <&intc>; 341 wuc-base = <0xf01b38 0xf01b38 0xf01b38 0xf01b38 342 0xf01b38 0xf01b38 0xf01b38 0xf01b38>; 343 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 344 BIT(4) BIT(5) BIT(6) BIT(7) >; 345 has-volt-sel = <1 1 1 1 1 1 1 1>; 346 #gpio-cells = <2>; 347 }; 348 349 gpiom: gpio@f0160d { 350 compatible = "ite,it8xxx2-gpio-v2"; 351 reg = <0x00f0160d 1 /* GPDR (set) */ 352 0x00f01624 1 /* GPDMR (get) */ 353 0x00f0163c 1 /* GPOTR */ 354 0x00f01654 1 /* P18SCR */ 355 0x00f016c0 8>; /* GPCR */ 356 ngpios = <7>; 357 gpio-controller; 358 interrupts = <IT8XXX2_IRQ_WU144 IRQ_TYPE_LEVEL_HIGH 359 IT8XXX2_IRQ_WU145 IRQ_TYPE_LEVEL_HIGH 360 IT8XXX2_IRQ_WU146 IRQ_TYPE_LEVEL_HIGH 361 IT8XXX2_IRQ_WU147 IRQ_TYPE_LEVEL_HIGH 362 IT8XXX2_IRQ_WU148 IRQ_TYPE_LEVEL_HIGH 363 IT8XXX2_IRQ_WU149 IRQ_TYPE_LEVEL_HIGH 364 IT8XXX2_IRQ_WU150 IRQ_TYPE_LEVEL_HIGH 365 NO_FUNC 0>; 366 interrupt-parent = <&intc>; 367 wuc-base = <0xf01b3c 0xf01b3c 0xf01b3c 0xf01b3c 368 0xf01b3c 0xf01b3c 0xf01b3c NO_FUNC >; 369 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 370 BIT(4) BIT(5) BIT(6) 0 >; 371 has-volt-sel = <1 1 1 1 1 1 1 0>; 372 #gpio-cells = <2>; 373 }; 374 375 gpioksi: gpio@f01d08 { 376 compatible = "ite,it8xxx2-gpio-v2"; 377 reg = <0x00f01d08 1 /* GPDR (set) */ 378 0x00f01d09 1 /* GPDMR (get) */ 379 0x00f01d2c 1 /* GPOTR */ 380 NO_FUNC 1 /* P18SCR */ 381 0x00f01d40 8>; /* GPCR */ 382 ngpios = <8>; 383 gpio-controller; 384 interrupts = <NO_FUNC 0 385 NO_FUNC 0 386 NO_FUNC 0 387 NO_FUNC 0 388 NO_FUNC 0 389 NO_FUNC 0 390 NO_FUNC 0 391 NO_FUNC 0>; 392 interrupt-parent = <&intc>; 393 keyboard-controller; 394 #gpio-cells = <2>; 395 }; 396 397 gpioksoh: gpio@f01d01 { 398 compatible = "ite,it8xxx2-gpio-v2"; 399 reg = <0x00f01d01 1 /* GPDR (set) */ 400 0x00f01d0c 1 /* GPDMR (get) */ 401 0x00f01d2d 1 /* GPOTR */ 402 NO_FUNC 1 /* P18SCR */ 403 0x00f01d50 8>; /* GPCR */ 404 ngpios = <8>; 405 gpio-controller; 406 interrupts = <NO_FUNC 0 407 NO_FUNC 0 408 NO_FUNC 0 409 NO_FUNC 0 410 NO_FUNC 0 411 NO_FUNC 0 412 NO_FUNC 0 413 NO_FUNC 0>; 414 interrupt-parent = <&intc>; 415 keyboard-controller; 416 #gpio-cells = <2>; 417 }; 418 419 gpioksol: gpio@f01d00 { 420 compatible = "ite,it8xxx2-gpio-v2"; 421 reg = <0x00f01d00 1 /* GPDR (set) */ 422 0x00f01d0f 1 /* GPDMR (get) */ 423 0x00f01d2e 1 /* GPOTR */ 424 NO_FUNC 1 /* P18SCR */ 425 0x00f01d48 8>; /* GPCR */ 426 ngpios = <8>; 427 gpio-controller; 428 interrupts = <NO_FUNC 0 429 NO_FUNC 0 430 NO_FUNC 0 431 NO_FUNC 0 432 NO_FUNC 0 433 NO_FUNC 0 434 NO_FUNC 0 435 NO_FUNC 0>; 436 interrupt-parent = <&intc>; 437 keyboard-controller; 438 #gpio-cells = <2>; 439 }; 440 441 pinctrl: pin-controller { 442 compatible = "ite,it8xxx2-pinctrl"; 443 #address-cells = <1>; 444 #size-cells = <1>; 445 status = "okay"; 446 }; 447 448 pinctrla: pinctrl@f01660 { 449 compatible = "ite,it8xxx2-pinctrl-func"; 450 reg = <0x00f01660 8 /* GPCR */ 451 0x00f03e30 1>; /* PDSCA */ 452 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 453 0xf02032 0xf02032 0xf03e10 0xf03e10>; 454 func3-en-mask = <0 0 0 0 455 0x02 0x02 0x10 0x0C >; 456 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 457 NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; 458 func4-en-mask = <0 0 0 0 459 0 0 0 0 >; 460 volt-sel = <0xf01648 0xf01648 0xf01648 0xf01648 461 0xf01648 0xf01648 0xf01648 0xf01648>; 462 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 463 BIT(4) BIT(5) BIT(6) BIT(7) >; 464 #pinmux-cells = <2>; 465 gpio-group; 466 }; 467 468 pinctrlb: pinctrl@f01668 { 469 compatible = "ite,it8xxx2-pinctrl-func"; 470 reg = <0x00f01668 8 /* GPCR */ 471 0x00f03e31 1>; /* PDSCB */ 472 func3-gcr = <0xf03e15 0xf03e15 0xf03e11 NO_FUNC 473 NO_FUNC 0xf03e11 NO_FUNC NO_FUNC>; 474 func3-en-mask = <0x01 0x02 0x20 0 475 0 0x20 0 0 >; 476 func3-ext = <NO_FUNC NO_FUNC 0xf03e16 NO_FUNC 477 NO_FUNC 0xf03e16 NO_FUNC NO_FUNC>; 478 func3-ext-mask = <0 0 0x40 0 479 0 0x40 0 0 >; 480 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 481 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 482 func4-en-mask = <0 0 0 0 483 0 0 0 0 >; 484 volt-sel = <0xf01649 0xf01649 0xf01649 0xf01649 485 0xf01649 0xf01649 0xf01649 NO_FUNC>; 486 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 487 BIT(4) BIT(5) BIT(6) 0 >; 488 #pinmux-cells = <2>; 489 gpio-group; 490 }; 491 492 pinctrlc: pinctrl@f01670 { 493 compatible = "ite,it8xxx2-pinctrl-func"; 494 reg = <0x00f01670 8 /* GPCR */ 495 0x00f03e32 1>; /* PDSCC */ 496 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC 0xf03e10 497 NO_FUNC 0xf03e10 NO_FUNC 0xf03e13>; 498 func3-en-mask = <0 0 0 0x10 499 0 0x10 0 0x02 >; 500 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 501 NO_FUNC NO_FUNC NO_FUNC 0xf03e16>; 502 func4-en-mask = <0 0 0 0 503 0 0 0 0x80 >; 504 volt-sel = <0xf0164a 0xf0164a 0xf0164a 0xf0164a 505 0xf0164a 0xf0164a 0xf0164a 0xf0164a>; 506 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 507 BIT(4) BIT(5) BIT(6) BIT(7) >; 508 #pinmux-cells = <2>; 509 gpio-group; 510 }; 511 512 pinctrld: pinctrl@f01678 { 513 compatible = "ite,it8xxx2-pinctrl-func"; 514 reg = <0x00f01678 8 /* GPCR */ 515 0x00f03e33 1>; /* PDSCD */ 516 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 517 NO_FUNC 0xf03e10 NO_FUNC NO_FUNC>; 518 func3-en-mask = <0 0 0 0 519 0 0x02 0 0 >; 520 func4-gcr = <0xf03e16 NO_FUNC NO_FUNC NO_FUNC 521 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 522 func4-en-mask = <0x80 0 0 0 523 0 0 0 0 >; 524 volt-sel = <0xf0164b 0xf0164b 0xf0164b 0xf0164b 525 0xf0164b 0xf0164b 0xf0164b 0xf0164b>; 526 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 527 BIT(4) BIT(5) BIT(6) BIT(7) >; 528 #pinmux-cells = <2>; 529 gpio-group; 530 }; 531 532 pinctrle: pinctrl@f01680 { 533 compatible = "ite,it8xxx2-pinctrl-func"; 534 reg = <0x00f01680 8 /* GPCR */ 535 0x00f03e34 1>; /* PDSCE */ 536 func3-gcr = <NO_FUNC 0xf03e16 0xf03e16 NO_FUNC 537 NO_FUNC 0xf03e10 NO_FUNC NO_FUNC >; 538 func3-en-mask = <0 0x20 0x20 0 539 0 0x08 0 0 >; 540 func3-ext = <0xf02032 0xf02032 0xf02032 NO_FUNC 541 NO_FUNC NO_FUNC NO_FUNC 0xf02032>; 542 func3-ext-mask = <0x01 0x02 0x02 0 543 0 0 0 0x01 >; 544 func4-gcr = <0xf03e13 NO_FUNC NO_FUNC NO_FUNC 545 NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; 546 func4-en-mask = <0x01 0 0 0 547 0 0 0 0 >; 548 volt-sel = <0xf0164c 0xf0164c 0xf0164c 0xf0164c 549 0xf0164c 0xf0164c 0xf0164c 0xf0164c>; 550 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 551 BIT(4) BIT(5) BIT(6) BIT(7) >; 552 #pinmux-cells = <2>; 553 gpio-group; 554 }; 555 556 pinctrlf: pinctrl@f01688 { 557 compatible = "ite,it8xxx2-pinctrl-func"; 558 reg = <0x00f01688 8 /* GPCR */ 559 0x00f03e35 1>; /* PDSCF */ 560 func3-gcr = <0xf03e15 0xf03e15 0xf03e10 0xf03e10 561 NO_FUNC NO_FUNC 0xf03e11 NO_FUNC>; 562 func3-en-mask = <0x04 0x08 0x02 0x02 563 0 0 0x10 0 >; 564 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 565 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 566 func4-en-mask = <0 0 0 0 567 0 0 0 0 >; 568 volt-sel = <0xf0164d 0xf0164d 0xf0164d 0xf0164d 569 0xf0164d 0xf0164d 0xf0164d 0xf0164d>; 570 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 571 BIT(4) BIT(5) BIT(6) BIT(7) >; 572 #pinmux-cells = <2>; 573 gpio-group; 574 }; 575 576 pinctrlg: pinctrl@f01690 { 577 compatible = "ite,it8xxx2-pinctrl-func"; 578 reg = <0x00f01690 8 /* GPCR */ 579 0x00f03e36 1>; /* PDSCG */ 580 func3-gcr = <0xf03e10 0xf03e10 0xf03e10 NO_FUNC 581 NO_FUNC NO_FUNC 0xf03e10 NO_FUNC>; 582 func3-en-mask = <0x20 0x08 0x10 0 583 0 0 0x02 0 >; 584 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 585 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 586 func4-en-mask = <0 0 0 0 587 0 0 0 0 >; 588 volt-sel = <0xf0164e 0xf0164e 0xf0164e NO_FUNC 589 NO_FUNC NO_FUNC 0xf0164e NO_FUNC >; 590 volt-sel-mask = <BIT(0) BIT(1) BIT(2) 0 591 0 0 BIT(6) 0 >; 592 #pinmux-cells = <2>; 593 gpio-group; 594 }; 595 596 pinctrlh: pinctrl@f01698 { 597 compatible = "ite,it8xxx2-pinctrl-func"; 598 reg = <0x00f01698 8 /* GPCR */ 599 0x00f03e37 1>; /* PDSCH */ 600 func3-gcr = <NO_FUNC 0xf03e11 0xf03e11 NO_FUNC 601 NO_FUNC 0 0 NO_FUNC>; 602 func3-en-mask = <0 0x20 0x20 0 603 0 0 0 0 >; 604 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 605 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 606 func4-en-mask = <0 0 0 0 607 0 0 0 0 >; 608 volt-sel = <0xf0164f 0xf0164f 0xf0164f 0xf0164f 609 0xf0164f 0xf0164f 0xf0164f NO_FUNC>; 610 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 611 BIT(4) BIT(5) BIT(6) 0 >; 612 #pinmux-cells = <2>; 613 gpio-group; 614 }; 615 616 pinctrli: pinctrl@f016a0 { 617 compatible = "ite,it8xxx2-pinctrl-func"; 618 reg = <0x00f016a0 8 /* GPCR */ 619 NO_FUNC 1>; 620 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 621 NO_FUNC 0xf03e10 0xf03e10 0xf03e10>; 622 func3-en-mask = <0 0 0 0 623 0 0x08 0x08 0x08 >; 624 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 625 NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; 626 func4-en-mask = <0 0 0 0 627 0 0 0 0 >; 628 volt-sel = <0xf01650 0xf01650 0xf01650 0xf01650 629 0xf01650 0xf01650 0xf01650 0xf01650>; 630 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 631 BIT(4) BIT(5) BIT(6) BIT(7) >; 632 #pinmux-cells = <2>; 633 gpio-group; 634 }; 635 636 pinctrlj: pinctrl@f016a8 { 637 compatible = "ite,it8xxx2-pinctrl-func"; 638 reg = <0x00f016a8 8 /* GPCR */ 639 0x00f03e39 1>; /* PDSCJ */ 640 func3-gcr = <0xf03e14 NO_FUNC 0xf03e14 0xf03e14 641 0xf03e10 0xf03e10 NO_FUNC NO_FUNC>; 642 func3-en-mask = <0x01 0 0x01 0x02 643 0x02 0x03 0 0 >; 644 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 645 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 646 func4-en-mask = <0 0 0 0 647 0 0 0 0 >; 648 volt-sel = <0xf01651 0xf01651 0xf01651 0xf01651 649 0xf01651 0xf01651 NO_FUNC NO_FUNC >; 650 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 651 BIT(4) BIT(5) 0 0 >; 652 #pinmux-cells = <2>; 653 gpio-group; 654 }; 655 656 pinctrlk: pinctrl@f016b0 { 657 compatible = "ite,it8xxx2-pinctrl-func"; 658 reg = <0x00f016b0 8 /* GPCR */ 659 0x00f03e3A 1>; /* PDSCK */ 660 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 661 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 662 func3-en-mask = <0 0 0 0 663 0 0 0 0 >; 664 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 665 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 666 func4-en-mask = <0 0 0 0 667 0 0 0 0 >; 668 volt-sel = <0xf01652 0xf01652 0xf01652 0xf01652 669 0xf01652 0xf01652 0xf01652 0xf01652>; 670 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 671 BIT(4) BIT(5) BIT(6) BIT(7) >; 672 #pinmux-cells = <2>; 673 gpio-group; 674 }; 675 676 pinctrll: pinctrl@f016b8 { 677 compatible = "ite,it8xxx2-pinctrl-func"; 678 reg = <0x00f016b8 8 /* GPCR */ 679 0x00f03e3B 1>; /* PDSCL */ 680 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 681 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 682 func3-en-mask = <0 0 0 0 683 0 0 0 0 >; 684 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 685 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 686 func4-en-mask = <0 0 0 0 687 0 0 0 0 >; 688 volt-sel = <0xf01653 0xf01653 0xf01653 0xf01653 689 0xf01653 0xf01653 0xf01653 0xf01653>; 690 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 691 BIT(4) BIT(5) BIT(6) BIT(7) >; 692 #pinmux-cells = <2>; 693 gpio-group; 694 }; 695 696 pinctrlm: pinctrl@f016c0 { 697 compatible = "ite,it8xxx2-pinctrl-func"; 698 reg = <0x00f016c0 8 /* GPCR */ 699 NO_FUNC 1>; 700 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 701 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 702 func3-en-mask = <0 0 0 0 703 0 0 0 0 >; 704 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 705 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 706 func4-en-mask = <0 0 0 0 707 0 0 0 0 >; 708 volt-sel = <0xf03e2d 0xf03e2d 0xf03e2d 0xf03e2d 709 0xf03e2d 0xf03e2d 0xf03e2d NO_FUNC >; 710 volt-sel-mask = <BIT(4) BIT(4) BIT(4) BIT(4) 711 BIT(4) BIT(4) BIT(4) 0 >; 712 #pinmux-cells = <2>; 713 gpio-group; 714 }; 715 716 pinctrlksi: pinctrl@f01d40 { 717 compatible = "ite,it8xxx2-pinctrl-func"; 718 reg = <0x00f01d40 8 /* KSIGCTRL */ 719 0x00f01d05 1>; /* KSICTRL */ 720 pp-od-mask = <NO_FUNC>; 721 pullup-mask = <BIT(2)>; 722 #pinmux-cells = <2>; 723 }; 724 725 pinctrlksol: pinctrl@f01d48 { 726 compatible = "ite,it8xxx2-pinctrl-func"; 727 reg = <0x00f01d48 8 /* KSOLGCTRL */ 728 0x00f01d02 1>; /* KSOCTRL */ 729 pp-od-mask = <BIT(0)>; 730 pullup-mask = <BIT(2)>; 731 #pinmux-cells = <2>; 732 }; 733 734 pinctrlksoh: pinctrl@f01d50 { 735 compatible = "ite,it8xxx2-pinctrl-func"; 736 reg = <0x00f01d50 8 /* KSOHGCTRL */ 737 0x00f01d02 1>; /* KSOCTRL */ 738 pp-od-mask = <BIT(0)>; 739 pullup-mask = <BIT(2)>; 740 #pinmux-cells = <2>; 741 }; 742 743 wuc1: wakeup-controller@f01b00 { 744 compatible = "ite,it8xxx2-wuc"; 745 reg = <0x00f01b00 1 /* WUEMR1 */ 746 0x00f01b01 1 /* WUESR1 */ 747 0x00f01b02 1 /* WUENR1 */ 748 0x00f01b03 1>; /* WUBEMR1 */ 749 wakeup-controller; 750 #wuc-cells = <1>; 751 }; 752 753 wuc2: wakeup-controller@f01b04 { 754 compatible = "ite,it8xxx2-wuc"; 755 reg = <0x00f01b04 1 /* WUEMR2 */ 756 0x00f01b05 1 /* WUESR2 */ 757 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR2 */ 758 0x00f01b07 1>; /* WUBEMR2 */ 759 wakeup-controller; 760 #wuc-cells = <1>; 761 }; 762 763 wuc3: wakeup-controller@f01b08 { 764 compatible = "ite,it8xxx2-wuc"; 765 reg = <0x00f01b08 1 /* WUEMR3 */ 766 0x00f01b09 1 /* WUESR3 */ 767 0x00f01b0a 1 /* WUENR3 */ 768 0x00f01b0b 1>; /* WUBEMR3 */ 769 wakeup-controller; 770 #wuc-cells = <1>; 771 }; 772 773 wuc4: wakeup-controller@f01b0c { 774 compatible = "ite,it8xxx2-wuc"; 775 reg = <0x00f01b0c 1 /* WUEMR4 */ 776 0x00f01b0d 1 /* WUESR4 */ 777 0x00f01b0e 1 /* WUENR4 */ 778 0x00f01b0f 1>; /* WUBEMR4 */ 779 wakeup-controller; 780 #wuc-cells = <1>; 781 }; 782 783 wuc5: wakeup-controller@f01b10 { 784 compatible = "ite,it8xxx2-wuc"; 785 reg = <0x00f01b10 1 /* WUEMR5 */ 786 0x00f01b11 1 /* WUESR5 */ 787 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR5 */ 788 0x00f01b13 1>; /* WUBEMR5 */ 789 wakeup-controller; 790 #wuc-cells = <1>; 791 }; 792 793 wuc6: wakeup-controller@f01b14 { 794 compatible = "ite,it8xxx2-wuc"; 795 reg = <0x00f01b14 1 /* WUEMR6 */ 796 0x00f01b15 1 /* WUESR6 */ 797 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR6 */ 798 0x00f01b17 1>; /* WUBEMR6 */ 799 wakeup-controller; 800 #wuc-cells = <1>; 801 }; 802 803 wuc7: wakeup-controller@f01b18 { 804 compatible = "ite,it8xxx2-wuc"; 805 reg = <0x00f01b18 1 /* WUEMR7 */ 806 0x00f01b19 1 /* WUESR7 */ 807 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR7 */ 808 0x00f01b1b 1>; /* WUBEMR7 */ 809 wakeup-controller; 810 #wuc-cells = <1>; 811 }; 812 813 wuc8: wakeup-controller@f01b1c { 814 compatible = "ite,it8xxx2-wuc"; 815 reg = <0x00f01b1c 1 /* WUEMR8 */ 816 0x00f01b1d 1 /* WUESR8 */ 817 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR8 */ 818 0x00f01b1f 1>; /* WUBEMR8 */ 819 wakeup-controller; 820 #wuc-cells = <1>; 821 }; 822 823 wuc9: wakeup-controller@f01b20 { 824 compatible = "ite,it8xxx2-wuc"; 825 reg = <0x00f01b20 1 /* WUEMR9 */ 826 0x00f01b21 1 /* WUESR9 */ 827 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR9 */ 828 0x00f01b23 1>; /* WUBEMR9 */ 829 wakeup-controller; 830 #wuc-cells = <1>; 831 }; 832 833 wuc10: wakeup-controller@f01b24 { 834 compatible = "ite,it8xxx2-wuc"; 835 reg = <0x00f01b24 1 /* WUEMR10 */ 836 0x00f01b25 1 /* WUESR10 */ 837 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR10 */ 838 0x00f01b27 1>; /* WUBEMR10 */ 839 wakeup-controller; 840 #wuc-cells = <1>; 841 }; 842 843 wuc11: wakeup-controller@f01b28 { 844 compatible = "ite,it8xxx2-wuc"; 845 reg = <0x00f01b28 1 /* WUEMR11 */ 846 0x00f01b29 1 /* WUESR11 */ 847 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR11 */ 848 0x00f01b2b 1>; /* WUBEMR11 */ 849 wakeup-controller; 850 #wuc-cells = <1>; 851 }; 852 853 wuc12: wakeup-controller@f01b2c { 854 compatible = "ite,it8xxx2-wuc"; 855 reg = <0x00f01b2c 1 /* WUEMR12 */ 856 0x00f01b2d 1 /* WUESR12 */ 857 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR12 */ 858 0x00f01b2f 1>; /* WUBEMR12 */ 859 wakeup-controller; 860 #wuc-cells = <1>; 861 }; 862 863 wuc13: wakeup-controller@f01b30 { 864 compatible = "ite,it8xxx2-wuc"; 865 reg = <0x00f01b30 1 /* WUEMR13 */ 866 0x00f01b31 1 /* WUESR13 */ 867 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR13 */ 868 0x00f01b33 1>; /* WUBEMR13 */ 869 wakeup-controller; 870 #wuc-cells = <1>; 871 }; 872 873 wuc14: wakeup-controller@f01b34 { 874 compatible = "ite,it8xxx2-wuc"; 875 reg = <0x00f01b34 1 /* WUEMR14 */ 876 0x00f01b35 1 /* WUESR14 */ 877 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR14 */ 878 0x00f01b37 1>; /* WUBEMR14 */ 879 wakeup-controller; 880 #wuc-cells = <1>; 881 }; 882 883 wuc15: wakeup-controller@f01b38 { 884 compatible = "ite,it8xxx2-wuc"; 885 reg = <0x00f01b38 1 /* WUEMR15 */ 886 0x00f01b39 1 /* WUESR15 */ 887 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR15 */ 888 0x00f01b3b 1>; /* WUBEMR15 */ 889 wakeup-controller; 890 #wuc-cells = <1>; 891 }; 892 893 wuc16: wakeup-controller@f01b3c { 894 compatible = "ite,it8xxx2-wuc"; 895 reg = <0x00f01b3c 1 /* WUEMR16 */ 896 0x00f01b3d 1 /* WUESR16 */ 897 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR16 */ 898 0x00f01b3f 1>; /* WUBEMR16 */ 899 wakeup-controller; 900 #wuc-cells = <1>; 901 }; 902 903 i2c0: i2c@f04300 { 904 compatible = "ite,enhance-i2c"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 reg = <0x00f04300 0x0080>; 908 interrupts = <IT8XXX2_IRQ_SMB_A IRQ_TYPE_LEVEL_HIGH>; 909 interrupt-parent = <&intc>; 910 status = "disabled"; 911 port-num = <SMB_CHANNEL_A>; 912 channel-switch-sel = <I2C_CHA_LOCATE>; 913 scl-gpios = <&gpiob 3 0>; 914 sda-gpios = <&gpiob 4 0>; 915 clock-gate-offset = <CGC_OFFSET_SMBA>; 916 }; 917 918 i2c1: i2c@f04380 { 919 compatible = "ite,enhance-i2c"; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 reg = <0x00f04380 0x0080>; 923 interrupts = <IT8XXX2_IRQ_SMB_B IRQ_TYPE_LEVEL_HIGH>; 924 interrupt-parent = <&intc>; 925 status = "disabled"; 926 port-num = <SMB_CHANNEL_B>; 927 channel-switch-sel = <I2C_CHB_LOCATE>; 928 scl-gpios = <&gpioc 1 0>; 929 sda-gpios = <&gpioc 2 0>; 930 clock-gate-offset = <CGC_OFFSET_SMBB>; 931 }; 932 933 i2c2: i2c@f04400 { 934 compatible = "ite,enhance-i2c"; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 reg = <0x00f04400 0x0080>; 938 interrupts = <IT8XXX2_IRQ_SMB_C IRQ_TYPE_LEVEL_HIGH>; 939 interrupt-parent = <&intc>; 940 status = "disabled"; 941 port-num = <SMB_CHANNEL_C>; 942 channel-switch-sel = <I2C_CHC_LOCATE>; 943 scl-gpios = <&gpiof 6 0>; 944 sda-gpios = <&gpiof 7 0>; 945 clock-gate-offset = <CGC_OFFSET_SMBC>; 946 }; 947 948 i2c3: i2c@f04480 { 949 compatible = "ite,enhance-i2c"; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 reg = <0x00f04480 0x0080>; 953 interrupts = <IT8XXX2_IRQ_SMB_D IRQ_TYPE_LEVEL_HIGH>; 954 interrupt-parent = <&intc>; 955 status = "disabled"; 956 port-num = <I2C_CHANNEL_D>; 957 channel-switch-sel = <I2C_CHD_LOCATE>; 958 scl-gpios = <&gpioh 1 0>; 959 sda-gpios = <&gpioh 2 0>; 960 clock-gate-offset = <CGC_OFFSET_SMBD>; 961 }; 962 963 i2c4: i2c@f04500 { 964 compatible = "ite,enhance-i2c"; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 reg = <0x00f04500 0x0080>; 968 interrupts = <IT8XXX2_IRQ_SMB_E IRQ_TYPE_LEVEL_HIGH>; 969 interrupt-parent = <&intc>; 970 status = "disabled"; 971 port-num = <I2C_CHANNEL_E>; 972 channel-switch-sel = <I2C_CHE_LOCATE>; 973 scl-gpios = <&gpioe 0 0>; 974 sda-gpios = <&gpioe 7 0>; 975 clock-gate-offset = <CGC_OFFSET_SMBE>; 976 }; 977 978 i2c5: i2c@f04580 { 979 compatible = "ite,enhance-i2c"; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 reg = <0x00f04580 0x0080>; 983 interrupts = <IT8XXX2_IRQ_SMB_F IRQ_TYPE_LEVEL_HIGH>; 984 interrupt-parent = <&intc>; 985 status = "disabled"; 986 port-num = <I2C_CHANNEL_F>; 987 channel-switch-sel = <I2C_CHF_LOCATE>; 988 scl-gpios = <&gpioa 4 0>; 989 sda-gpios = <&gpioa 5 0>; 990 clock-gate-offset = <CGC_OFFSET_SMBF>; 991 }; 992 993 ite_uart2_wrapper: uartwrapper@f02820 { 994 compatible = "ite,it8xxx2-uart"; 995 reg = <0x00f02820 0x0020>; 996 status = "disabled"; 997 port-num = <2>; 998 gpios = <&gpiof 0 0>; 999 uart-dev = <&uart2>; 1000 }; 1001 1002 usb0: usbd@f02f00 { 1003 compatible = "ite,it82xx2-usb"; 1004 interrupts = <IT8XXX2_IRQ_USB IRQ_TYPE_LEVEL_HIGH 1005 IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH>; 1006 interrupt-parent = <&intc>; 1007 wucctrl = <&wuc_wu90>; 1008 reg = <0x00f02f00 256>; 1009 status = "disabled"; 1010 num-bidir-endpoints = <1>; 1011 num-in-endpoints = <10>; 1012 num-out-endpoints = <5>; 1013 }; 1014 1015 sha0: crypto@f03c00 { 1016 compatible = "ite,it8xxx2-sha-v2"; 1017 reg = <0x00f03c00 0x5>; 1018 status = "disabled"; 1019 }; 1020 1021 spi0: spi@f02600 { 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 compatible = "ite,it8xxx2-spi"; 1025 reg = <0x00f02600 0x34>; 1026 interrupt-parent = <&intc>; 1027 interrupts = <37 IRQ_TYPE_EDGE_RISING>; 1028 status = "disabled"; 1029 }; 1030 }; 1031}; 1032
