1/*
2 * Copyright 2022 The Chromium OS Authors
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/g4/stm32g474Xe.dtsi>
9#include <st/g4/stm32g474r(b-c-e)tx-pinctrl.dtsi>
10#include <zephyr/dt-bindings/input/input-event-codes.h>
11
12/ {
13	model = "B-G474E-DPOW1 Discovery board";
14	compatible = "st,b-g474e-dpow1";
15
16	chosen {
17		zephyr,console = &usart3;
18		zephyr,shell-uart = &usart3;
19		zephyr,sram = &sram0;
20		zephyr,flash = &flash0;
21	};
22
23	leds {
24		compatible = "gpio-leds";
25		blue_led_2: led2 {
26			gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>;
27			label = "LED_DOWN_BLUE";
28		};
29		orange_led_3: led3 {
30			gpios = <&gpiob 1 GPIO_ACTIVE_HIGH>;
31			label = "LED_LEFT_ORANGE";
32		};
33		green_led_4: led4 {
34			gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>;
35			label = "LED_RIGHT_GREEN";
36		};
37		red_led_5: led5 {
38			gpios = <&gpiob 5 GPIO_ACTIVE_HIGH>;
39			label = "LED_UP_RED";
40		};
41	};
42
43	gpio_keys {
44		compatible = "gpio-keys";
45		joystick_sel: button0 {
46			label = "JOYSTICK_SEL";
47			gpios = <&gpioc 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
48			zephyr,code = <INPUT_KEY_ENTER>;
49		};
50		joystick_left: button1 {
51			label = "JOYSTICK_LEFT";
52			gpios = <&gpioc 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
53			zephyr,code = <INPUT_KEY_LEFT>;
54		};
55		joystick_down: button2 {
56			label = "JOYSTICK_DOWN";
57			gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
58			zephyr,code = <INPUT_KEY_DOWN>;
59		};
60		joystick_right: button3 {
61			label = "JOYSTICK_RIGHT";
62			gpios = <&gpiob 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
63			zephyr,code = <INPUT_KEY_RIGHT>;
64		};
65		joystick_up: button4 {
66			label = "JOYSTICK_UP";
67			gpios = <&gpiob 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
68			zephyr,code = <INPUT_KEY_UP>;
69		};
70	};
71
72	aliases {
73		led0 = &blue_led_2;
74		led1 = &orange_led_3;
75		led2 = &green_led_4;
76		led3 = &red_led_5;
77		sw0 = &joystick_sel;
78		sw1 = &joystick_left;
79		sw2 = &joystick_down;
80		sw3 = &joystick_right;
81		sw4 = &joystick_up;
82		watchdog0 = &iwdg;
83	};
84};
85
86&clk_lsi {
87	status = "okay";
88};
89
90&clk_hsi48 {
91	status = "okay";
92};
93
94&clk_hsi {
95	status = "okay";
96};
97
98stm32_lp_tick_source: &lptim1 {
99	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
100	<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
101	status = "okay";
102};
103
104&pll {
105	div-m = <1>;
106	mul-n = <16>;
107	div-p = <7>;
108	div-q = <2>;
109	div-r = <2>;
110	clocks = <&clk_hsi>;
111	status = "okay";
112};
113
114&rcc {
115	clocks = <&pll>;
116	clock-frequency = <DT_FREQ_M(128)>;
117	ahb-prescaler = <1>;
118	apb1-prescaler = <1>;
119	apb2-prescaler = <1>;
120};
121
122&usart3 {
123	pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11>;
124	pinctrl-1 = <&analog_pc10 &analog_pc11>;
125	pinctrl-names = "default", "sleep";
126	current-speed = <115200>;
127	status = "okay";
128};
129
130&iwdg {
131	status = "okay";
132};
133
134&adc2 {
135	pinctrl-0 = <&adc2_in8_pc2>;
136	pinctrl-names = "default";
137	st,adc-clock-source = "SYNC";
138	st,adc-prescaler = <4>;
139	status = "okay";
140
141	#address-cells = <1>;
142	#size-cells = <0>;
143
144	channel@8 {
145		reg = <8>;
146		zephyr,gain = "ADC_GAIN_1";
147		zephyr,reference = "ADC_REF_INTERNAL";
148		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
149		zephyr,resolution = <12>;
150		zephyr,vref-mv = <3300>;
151	};
152};
153
154&ucpd1 {
155	status = "okay";
156
157	/*
158	 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
159	 * a prescaler who's output feeds the 'half-bit' divider which is used
160	 * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
161	 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
162	 * range is 9 <--> 18 MHz.
163	 *
164	 *          +-------+ @ 16 MHz +-------+   @ ~600 kHz   +-----------+
165	 * HSI ---->| /psc  |--------->| /hbit |--------------->| trans_cnt |
166	 *          +-------+          +-------+   |            +-----------+
167	 *                                         |            +-----------+
168	 *                                         +----------->| ifrgap_cnt|
169	 *                                                      +-----------+
170	 * Requirements:
171	 *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
172	 *   2. tTransitionWindow - 12 to 20 uSec
173	 *   3. tInterframGap - uSec
174	 *
175	 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
176	 * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
177	 * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
178	 */
179	psc-ucpdclk = <1>;
180	hbitclkdiv = <27>;
181	pinctrl-0 = <&ucpd1_cc1_pb6 &ucpd1_cc2_pb4>;
182	pinctrl-names = "default";
183};
184
185zephyr_udc0: &usb {
186	pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
187	pinctrl-names = "default";
188	status = "okay";
189};
190