Searched refs:and (Results 3776 – 3800 of 3855) sorted by relevance
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103 * configuration to pass PWM signal on pins 0 and 1. First valid config is P9.2.
233 * and is calculated as ((15.625 * SDRAM_CLK_MHZ) - 20)
210 /* I2C1, Raspberry Pi and Groove connectors */
259 * control in a distributed way (GPIO registers and PSEL
293 * control in a distributed way (GPIO registers and PSEL
136 /* Side with battery connector (with CC1352 and not MSP430) */
256 * The flash starting at 0x000f8000 and ending at
55 and r0, r0, #MODE_MASK
10 * (and be extended to test) real hardware.
231 /* MX25R64 supports only pp and pp4io */
67 <11 0 &gpio4 7 0>; /* Pin 11, LCD and touch reset */
65 #warning CONFIG_BT_L2CAP_TX_MTU is too large and can result in packets that cannot \
42 /* Usable RAM is after the exception vectors and page-aligned. */360 * and the beginning of .text. We can put exception handling
58 * between code and data. Boards can98 * addresses differ between non-secure (0x40000000) and secure
132 …<mxCell id="Db8zi3n4dXzB52SZQf6J-89" value="<div>iface commands and events,</div><d…135 …3n4dXzB52SZQf6J-91" value="<div>iface commands</div><div>and events</div>"…138 …n4dXzB52SZQf6J-113" value="<div>iface commands</div><div>and events</div>"…
29 commands and target utility features. To use the provisioning
244 /* MX25R64 supports only pp and pp4io */
12 /* ADC1 inputs 10 and 11 */
246 * and is calculated as ((15.625 * SDRAM_CLK_MHZ) - 20)
282 * The flash starting at 0x000f8000 and ending at
118 * The flash starting at offset 0x10000 and ending at
250 /* MX25R64 supports only pp and pp4io */
69 /* Cells for bus type, clock control reg and bit */368 /* host sub-module IRQ and priority */
126 * and uses it in preference to the first symbol in IRAM
70 /* power the ETH PHY , and FDCAN1 XVCR*/
