1/*
2 * Copyright (c) 2024 BayLibre
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <st/l4/stm32l4s5Xi.dtsi>
10#include <st/l4/stm32l4s5qiix-pinctrl.dtsi>
11#include "arduino_r3_connector.dtsi"
12#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
13
14/ {
15	model = "Analog Devices Inc. EVAL-ADIN1110EBZ board";
16	compatible = "adi,eval-adin1110ebz";
17
18	chosen {
19		zephyr,console = &usart1;
20		zephyr,shell-uart = &usart1;
21		zephyr,sram = &sram0;
22		zephyr,flash = &flash0;
23		zephyr,code-partition = &slot0_partition;
24		zephyr,flash-controller = &mx25r6435f;
25	};
26
27	ram0: psram@60000000 {
28		compatible = "zephyr,memory-region", "mmio-sram";
29		device_type = "memory";
30		reg = <0x60000000 DT_SIZE_M(8)>;
31		zephyr,memory-region = "RAM0";
32	};
33
34	leds { /* Respecting pcb silkscreen naming */
35		compatible = "gpio-leds";
36		green_led: led_uC0 {
37			gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
38			label = "Status uC0";
39		};
40		red_led: led_uC1 {
41			gpios = <&gpioe 2 GPIO_ACTIVE_LOW>;
42			label = "Status uC1 ";
43		};
44		yellow_led: led_uC2 {
45			gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
46			label = "Status uC2";
47		};
48		blue_led: led_uC3 {
49			gpios = <&gpiog 15 GPIO_ACTIVE_LOW>;
50			label = "Status uC3";
51		};
52	};
53
54	aliases {
55		led0 = &green_led;
56		watchdog0 = &iwdg;
57		ambient-temp0 = &adt7420;
58	};
59
60	soc {
61		fmc: memory-controller@a0000000 {
62			compatible = "st,stm32-fmc";
63			reg = <0xa0000000 0x400>;
64			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
65
66			sram {
67				compatible = "st,stm32-fmc-nor-psram";
68
69				#address-cells = <1>;
70				#size-cells = <0>;
71			};
72		};
73	};
74};
75
76&clk_lsi {
77	status = "okay";
78};
79
80&clk_hsi48 {
81	status = "okay";
82};
83
84&clk_hsi {
85	status = "okay";
86};
87
88&pll {
89	div-m = <4>;
90	mul-n = <40>;
91	div-q = <2>;
92	div-r = <2>;
93	clocks = <&clk_hsi>;
94	status = "okay";
95};
96
97&rcc {
98	clocks = <&pll>;
99	clock-frequency = <DT_FREQ_M(80)>;
100	ahb-prescaler = <1>;
101	apb1-prescaler = <1>;
102	apb2-prescaler = <1>;
103};
104
105&flash0 {
106	partitions {
107		compatible = "fixed-partitions";
108		#address-cells = <1>;
109		#size-cells = <1>;
110
111		boot_partition: partition@0 {
112			label = "mcuboot";
113			reg = <0x00000000 DT_SIZE_K(64)>;
114			read-only;
115		};
116
117		/*
118		 * The flash starting at offset 0x10000 and ending at
119		 * offset 0x1ffff is reserved for use by the application.
120		 */
121
122		slot0_partition: partition@20000 {
123			label = "image-0";
124			reg = <0x00020000 DT_SIZE_K(432)>;
125		};
126		slot1_partition: partition@8c000 {
127			label = "image-1";
128			reg = <0x0008C000 DT_SIZE_K(432)>;
129		};
130		scratch_partition: partition@f8000 {
131			label = "image-scratch";
132			reg = <0x000F8000 DT_SIZE_K(16)>;
133		};
134
135		storage_partition: partition@fc000 {
136			label = "storage";
137			reg = <0x000fc000 DT_SIZE_K(16)>;
138		};
139	};
140};
141
142&iwdg {
143	status = "okay";
144};
145
146&rng {
147	status = "okay";
148};
149
150&dma1 {
151	status = "okay";
152};
153
154&dmamux1 {
155	status = "okay";
156};
157
158&usart1 { /* USB FT232 */
159	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
160	pinctrl-names = "default";
161	current-speed = <115200>;
162	status = "okay";
163};
164
165&uart4 { /* ARDUINO P405 1 & 2 */
166	pinctrl-0 = <&uart4_tx_pa0 &uart4_rx_pa1>;
167	pinctrl-names = "default";
168	current-speed = <115200>;
169};
170
171&i2c1 {
172	pinctrl-0 = <&i2c1_scl_pg14 &i2c1_sda_pg13>;
173	pinctrl-names = "default";
174	status = "okay";
175	clock-frequency = <I2C_BITRATE_FAST>;
176};
177
178&i2c3 {
179	pinctrl-0 = <&i2c3_scl_pg7 &i2c3_sda_pg8>;
180	pinctrl-names = "default";
181	status = "okay";
182	clock-frequency = <I2C_BITRATE_FAST>;
183
184	adt7420: adt7420@48 {
185		compatible = "adi,adt7420";
186		reg = <0x48>;
187	};
188};
189
190&spi1 {
191	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
192	pinctrl-names = "default";
193	cs-gpios = <&gpioa 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
194};
195
196&spi2 {
197	pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;
198	pinctrl-names = "default";
199	cs-gpios = <&gpiob 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
200	dmas = <&dmamux1 2 13 (STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC |
201		       STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>,
202		       <&dmamux1 3 12 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC |
203		       STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>;
204		dma-names = "tx", "rx";
205	status = "okay";
206
207	adin1110: adin1110@0 {
208		compatible = "adi,adin1110";
209		reg = <0x0>;
210		spi-max-frequency = <25000000>;
211		int-gpios = <&gpiob 11 GPIO_ACTIVE_LOW>;
212		reset-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>;
213		status = "okay";
214		spi-oa;
215		spi-oa-protection;
216
217		port1 {
218			local-mac-address = [ 00 E0 22 FE DA C8 ];
219		};
220		mdio {
221			compatible = "adi,adin2111-mdio";
222			#address-cells = <1>;
223			#size-cells = <0>;
224
225			ethernet-phy@1 {
226				reg = <0x1>;
227				compatible = "adi,adin2111-phy";
228			};
229		};
230	};
231};
232
233&spi3 {
234	pinctrl-0 = <&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12>;
235	pinctrl-names = "default";
236	status = "okay";
237};
238
239&timers2 {
240	status = "okay";
241
242	pwm2: pwm {
243		status = "okay";
244		pinctrl-0 = <&tim2_ch1_pa15>;
245		pinctrl-names = "default";
246	};
247};
248
249&rtc {
250	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
251		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
252	status = "okay";
253};
254
255zephyr_udc0: &usbotg_fs {
256	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12
257		     &usb_otg_fs_id_pa10>;
258	pinctrl-names = "default";
259	status = "okay";
260};
261
262&octospi1 {
263	pinctrl-0 = <&octospim_p1_clk_pa3 &octospim_p1_ncs_pa4
264		     &octospim_p1_io0_pb1 &octospim_p1_io1_pb0
265		     &octospim_p1_io2_pa7 &octospim_p1_io3_pa6>;
266	pinctrl-names = "default";
267	dmas = <&dma1 0 40 0x480>; /* request 40 for OCTOSPI1 */
268	dma-names = "tx_rx";
269
270	status = "okay";
271
272	mx25r6435f: ospi-nor-flash@90000000 {
273		compatible = "st,stm32-ospi-nor";
274		reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Megabits */
275		ospi-max-frequency = <DT_FREQ_M(26)>; /* for Voltage Range 2 */
276		spi-bus-width = <OSPI_QUAD_MODE>;
277		data-rate = <OSPI_STR_TRANSFER>;
278		writeoc="PP_1_4_4";
279
280		partitions {
281			compatible = "fixed-partitions";
282			#address-cells = <1>;
283			#size-cells = <1>;
284
285			store_partition: partition@0 {
286				label = "store";
287				reg = <0x00000000 DT_SIZE_M(8)>;
288			};
289		};
290	};
291};
292
293&fmc {
294	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
295		     &fmc_nce_pd7 &fmc_nwe_pd5 &fmc_noe_pd4
296		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3
297		     &fmc_a4_pf4 &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13
298		     &fmc_a8_pf14 &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
299		     &fmc_a12_pg2 &fmc_a13_pg3 &fmc_a14_pg4 &fmc_a15_pg5
300		     &fmc_a16_pd11 &fmc_a17_pd12 &fmc_a18_pd13 &fmc_a19_pe3
301		     &fmc_a20_pe4 &fmc_a21_pe5
302		     &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1
303		     &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10
304		     &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14
305		     &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>;
306	pinctrl-names = "default";
307
308	sram {
309		bank@0 {
310			reg = <0x0>;
311			st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
312				      STM32_FMC_MEMORY_TYPE_SRAM
313				      STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
314				      STM32_FMC_BURST_ACCESS_MODE_DISABLE
315				      STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
316				      STM32_FMC_WAIT_TIMING_BEFORE_WS
317				      STM32_FMC_WRITE_OPERATION_ENABLE
318				      STM32_FMC_WAIT_SIGNAL_DISABLE
319				      STM32_FMC_EXTENDED_MODE_DISABLE
320				      STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
321				      STM32_FMC_WRITE_BURST_DISABLE
322				      STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
323				      STM32_FMC_WRITE_FIFO_DISABLE
324				      STM32_FMC_PAGE_SIZE_NONE>;
325			st,timing = <4 2 3 0 16 17 STM32_FMC_ACCESS_MODE_A>;
326		};
327	};
328};
329