1/*
2 * Copyright (c) 2016 Cadence Design Systems, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/**
8 * @file
9 * @brief Linker command/script file
10 *
11 * Linker script for the Xtensa platform.
12 */
13
14#include <xtensa/config/core-isa.h>
15
16#include <zephyr/linker/sections.h>
17
18#include <zephyr/devicetree.h>
19#include <zephyr/linker/linker-defs.h>
20#include <zephyr/linker/linker-tool.h>
21
22#define RAMABLE_REGION RAM :sram0_phdr
23#define ROMABLE_REGION RAM :sram0_phdr
24
25#ifdef CONFIG_MPU
26#define MPU_SEGMENT_SIZE_ALIGN . = ALIGN(XCHAL_MPU_ALIGN);
27#define HDR_MPU_SEGMENT_SIZE_ALIGN ALIGN(XCHAL_MPU_ALIGN)
28#define HDR_4K_OR_MPU_SEGMENT_SIZE_ALIGN ALIGN(XCHAL_MPU_ALIGN)
29#define LAST_RAM_ALIGN MPU_SEGMENT_SIZE_ALIGN
30#else
31#define MPU_SEGMENT_SIZE_ALIGN . = ALIGN(4);
32#define HDR_MPU_SEGMENT_SIZE_ALIGN ALIGN(4)
33#define HDR_4K_OR_MPU_SEGMENT_SIZE_ALIGN ALIGN(4096)
34#endif
35
36#define PHYS_SRAM0_ADDR	(DT_REG_ADDR(DT_NODELABEL(sram0)))
37#define PHYS_SRAM0_SIZE	(DT_REG_SIZE(DT_NODELABEL(sram0)))
38
39#define PHYS_ROM0_ADDR	(DT_REG_ADDR(DT_NODELABEL(srom0)))
40#define PHYS_ROM0_SIZE	(DT_REG_SIZE(DT_NODELABEL(srom0)))
41
42/* Usable RAM is after the exception vectors and page-aligned. */
43#define PHYS_RAM_ADDR	(PHYS_SRAM0_ADDR + CONFIG_SRAM_OFFSET)
44#define PHYS_RAM_SIZE	(PHYS_SRAM0_SIZE - CONFIG_SRAM_OFFSET)
45
46MEMORY
47{
48  dram1_0_seg  : org = 0x3FFC0000, len = 0x20000
49  dram0_0_seg  : org = 0x3FFE0000, len = 0x20000
50  iram0_0_seg  : org = 0x40000000, len = 0x178
51  iram0_1_seg  : org = 0x40000178, len = 0x8
52  iram0_2_seg  : org = 0x40000180, len = 0x38
53  iram0_3_seg  : org = 0x400001B8, len = 0x8
54  iram0_4_seg  : org = 0x400001C0, len = 0x38
55  iram0_5_seg  : org = 0x400001F8, len = 0x8
56  iram0_6_seg  : org = 0x40000200, len = 0x38
57  iram0_7_seg  : org = 0x40000238, len = 0x8
58  iram0_8_seg  : org = 0x40000240, len = 0x38
59  iram0_9_seg  : org = 0x40000278, len = 0x8
60  iram0_10_seg : org = 0x40000280, len = 0x38
61  iram0_11_seg : org = 0x400002B8, len = 0x8
62  iram0_12_seg : org = 0x400002C0, len = 0x38
63  iram0_13_seg : org = 0x400002F8, len = 0x8
64  iram0_14_seg : org = 0x40000300, len = 0x38
65  iram0_15_seg : org = 0x40000338, len = 0x8
66  iram0_16_seg : org = 0x40000340, len = 0x38
67  iram0_17_seg : org = 0x40000378, len = 0x48
68  iram0_18_seg : org = 0x400003C0, len = 0x40
69  iram0_19_seg : org = 0x40000400, len = 0x1FC00
70#ifdef CONFIG_MPU
71  vec_helpers  : org = 0x40002400, len = (PHYS_RAM_ADDR - 0x00002400)
72#endif
73  srom0_seg    : org = PHYS_ROM0_ADDR, len = PHYS_ROM0_SIZE
74  RAM          : org = PHYS_RAM_ADDR, len = PHYS_RAM_SIZE
75
76#ifdef CONFIG_GEN_ISR_TABLES
77  /* The space before exception vectors is not being used.
78   * So we stuff the temporary IDT_LIST there to avoid
79   * some linker issues which would balloon the size of
80   * the intermediate files (like zephyr_pre0.elf, to
81   * couple hundred MBs or even GBs).
82   */
83  IDT_LIST     : org = 0x3FFBE000, len = 0x2000
84#endif
85}
86
87PHDRS
88{
89  dram1_0_phdr PT_LOAD;
90  dram1_0_bss_phdr PT_LOAD;
91  dram0_0_phdr PT_LOAD;
92  dram0_0_bss_phdr PT_LOAD;
93  iram0_0_phdr PT_LOAD;
94  iram0_1_phdr PT_LOAD;
95  iram0_2_phdr PT_LOAD;
96  iram0_3_phdr PT_LOAD;
97  iram0_4_phdr PT_LOAD;
98  iram0_5_phdr PT_LOAD;
99  iram0_6_phdr PT_LOAD;
100  iram0_7_phdr PT_LOAD;
101  iram0_8_phdr PT_LOAD;
102  iram0_9_phdr PT_LOAD;
103  iram0_10_phdr PT_LOAD;
104  iram0_11_phdr PT_LOAD;
105  iram0_12_phdr PT_LOAD;
106  iram0_13_phdr PT_LOAD;
107  iram0_14_phdr PT_LOAD;
108  iram0_15_phdr PT_LOAD;
109  iram0_16_phdr PT_LOAD;
110  iram0_17_phdr PT_LOAD;
111  iram0_18_phdr PT_LOAD;
112
113#ifdef CONFIG_XTENSA_MPU
114  vec_helpers_phdr PT_LOAD;
115#endif
116
117  srom0_phdr PT_LOAD;
118  sram0_phdr PT_LOAD;
119  sram0_bss_phdr PT_LOAD;
120}
121
122
123/*  Default entry point:  */
124ENTRY(CONFIG_KERNEL_ENTRY)
125
126_rom_store_table = 0;
127
128PROVIDE(_memmap_vecbase_reset = 0x40000000);
129PROVIDE(_memmap_reset_vector = 0x50000000);
130
131/* Various memory-map dependent cache attribute settings: */
132_memmap_cacheattr_wb_base = 0x00001110;
133_memmap_cacheattr_wt_base = 0x00001110;
134_memmap_cacheattr_bp_base = 0x00002220;
135_memmap_cacheattr_unused_mask = 0xFFFF000F;
136_memmap_cacheattr_wb_trapnull = 0x2222111F;
137_memmap_cacheattr_wba_trapnull = 0x2222111F;
138_memmap_cacheattr_wbna_trapnull = 0x2222111F;
139_memmap_cacheattr_wt_trapnull = 0x2222111F;
140_memmap_cacheattr_bp_trapnull = 0x2222222F;
141_memmap_cacheattr_wb_strict = 0xFFFF111F;
142_memmap_cacheattr_wt_strict = 0xFFFF111F;
143_memmap_cacheattr_bp_strict = 0xFFFF222F;
144_memmap_cacheattr_wb_allvalid = 0x22221112;
145_memmap_cacheattr_wt_allvalid = 0x22221112;
146_memmap_cacheattr_bp_allvalid = 0x22222222;
147PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_bp_trapnull);
148
149SECTIONS
150{
151
152#include <zephyr/linker/rel-sections.ld>
153
154#ifdef CONFIG_GEN_ISR_TABLES
155#include <zephyr/linker/intlist.ld>
156#endif
157
158  .dram1.rodata : ALIGN(4)
159  {
160    _dram1_rodata_start = ABSOLUTE(.);
161    *(.dram1.rodata)
162    _dram1_rodata_end = ABSOLUTE(.);
163  } >dram1_0_seg :dram1_0_phdr
164
165  .dram1.literal : ALIGN(4)
166  {
167    _dram1_literal_start = ABSOLUTE(.);
168    *(.dram1.literal)
169    _dram1_literal_end = ABSOLUTE(.);
170  } >dram1_0_seg :dram1_0_phdr
171
172  .dram1.data : ALIGN(4)
173  {
174    _dram1_data_start = ABSOLUTE(.);
175    *(.dram1.data)
176    _dram1_data_end = ABSOLUTE(.);
177  } >dram1_0_seg :dram1_0_phdr
178
179  .dram1.bss (NOLOAD) : ALIGN(8)
180  {
181    . = ALIGN (8);
182    _dram1_bss_start = ABSOLUTE(.);
183    *(.dram1.bss)
184    . = ALIGN (8);
185    _dram1_bss_end = ABSOLUTE(.);
186    _memmap_seg_dram1_0_end = ALIGN(0x8);
187  } >dram1_0_seg :dram1_0_bss_phdr
188
189  .dram0.rodata : ALIGN(4)
190  {
191    _dram0_rodata_start = ABSOLUTE(.);
192    *(.dram0.rodata)
193    _dram0_rodata_end = ABSOLUTE(.);
194  } >dram0_0_seg :dram0_0_phdr
195
196  .dram0.literal : ALIGN(4)
197  {
198    _dram0_literal_start = ABSOLUTE(.);
199    *(.dram0.literal)
200    _dram0_literal_end = ABSOLUTE(.);
201  } >dram0_0_seg :dram0_0_phdr
202
203  .dram0.data : ALIGN(4)
204  {
205    _dram0_data_start = ABSOLUTE(.);
206    *(.dram0.data)
207    _dram0_data_end = ABSOLUTE(.);
208  } >dram0_0_seg :dram0_0_phdr
209
210  .dram0.bss (NOLOAD) : ALIGN(8)
211  {
212    . = ALIGN (8);
213    _dram0_bss_start = ABSOLUTE(.);
214    *(.dram0.bss)
215    . = ALIGN (8);
216    _dram0_bss_end = ABSOLUTE(.);
217    _memmap_seg_dram0_0_end = ALIGN(0x8);
218  } >dram0_0_seg :dram0_0_bss_phdr
219
220  .WindowVectors.text : ALIGN(4)
221  {
222    _WindowVectors_text_start = ABSOLUTE(.);
223    KEEP (*(.WindowVectors.text))
224    _WindowVectors_text_end = ABSOLUTE(.);
225  } >iram0_0_seg :iram0_0_phdr
226
227  .Level2InterruptVector.literal : ALIGN(4)
228  {
229    _Level2InterruptVector_literal_start = ABSOLUTE(.);
230    *(.Level2InterruptVector.literal)
231    _Level2InterruptVector_literal_end = ABSOLUTE(.);
232  } >iram0_1_seg :iram0_1_phdr
233
234  .Level2InterruptVector.text : ALIGN(4)
235  {
236    _Level2InterruptVector_text_start = ABSOLUTE(.);
237    KEEP (*(.Level2InterruptVector.text))
238    _Level2InterruptVector_text_end = ABSOLUTE(.);
239  } >iram0_2_seg :iram0_2_phdr
240
241  .Level3InterruptVector.literal : ALIGN(4)
242  {
243    _Level3InterruptVector_literal_start = ABSOLUTE(.);
244    *(.Level3InterruptVector.literal)
245    _Level3InterruptVector_literal_end = ABSOLUTE(.);
246  } >iram0_3_seg :iram0_3_phdr
247
248  .Level3InterruptVector.text : ALIGN(4)
249  {
250    _Level3InterruptVector_text_start = ABSOLUTE(.);
251    KEEP (*(.Level3InterruptVector.text))
252    _Level3InterruptVector_text_end = ABSOLUTE(.);
253  } >iram0_4_seg :iram0_4_phdr
254
255  .Level4InterruptVector.literal : ALIGN(4)
256  {
257    _Level4InterruptVector_literal_start = ABSOLUTE(.);
258    *(.Level4InterruptVector.literal)
259    _Level4InterruptVector_literal_end = ABSOLUTE(.);
260  } >iram0_5_seg :iram0_5_phdr
261
262  .Level4InterruptVector.text : ALIGN(4)
263  {
264    _Level4InterruptVector_text_start = ABSOLUTE(.);
265    KEEP (*(.Level4InterruptVector.text))
266    _Level4InterruptVector_text_end = ABSOLUTE(.);
267  } >iram0_6_seg :iram0_6_phdr
268
269  .Level5InterruptVector.literal : ALIGN(4)
270  {
271    _Level5InterruptVector_literal_start = ABSOLUTE(.);
272    *(.Level5InterruptVector.literal)
273    _Level5InterruptVector_literal_end = ABSOLUTE(.);
274  } >iram0_7_seg :iram0_7_phdr
275
276  .Level5InterruptVector.text : ALIGN(4)
277  {
278    _Level5InterruptVector_text_start = ABSOLUTE(.);
279    KEEP (*(.Level5InterruptVector.text))
280    _Level5InterruptVector_text_end = ABSOLUTE(.);
281  } >iram0_8_seg :iram0_8_phdr
282
283  .DebugExceptionVector.literal : ALIGN(4)
284  {
285    _DebugExceptionVector_literal_start = ABSOLUTE(.);
286    *(.DebugExceptionVector.literal)
287    _DebugExceptionVector_literal_end = ABSOLUTE(.);
288  } >iram0_9_seg :iram0_9_phdr
289
290  .DebugExceptionVector.text : ALIGN(4)
291  {
292    _DebugExceptionVector_text_start = ABSOLUTE(.);
293    KEEP (*(.DebugExceptionVector.text))
294    _DebugExceptionVector_text_end = ABSOLUTE(.);
295  } >iram0_10_seg :iram0_10_phdr
296
297  .NMIExceptionVector.literal : ALIGN(4)
298  {
299    _NMIExceptionVector_literal_start = ABSOLUTE(.);
300    *(.NMIExceptionVector.literal)
301    _NMIExceptionVector_literal_end = ABSOLUTE(.);
302  } >iram0_11_seg :iram0_11_phdr
303
304  .NMIExceptionVector.text : ALIGN(4)
305  {
306    _NMIExceptionVector_text_start = ABSOLUTE(.);
307    KEEP (*(.NMIExceptionVector.text))
308    _NMIExceptionVector_text_end = ABSOLUTE(.);
309  } >iram0_12_seg :iram0_12_phdr
310
311  .KernelExceptionVector.literal : ALIGN(4)
312  {
313    _KernelExceptionVector_literal_start = ABSOLUTE(.);
314    *(.KernelExceptionVector.literal)
315    _KernelExceptionVector_literal_end = ABSOLUTE(.);
316  } >iram0_13_seg :iram0_13_phdr
317
318  .KernelExceptionVector.text : ALIGN(4)
319  {
320    _KernelExceptionVector_text_start = ABSOLUTE(.);
321    KEEP (*(.KernelExceptionVector.text))
322    _KernelExceptionVector_text_end = ABSOLUTE(.);
323  } >iram0_14_seg :iram0_14_phdr
324
325  .UserExceptionVector.literal : ALIGN(4)
326  {
327    _UserExceptionVector_literal_start = ABSOLUTE(.);
328    *(.UserExceptionVector.literal)
329    _UserExceptionVector_literal_end = ABSOLUTE(.);
330  } >iram0_15_seg :iram0_15_phdr
331
332  .UserExceptionVector.text : ALIGN(4)
333  {
334    _UserExceptionVector_text_start = ABSOLUTE(.);
335    KEEP (*(.UserExceptionVector.text))
336    _UserExceptionVector_text_end = ABSOLUTE(.);
337  } >iram0_16_seg :iram0_16_phdr
338
339  .DoubleExceptionVector.literal : ALIGN(4)
340  {
341    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
342    *(.DoubleExceptionVector.literal)
343    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
344  } >iram0_17_seg :iram0_17_phdr
345
346  .DoubleExceptionVector.text : ALIGN(4)
347  {
348    _DoubleExceptionVector_text_start = ABSOLUTE(.);
349    KEEP (*(.DoubleExceptionVector.text))
350    _DoubleExceptionVector_text_end = ABSOLUTE(.);
351  } >iram0_18_seg :iram0_18_phdr
352
353#define LIB_OBJ_FUNC_IN_SECT(library, obj_file, func)		\
354	*##library##:##obj_file##(.literal.##func .text.##func)	\
355
356#ifdef CONFIG_XTENSA_MPU
357  .vec_helpers :
358  {
359    /* There is quite some space between .DoubleExceptionVector
360     * and the beginning of .text. We can put exception handling
361     * code here.
362     */
363
364    *libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.literal .text)
365    *libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.iram.text .iram0.text)
366
367    *libarch__xtensa__core.a:window_vectors.S.obj(.iram.text)
368
369    *libarch__xtensa__core.a:crt1.S.obj(.literal .text)
370
371    LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,xtensa_asm2.c.obj,*)
372    LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,fatal.c.obj,*)
373    LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,cpu_idle.c.obj,*)
374
375    *(.literal.arch_is_in_isr .text.arch_is_in_isr)
376
377    /* To support backtracing */
378    LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,xtensa_backtrace.c.obj,*)
379
380    *libarch__xtensa__core.a:debug_helpers_asm.S.obj(.iram1.literal .iram1)
381
382    /* Userspace related stuff */
383    LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,userspace.S.obj,xtensa_do_syscall)
384
385    /* Below are to speed up execution by avoiding TLB misses
386     * on frequently used functions.
387     *
388     * There is almost 1MB space (due to TLB pinning) so we can
389     * be generous.
390     */
391    LIB_OBJ_FUNC_IN_SECT(libkernel.a,,*)
392
393    LIB_OBJ_FUNC_IN_SECT(libdrivers__console.a,,*)
394    LIB_OBJ_FUNC_IN_SECT(libdrivers__timer.a,,*)
395
396    *(.literal.z_vrfy_* .text.z_vrfy_*)
397    *(.literal.z_mrsh_* .text.z_mrsh_*)
398    *(.literal.z_impl_* .text.z_impl_*)
399    *(.literal.z_obj_*  .text.z_obj_*)
400
401    *(.literal.k_sys_fatal_error_handler .text.k_sys_fatal_error_handler)
402  } >vec_helpers :vec_helpers_phdr
403#endif /* CONFIG_XTENSA_MPU */
404
405#ifdef CONFIG_CODE_DATA_RELOCATION
406#include <linker_relocate.ld>
407#endif
408
409  .ResetVector.text : ALIGN(4)
410  {
411    __rom_region_start = ABSOLUTE(.);
412    _ResetVector_text_start = ABSOLUTE(.);
413    KEEP (*(.ResetVector.text))
414    _ResetVector_text_end = ABSOLUTE(.);
415  } >srom0_seg :srom0_phdr
416
417  .text : HDR_MPU_SEGMENT_SIZE_ALIGN
418  {
419    _stext = .;
420    __text_region_start = .;
421    z_mapped_start = .;
422    _text_start = ABSOLUTE(.);
423    *(.entry.text)
424    *(.init.literal)
425    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
426    *(.iram1.literal .iram1)
427    KEEP(*(.init))
428    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
429    *(.fini.literal)
430    KEEP(*(.fini))
431    *(.gnu.version)
432
433    #include <zephyr/linker/kobject-text.ld>
434
435    MPU_SEGMENT_SIZE_ALIGN
436
437    _text_end = ABSOLUTE(.);
438    _etext = .;
439  } >RAMABLE_REGION
440  __text_region_end = .;
441
442  .rodata : HDR_MPU_SEGMENT_SIZE_ALIGN
443  {
444    __rodata_region_start = ABSOLUTE(.);
445    *(.rodata)
446    *(.rodata.*)
447    *(.gnu.linkonce.r.*)
448    *(.rodata1)
449
450    . = ALIGN(4);
451    #include <snippets-rodata.ld>
452    #include <zephyr/linker/kobject-rom.ld>
453  } >RAMABLE_REGION
454
455#include <zephyr/linker/common-rom.ld>
456
457#include <zephyr/linker/thread-local-storage.ld>
458
459#include <zephyr/linker/cplusplus-rom.ld>
460
461  .rodata_end : ALIGN(4)
462  {
463    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
464    _bss_table_start = ABSOLUTE(.);
465    LONG(_bss_start)
466    LONG(_bss_end)
467    _bss_table_end = ABSOLUTE(.);
468
469    MPU_SEGMENT_SIZE_ALIGN
470
471    __rodata_region_end = ABSOLUTE(.);
472  } >RAMABLE_REGION
473
474#ifdef CONFIG_USERSPACE
475#define SMEM_PARTITION_ALIGN(size) MPU_SEGMENT_SIZE_ALIGN
476#define APP_SHARED_ALIGN  MPU_SEGMENT_SIZE_ALIGN
477
478#include <app_smem.ld>
479
480  _image_ram_start = _app_smem_start;
481  _app_smem_size = _app_smem_end - _app_smem_start;
482  _app_smem_num_words = _app_smem_size >> 2;
483  _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
484  _app_smem_num_words = _app_smem_size >> 2;
485#endif /* CONFIG_USERSPACE */
486
487  .data : HDR_MPU_SEGMENT_SIZE_ALIGN
488  {
489#ifndef CONFIG_USERSPACE
490    _image_ram_start = ABSOLUTE(.);
491#endif
492    __data_start = ABSOLUTE(.);
493    *(.data)
494    *(.data.*)
495    *(.gnu.linkonce.d.*)
496    KEEP(*(.gnu.linkonce.d.*personality*))
497    *(.data1)
498    *(.sdata)
499    *(.sdata.*)
500    *(.gnu.linkonce.s.*)
501    *(.sdata2)
502    *(.sdata2.*)
503    *(.gnu.linkonce.s2.*)
504    KEEP(*(.jcr))
505
506    . = ALIGN(4);
507    #include <snippets-rwdata.ld>
508    . = ALIGN(4);
509
510    MPU_SEGMENT_SIZE_ALIGN
511
512    __data_end = ABSOLUTE(.);
513  } >RAMABLE_REGION
514
515#include <snippets-sections.ld>
516
517#include <snippets-data-sections.ld>
518
519#include <zephyr/linker/common-ram.ld>
520
521#include <zephyr/linker/cplusplus-ram.ld>
522
523#include <snippets-ram-sections.ld>
524
525  .bss (NOLOAD) : HDR_MPU_SEGMENT_SIZE_ALIGN
526  {
527    . = ALIGN (8);
528    _bss_start = ABSOLUTE(.);
529    *(.dynsbss)
530    *(.sbss)
531    *(.sbss.*)
532    *(.gnu.linkonce.sb.*)
533    *(.scommon)
534    *(.sbss2)
535    *(.sbss2.*)
536    *(.gnu.linkonce.sb2.*)
537    *(.dynbss)
538    *(.bss)
539    *(.bss.*)
540    *(.gnu.linkonce.b.*)
541    *(COMMON)
542    *(.sram.bss)
543    . = ALIGN (8);
544    _bss_end = ABSOLUTE(.);
545
546    MPU_SEGMENT_SIZE_ALIGN
547
548  } >RAM :sram0_bss_phdr
549
550#include <zephyr/linker/common-noinit.ld>
551
552/* Must be last in RAM */
553#include <zephyr/linker/kobject-data.ld>
554
555#include <zephyr/linker/ram-end.ld>
556
557  _heap_start = .;
558
559  PROVIDE(_heap_sentry = ORIGIN(RAM) + LENGTH(RAM));
560  PROVIDE(_heap_end = ORIGIN(RAM) + LENGTH(RAM));
561
562  PROVIDE(__stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE);
563
564#include <zephyr/linker/debug-sections.ld>
565
566  .xtensa.info  0 :  { *(.xtensa.info) }
567  .xt.insn 0 :
568  {
569    KEEP (*(.xt.insn))
570    KEEP (*(.gnu.linkonce.x.*))
571  }
572  .xt.prop 0 :
573  {
574    KEEP (*(.xt.prop))
575    KEEP (*(.xt.prop.*))
576    KEEP (*(.gnu.linkonce.prop.*))
577  }
578  .xt.lit 0 :
579  {
580    KEEP (*(.xt.lit))
581    KEEP (*(.xt.lit.*))
582    KEEP (*(.gnu.linkonce.p.*))
583  }
584  .debug.xt.callgraph 0 :
585  {
586    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
587  }
588}
589