1/*
2 * Copyright (c) 2018 Yurii Hamann
3 * Copyright (c) 2022, Rtone.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/dts-v1/;
9#include <st/f7/stm32f750X8.dtsi>
10#include <st/f7/stm32f750n8hx-pinctrl.dtsi>
11#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
12#include "arduino_r3_connector.dtsi"
13#include <zephyr/dt-bindings/input/input-event-codes.h>
14
15/ {
16	model = "STMicroelectronics STM32F7508-DK";
17	compatible = "st,stm32f7508_dk";
18
19	chosen {
20		zephyr,console = &usart1;
21		zephyr,shell-uart = &usart1;
22		zephyr,sram = &sram0;
23		zephyr,flash = &flash0;
24		zephyr,dtcm = &dtcm;
25		zephyr,flash-controller = &n25q128a1;
26		zephyr,display = &ltdc;
27		zephyr,touch = &ft5336;
28	};
29
30	leds {
31		compatible = "gpio-leds";
32		green_led_1: led_1 {
33			gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>;
34			label = "User LD1";
35		};
36	};
37
38	gpio_keys {
39		compatible = "gpio-keys";
40		user_button: button {
41			label = "User";
42			gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
43			zephyr,code = <INPUT_KEY_0>;
44		};
45	};
46
47	lvgl_pointer {
48		compatible = "zephyr,lvgl-pointer-input";
49		input = <&ft5336>;
50	};
51
52	sdram1: sdram@c0000000 {
53		compatible = "zephyr,memory-region", "mmio-sram";
54		device_type = "memory";
55		reg = <0xc0000000 DT_SIZE_M(16)>;
56		zephyr,memory-region = "SDRAM1";
57		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
58	};
59
60	aliases {
61		led0 = &green_led_1;
62		sw0 = &user_button;
63	};
64};
65
66&clk_lsi {
67	status = "okay";
68};
69
70&clk_hse {
71	clock-frequency = <DT_FREQ_M(25)>;
72	status = "okay";
73};
74
75&pll {
76	div-m = <25>;
77	mul-n = <432>;
78	div-p = <2>;
79	div-q = <9>;
80	clocks = <&clk_hse>;
81	status = "okay";
82};
83
84&rcc {
85	clocks = <&pll>;
86	clock-frequency = <DT_FREQ_M(216)>;
87	ahb-prescaler = <1>;
88	apb1-prescaler = <4>;
89	apb2-prescaler = <2>;
90};
91
92&i2c1 {
93	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
94	pinctrl-names = "default";
95	status = "okay";
96	clock-frequency = <I2C_BITRATE_FAST>;
97};
98
99&i2c3 {
100	pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
101	pinctrl-names = "default";
102	status = "okay";
103	clock-frequency = <I2C_BITRATE_FAST>;
104
105	ft5336: ft5336@38 {
106		compatible = "focaltech,ft5336";
107		reg = <0x38>;
108		int-gpios = <&gpioi 13 0>;
109	};
110};
111
112&spi2 {
113	pinctrl-0 = <&spi2_sck_pi1 &spi2_miso_pb14 &spi2_mosi_pb15>;
114	pinctrl-names = "default";
115	cs-gpios = <&gpioa 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
116	status = "okay";
117};
118
119&usart1 {
120	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pb7>;
121	pinctrl-names = "default";
122	current-speed = <115200>;
123	status = "okay";
124};
125
126&usart6 {
127	pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
128	pinctrl-names = "default";
129	current-speed = <115200>;
130	status = "okay";
131};
132
133zephyr_udc0: &usbotg_fs {
134	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
135	pinctrl-names = "default";
136	status = "okay";
137};
138
139&timers3 {
140	st,prescaler = <10000>;
141	status = "okay";
142
143	pwm3: pwm {
144		status = "okay";
145		pinctrl-0 = <&tim3_ch1_pb4>;
146		pinctrl-names = "default";
147	};
148};
149
150&rtc {
151	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
152		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
153	status = "okay";
154};
155
156&sdmmc1 {
157	status = "okay";
158	pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
159		     &sdmmc1_d2_pc10 &sdmmc1_d3_pc11
160		     &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
161	pinctrl-names = "default";
162	cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
163};
164
165&mac {
166	status = "okay";
167	pinctrl-0 = <&eth_mdc_pc1
168		     &eth_rxd0_pc4
169		     &eth_rxd1_pc5
170		     &eth_ref_clk_pa1
171		     &eth_mdio_pa2
172		     &eth_crs_dv_pa7
173		     &eth_tx_en_pg11
174		     &eth_txd0_pg13
175		     &eth_txd1_pg14>;
176	pinctrl-names = "default";
177};
178
179&quadspi {
180	pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pb6
181		     &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pd12
182		     &quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pd13>;
183	pinctrl-names = "default";
184	status = "okay";
185
186	n25q128a1: qspi-nor-flash@90000000 {
187		compatible = "st,stm32-qspi-nor";
188		reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */
189		qspi-max-frequency = <72000000>;
190		status = "okay";
191
192		partitions {
193			compatible = "fixed-partitions";
194			#address-cells = <1>;
195			#size-cells = <1>;
196
197			slot1_partition: partition@0 {
198				label = "image-1";
199				reg = <0x00000000 DT_SIZE_K(640)>;
200				};
201
202			storage_partition: partition@a0000 {
203				label = "storage";
204				reg = <0x000a0000 DT_SIZE_M(15)>;
205			};
206		};
207	};
208};
209
210&fmc {
211	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
212		     &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke0_pc3
213		     &fmc_sdne0_ph3 &fmc_sdnras_pf11 &fmc_sdncas_pg15
214		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
215		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
216		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
217		     &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
218		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
219		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
220		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
221		     &fmc_d15_pd10>;
222	pinctrl-names = "default";
223	status = "okay";
224
225	sdram {
226		status = "okay";
227		power-up-delay = <100>;
228		num-auto-refresh = <8>;
229		mode-register = <0x220>;
230		/*
231		 * Auto refresh command shall be issued every 15.625 us
232		 * and is calculated as ((15.625 * SDRAM_CLK_MHZ) - 20)
233		 * Note: SDRAM_CLK_MHZ = HCLK_MHZ / 2 (108 MHz)
234		 */
235		refresh-rate = <1667>;
236		bank@0 {
237			reg = <0>;
238			st,sdram-control = <STM32_FMC_SDRAM_NC_8
239						STM32_FMC_SDRAM_NR_12
240						STM32_FMC_SDRAM_MWID_16
241						STM32_FMC_SDRAM_NB_4
242						STM32_FMC_SDRAM_CAS_2
243						STM32_FMC_SDRAM_SDCLK_PERIOD_2
244						STM32_FMC_SDRAM_RBURST_ENABLE
245						STM32_FMC_SDRAM_RPIPE_0>;
246			st,sdram-timing = <2 6 4 6 2 2 2>;
247		};
248	};
249};
250
251&ltdc {
252	pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
253		     &ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
254		     &ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
255		     &ltdc_g4_pj11 &ltdc_g5_pk0 &ltdc_g6_pk1 &ltdc_g7_pk2
256		     &ltdc_b0_pe4 &ltdc_b1_pj13 &ltdc_b2_pj14 &ltdc_b3_pj15
257		     &ltdc_b4_pg12 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
258		     &ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi10 &ltdc_vsync_pi9>;
259	pinctrl-names = "default";
260	disp-on-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
261	bl-ctrl-gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
262	ext-sdram = <&sdram1>;
263	status = "okay";
264
265	width = <480>;
266	height = <272>;
267	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
268	display-timings {
269		compatible = "zephyr,panel-timing";
270		de-active = <0>;
271		pixelclk-active = <0>;
272		hsync-active = <0>;
273		vsync-active = <0>;
274		hsync-len = <1>;
275		vsync-len = <10>;
276		hback-porch = <43>;
277		vback-porch = <12>;
278		hfront-porch = <8>;
279		vfront-porch = <4>;
280	};
281	def-back-color-red = <0xFF>;
282	def-back-color-green = <0xFF>;
283	def-back-color-blue = <0xFF>;
284};
285