1/*
2 * Copyright (c) 2024 Felipe Neves
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/h7/stm32h753Xi.dtsi>
9#include <st/h7/stm32h753bitx-pinctrl.dtsi>
10#include <zephyr/dt-bindings/input/input-event-codes.h>
11
12/ {
13	model = "Witte Technology STM32H753ZI Linum board";
14	compatible = "witte,linum";
15
16	chosen {
17		zephyr,console = &usart1;
18		zephyr,shell-uart = &usart1;
19		zephyr,sram = &sram0;
20		zephyr,flash = &flash0;
21		zephyr,dtcm = &dtcm;
22		zephyr,code-partition = &slot0_partition;
23		zephyr,canbus = &fdcan1;
24	};
25
26	sdram1: sdram@c0000000 {
27		compatible = "zephyr,memory-region", "mmio-sram";
28		device_type = "memory";
29		reg = <0xc0000000 DT_SIZE_M(8)>;
30		zephyr,memory-region = "SDRAM1";
31		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
32	};
33
34	leds: leds {
35		compatible = "gpio-leds";
36		green_led: led_0 {
37			gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
38			label = "User LD1";
39		};
40		red_led: led_1 {
41			gpios = <&gpiob 2 GPIO_ACTIVE_LOW>;
42			label = "User LD2";
43		};
44		blue_led: led_2 {
45			gpios = <&gpiog 3 GPIO_ACTIVE_LOW>;
46			label = "User LD3";
47		};
48
49	};
50
51	aliases {
52		led0 = &green_led;
53		led1 = &blue_led;
54	};
55};
56
57&gpiod {
58	status = "okay";
59
60	/* power the SD card */
61	mcu-sel-gpios {
62		gpio-hog;
63		gpios = <7 GPIO_ACTIVE_HIGH>;
64		output-high;
65	};
66};
67
68&gpioi {
69	status = "okay";
70	/* power the ETH PHY , and FDCAN1 XVCR*/
71	mcu-sel-gpios {
72		gpio-hog;
73		gpios = <2 GPIO_ACTIVE_HIGH>,
74				<4 GPIO_ACTIVE_HIGH>;
75
76		output-high;
77	};
78};
79
80&gpioe {
81	status = "okay";
82
83	/* power FDCAN2 XVCR*/
84	mcu-sel-gpios {
85		gpio-hog;
86		gpios = <2 GPIO_ACTIVE_HIGH>,
87				<4 GPIO_ACTIVE_HIGH>;
88
89		output-high;
90	};
91};
92
93&clk_lsi {
94	status = "okay";
95};
96
97&clk_hsi48 {
98	status = "okay";
99};
100
101&clk_hse {
102	/delete-property/ hse-bypass;
103	clock-frequency = <DT_FREQ_M(25)>;
104	status = "okay";
105};
106
107&pll {
108	div-m = <5>;
109	mul-n = <192>;
110	div-p = <2>;
111	div-q = <4>;
112	div-r = <4>;
113	clocks = <&clk_hse>;
114	status = "okay";
115};
116
117&pll2 {
118	div-m = <2>;
119	mul-n = <48>;
120	div-p = <8>;
121	div-q = <40>;
122	div-r = <3>;
123	clocks = <&clk_hse>;
124	status = "okay";
125};
126
127&rcc {
128	clocks = <&pll>;
129	clock-frequency = <DT_FREQ_M(480)>;
130	d1cpre = <1>;
131	hpre = <2>;
132	d1ppre = <2>;
133	d2ppre1 = <2>;
134	d2ppre2 = <2>;
135	d3ppre = <2>;
136};
137
138&usart1 {
139	pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>;
140	pinctrl-names = "default";
141	current-speed = <115200>;
142	status = "okay";
143};
144
145&usart2 {
146	pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
147	pinctrl-names = "default";
148	current-speed = <115200>;
149	status = "okay";
150};
151
152&usart3 {
153	pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
154	pinctrl-names = "default";
155	current-speed = <115200>;
156	status = "okay";
157};
158
159&uart4 {
160	pinctrl-0 = <&uart4_tx_pb9 &uart4_rx_pb8>;
161	pinctrl-names = "default";
162	current-speed = <115200>;
163	status = "okay";
164};
165
166&usart6 {
167	pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
168	pinctrl-names = "default";
169	current-speed = <115200>;
170	status = "okay";
171};
172
173zephyr_udc0: &usbotg_fs {
174	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
175	pinctrl-names = "default";
176	status = "okay";
177};
178
179&rtc {
180	clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
181		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
182	status = "okay";
183};
184
185&i2c3 {
186	pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
187	pinctrl-names = "default";
188	status = "okay";
189	clock-frequency = <I2C_BITRATE_FAST>;
190};
191
192&timers12 {
193	st,prescaler = <10000>;
194	status = "okay";
195
196	pwm12: pwm {
197		status = "okay";
198		pinctrl-0 = <&tim12_ch1_pb14>;
199		pinctrl-names = "default";
200	};
201};
202
203&adc1 {
204	pinctrl-0 = <&adc1_inp15_pa3>;
205	pinctrl-names = "default";
206	st,adc-clock-source = "SYNC";
207	st,adc-prescaler = <4>;
208	status = "okay";
209};
210
211&rng {
212	status = "okay";
213};
214
215&fdcan1 {
216	clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
217		 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
218	pinctrl-0 = <&fdcan1_tx_ph13 &fdcan1_rx_ph14>;
219	pinctrl-names = "default";
220	status = "okay";
221};
222
223&fdcan2 {
224	clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
225		 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
226	pinctrl-0 = <&fdcan2_rx_pb12 &fdcan2_tx_pb13>;
227	pinctrl-names = "default";
228	status = "okay";
229};
230
231&mac {
232	status = "okay";
233	pinctrl-0 = <&eth_rxd0_pc4
234		     &eth_rxd1_pc5
235		     &eth_ref_clk_pa1
236		     &eth_crs_dv_pa7
237		     &eth_tx_en_pg11
238		     &eth_txd0_pg13
239		     &eth_txd1_pg14>;
240	pinctrl-names = "default";
241};
242
243&mdio {
244	status = "okay";
245	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
246	pinctrl-names = "default";
247
248	ethernet-phy@0 {
249		compatible = "microchip,ksz8081";
250		reg = <0x00>;
251		status = "okay";
252		microchip,interface-type = "rmii-25MHz";
253	};
254};
255
256&spi1 {
257	status = "okay";
258	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>;
259	pinctrl-names = "default";
260	cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
261};
262
263&fmc {
264	pinctrl-0 = <&fmc_nbl0_pe0
265		&fmc_nbl1_pe1 &fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke0_pc3_c
266		&fmc_sdne0_pc2_c &fmc_sdnras_pf11 &fmc_sdncas_pg15
267		&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
268		&fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
269		&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
270		&fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
271		&fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
272		&fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
273		&fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
274		&fmc_d15_pd10>;
275	pinctrl-names = "default";
276	status = "okay";
277
278	sdram {
279		status = "okay";
280		power-up-delay = <100>;
281		num-auto-refresh = <8>;
282		mode-register = <0x220>;
283		refresh-rate = <0x603>;
284		bank@1 {
285			reg = <1>;
286			st,sdram-control = <STM32_FMC_SDRAM_NC_8
287				STM32_FMC_SDRAM_NR_12
288				STM32_FMC_SDRAM_MWID_16
289				STM32_FMC_SDRAM_NB_4
290				STM32_FMC_SDRAM_CAS_3
291				STM32_FMC_SDRAM_SDCLK_PERIOD_2
292				STM32_FMC_SDRAM_RBURST_ENABLE
293				STM32_FMC_SDRAM_RPIPE_0>;
294			st,sdram-timing = <2 7 4 7 2 2 2>;
295		};
296	};
297};
298
299&ltdc {
300		pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
301		&ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
302		&ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
303		&ltdc_g4_pj11 &ltdc_g5_pk0 &ltdc_g6_pk1 &ltdc_g7_pk2
304		&ltdc_b0_pj12 &ltdc_b1_pj13 &ltdc_b2_pj14 &ltdc_b3_pj15
305		&ltdc_b4_pk3 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
306		&ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi10 &ltdc_vsync_pi9>;
307	pinctrl-names = "default";
308
309	disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>;
310
311	ext-sdram = <&sdram1>;
312	status = "okay";
313
314	clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>,
315		<&rcc STM32_SRC_PLL3_R NO_SEL>;
316
317	width = <480>;
318	height = <272>;
319	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
320	display-timings {
321		compatible = "zephyr,panel-timing";
322		de-active = <1>;
323		pixelclk-active = <0>;
324		hsync-active = <0>;
325		vsync-active = <0>;
326		hsync-len = <1>;
327		vsync-len = <10>;
328		hback-porch = <43>;
329		vback-porch = <12>;
330		hfront-porch = <8>;
331		vfront-porch = <4>;
332	};
333	def-back-color-red = <0xFF>;
334	def-back-color-green = <0xFF>;
335	def-back-color-blue = <0xFF>;
336};
337
338&sdmmc1 {
339	pinctrl-0 = <&sdmmc1_d0_pc8
340		     &sdmmc1_d1_pc9
341		     &sdmmc1_d2_pc10
342		     &sdmmc1_d3_pc11
343		     &sdmmc1_ck_pc12
344		     &sdmmc1_cmd_pd2>;
345	pinctrl-names = "default";
346	cd-gpios = <&gpiog 7 GPIO_ACTIVE_LOW>;
347	status = "okay";
348
349	disk {
350		status = "okay";
351	};
352};
353
354&flash0 {
355	partitions {
356		compatible = "fixed-partitions";
357		#address-cells = <1>;
358		#size-cells = <1>;
359
360		/* 128KB for bootloader */
361		boot_partition: partition@0 {
362			label = "mcuboot";
363			reg = <0x00000000 DT_SIZE_K(128)>;
364			read-only;
365		};
366
367		/* storage: 128KB for settings */
368		storage_partition: partition@20000 {
369			label = "storage";
370			reg = <0x00020000 DT_SIZE_K(128)>;
371		};
372
373		/* application image slot: 256KB */
374		slot0_partition: partition@40000 {
375			label = "image-0";
376			reg = <0x00040000 DT_SIZE_K(256)>;
377		};
378
379		/* backup slot: 256KB */
380		slot1_partition: partition@80000 {
381			label = "image-1";
382			reg = <0x00080000 DT_SIZE_K(256)>;
383		};
384
385		/* swap slot: 128KB */
386		scratch_partition: partition@c0000 {
387			label = "image-scratch";
388			reg = <0x000c0000 DT_SIZE_K(128)>;
389		};
390
391	};
392};
393