1/*
2 * Copyright (c) 2024 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <nordic/nrf9280_cpuapp.dtsi>
10#include "nrf9280pdk_nrf9280-memory_map.dtsi"
11#include "nrf9280pdk_nrf9280-ipc_conf.dtsi"
12#include "nrf9280pdk_nrf9280-pinctrl.dtsi"
13
14/delete-node/ &cpurad_cpusys_ipc;
15/delete-node/ &cpusec_cpurad_ipc;
16
17/ {
18	compatible = "nordic,nrf9280pdk_nrf9280-cpuapp";
19	model = "Nordic nRF9280 DK nRF9280 Application MCU";
20
21	chosen {
22		zephyr,console = &uart136;
23		zephyr,code-partition = &cpuapp_slot0_partition;
24		zephyr,flash = &mram1x;
25		zephyr,sram = &cpuapp_data;
26		zephyr,shell-uart = &uart136;
27		zephyr,ieee802154 = &cpuapp_ieee802154;
28		zephyr,bt-hci = &bt_hci_ipc0;
29		nordic,802154-spinel-ipc = &ipc0;
30		zephyr,canbus = &can120;
31	};
32
33	aliases {
34		led0 = &led0;
35		led1 = &led1;
36		led2 = &led2;
37		led3 = &led3;
38		resetinfo = &cpuapp_resetinfo;
39		pwm-led0 = &pwm_led0;
40		sw0 = &button0;
41		sw1 = &button1;
42		sw2 = &button2;
43		sw3 = &button3;
44		ipc-to-cpusys = &cpuapp_cpusys_ipc;
45		watchdog0 = &wdt010;
46	};
47
48	buttons {
49		compatible = "gpio-keys";
50
51		button0: button_0 {
52			gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
53			label = "Push button 0";
54			zephyr,code = <INPUT_KEY_0>;
55		};
56
57		button1: button_1 {
58			gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
59			label = "Push button 1";
60			zephyr,code = <INPUT_KEY_1>;
61		};
62
63		button2: button_2 {
64			gpios = <&gpio0 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
65			label = "Push button 2";
66			zephyr,code = <INPUT_KEY_2>;
67		};
68
69		button3: button_3 {
70			gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
71			label = "Push button 3";
72			zephyr,code = <INPUT_KEY_3>;
73		};
74	};
75
76	leds {
77		compatible = "gpio-leds";
78
79		led0: led_0 {
80			gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
81			label = "Green LED 0";
82		};
83
84		led1: led_1 {
85			gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
86			label = "Green LED 1";
87		};
88
89		led2: led_2 {
90			gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
91			label = "Green LED 2";
92		};
93
94		led3: led_3 {
95			gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
96			label = "Green LED 3";
97		};
98	};
99
100	pwmleds {
101		compatible = "pwm-leds";
102		/*
103		 * LEDs are connected to GPIO Port 9 - pins 2-5. There is no valid hardware
104		 * configuration to pass PWM signal on pins 0 and 1. First valid config is P9.2.
105		 * Signal on PWM130's channel 0 can be passed directly on GPIO Port 9 pin 2.
106		 */
107		pwm_led0: pwm_led_0 {
108			pwms = <&pwm130 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
109		};
110	};
111};
112
113&cpuapp_ram0x_region {
114	status = "okay";
115};
116
117&cpuapp_cpucell_ram0x_region {
118	status = "okay";
119};
120
121&ram21_region {
122	status = "okay";
123};
124
125&cpuapp_bellboard {
126	status = "okay";
127	interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>;
128	interrupt-names = "irq0";
129	/* The following bells on this bellboard are rang by these cores
130	 *  - Bell 0: cpusec
131	 *  - Bell 6: cpusys
132	 *  - Bell 13: cpuppr
133	 *  - Bell 18: cpurad
134	 *  - Bells 24, 25, 29, 31: cpucell
135	 */
136	nordic,interrupt-mapping = <0xA3042041 0>;
137};
138
139&cpurad_bellboard {
140	status = "okay";
141};
142
143&cpucell_bellboard {
144	status = "okay";
145};
146
147&cpusys_vevif {
148	status = "okay";
149};
150
151&cpusec_cpuapp_ipc {
152	mbox-names = "tx", "rx";
153	tx-region = <&cpuapp_cpusec_ipc_shm>;
154	rx-region = <&cpusec_cpuapp_ipc_shm>;
155};
156
157ipc0: &cpuapp_cpurad_ipc {
158	status = "okay";
159	mbox-names = "rx", "tx";
160	tx-region = <&cpuapp_cpurad_ipc_shm>;
161	rx-region = <&cpurad_cpuapp_ipc_shm>;
162	tx-blocks = <32>;
163	rx-blocks = <32>;
164
165	bt_hci_ipc0: bt_hci_ipc0 {
166		compatible = "zephyr,bt-hci-ipc";
167		status = "okay";
168	};
169};
170
171&cpuapp_cpusys_ipc {
172	status = "okay";
173	mbox-names = "rx", "tx";
174	tx-region = <&cpuapp_cpusys_ipc_shm>;
175	rx-region = <&cpusys_cpuapp_ipc_shm>;
176};
177
178&cpuapp_cpuppr_ipc {
179	mbox-names = "rx", "tx";
180	tx-region = <&cpuapp_cpuppr_ipc_shm>;
181	rx-region = <&cpuppr_cpuapp_ipc_shm>;
182};
183
184&cpuapp_dma_region {
185	status = "okay";
186};
187
188&cpuapp_rx_partitions {
189	status = "okay";
190};
191
192&cpuapp_rw_partitions {
193	status = "okay";
194};
195
196&cpuppr_vpr {
197	execution-memory = <&cpuppr_code_data>;
198	source-memory = <&cpuppr_code_partition>;
199};
200
201&gpiote130 {
202	status = "okay";
203	owned-channels = <0 1 2 3 4 5 6 7>;
204};
205
206&gpio0 {
207	status = "okay";
208};
209
210&gpio2 {
211	status = "okay";
212};
213
214&gpio9 {
215	status = "okay";
216};
217
218&grtc {
219	status = "okay";
220	child-owned-channels = <5 6>;
221	nonsecure-channels = <5 6>;
222	owned-channels = <4 5 6>;
223};
224
225&uart135 {
226	current-speed = <115200>;
227	pinctrl-0 = <&uart135_default>;
228	pinctrl-1 = <&uart135_sleep>;
229	pinctrl-names = "default", "sleep";
230};
231
232&uart136 {
233	status = "okay";
234	memory-regions = <&cpuapp_dma_region>;
235	current-speed = <115200>;
236	pinctrl-0 = <&uart136_default>;
237	pinctrl-1 = <&uart136_sleep>;
238	pinctrl-names = "default", "sleep";
239};
240
241&gpio6 {
242	status = "okay";
243};
244
245&exmif {
246	cs-gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
247	pinctrl-0 = <&exmif_default>;
248	pinctrl-names = "default";
249	status = "okay";
250	mx25uw63: mx25uw6345g@0 {
251		compatible = "jedec,spi-nor";
252		status = "disabled";
253		reg = <0>;
254		spi-max-frequency = <DT_FREQ_M(48)>;
255		jedec-id = [c2 84 37];
256		sfdp-bfp = [
257			e5 20 8a ff  ff ff ff 03  00 ff 00 ff  00 ff 00 ff
258			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 10 d8
259			00 ff 00 ff  87 79 01 00  84 12 00 c4  cc 04 67 46
260			30 b0 30 b0  f4 bd d5 5c  00 00 00 ff  10 10 00 20
261			00 00 00 00  00 00 7c 23  48 00 00 00  00 00 88 88
262		];
263		size = <67108864>;
264		has-dpd;
265		t-enter-dpd = <10000>;
266		t-exit-dpd = <30000>;
267	};
268};
269
270&cpuapp_ieee802154 {
271	status = "okay";
272};
273
274zephyr_udc0: &usbhs {
275	status = "okay";
276};
277
278&canpll {
279	status = "okay";
280};
281
282&can120 {
283	status = "okay";
284	pinctrl-0 = <&can120_default>;
285	pinctrl-names = "default";
286};
287
288&pwm130 {
289	status = "okay";
290	pinctrl-0 = <&pwm130_default>;
291	pinctrl-1 = <&pwm130_sleep>;
292	pinctrl-names = "default", "sleep";
293	memory-regions = <&cpuapp_dma_region>;
294};
295
296&adc {
297	memory-regions = <&cpuapp_dma_region>;
298	status = "okay";
299};
300