| /Zephyr-latest/dts/bindings/reset/ |
| D | st,stm32-rcc-rctl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 To specify the reset line in a peripheral, the standard resets property needs
10 to be used, e.g.:
14 /* Cell contains information about RCU register offset and bit */
20 include/zephyr/dts-bindings/reset/stm32{soc_family}_reset.h header files.
22 compatible: "st,stm32-rcc-rctl"
24 include: [reset-controller.yaml, base.yaml]
27 "#reset-cells":
30 set-bit-to-deassert:
33 Indicates if the driver should set bit in clear register to
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| /Zephyr-latest/dts/bindings/spi/ |
| D | nxp,lpspi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: ["spi-controller.yaml", "pinctrl-device.yaml"]
17 pcs-sck-delay:
20 Delay in nanoseconds from the chip select assert to the first clock
21 edge. If not set, the minimum supported delay is used.
23 sck-pcs-delay:
26 Delay in nanoseconds from the last clock edge to the chip select
27 deassert. If not set, the minimum supported delay is used.
29 transfer-delay:
32 Delay in nanoseconds from the chip select deassert to the next chip
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| D | nxp,dspi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: ["spi-controller.yaml", "pinctrl-device.yaml"]
20 pcs-sck-delay:
23 Delay in nanoseconds from the chip select assert to the first clock
24 edge. If not set, the minimum supported delay is used.
26 sck-pcs-delay:
29 Delay in nanoseconds from the last clock edge to the chip select
30 deassert. If not set, the minimum supported delay is used.
32 transfer-delay:
35 Delay in nanoseconds from the chip select deassert to the next chip
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| /Zephyr-latest/boards/renesas/rcar_salvator_x/support/ |
| D | openocd.cfg | 1 # Renesas R-Car Gen3 H3 Salvator-X Cortex-R7 Board Config
3 source [find interface/ftdi/olimex-arm-usb-ocd-h.cfg]
5 set _CHIPNAME r8a77951
6 set DAP_TAPID 0x5ba00477
7 set CA57_0_DBGBASE 0x80410000
8 set CA57_0_CTIBASE 0x80420000
9 set CR7_DBGBASE 0x80910000
10 set CR7_CTIBASE 0x80918000
17 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $DAP_TAPID
18 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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| /Zephyr-latest/dts/bindings/serial/ |
| D | st,stm32-uart-base.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
8 - name: uart-controller.yaml
9 property-blocklist:
10 - clock-frequency
11 - name: pinctrl-device.yaml
12 - name: reset-device.yaml
13 - name: uart-controller-pin-inversion.yaml
28 single-wire:
31 Enable the single wire half-duplex communication.
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_opentitan.c | 4 * SPDX-License-Identifier: Apache-2.0
35 const struct wdt_ot_aontimer_cfg *const cfg = dev->config; in ot_aontimer_setup()
36 volatile uintptr_t regs = cfg->regs; in ot_aontimer_setup()
40 if (cfg->wdog_lock) { in ot_aontimer_setup()
41 /* Force a read to ensure the timer was enabled. */ in ot_aontimer_setup()
50 const struct wdt_ot_aontimer_cfg *const cfg = dev->config; in ot_aontimer_disable()
51 volatile uintptr_t regs = cfg->regs; in ot_aontimer_disable()
54 LOG_ERR("Cannot disable - watchdog settings locked."); in ot_aontimer_disable()
55 return -EPERM; in ot_aontimer_disable()
60 if (!(ctrl_val & BIT(0))) { in ot_aontimer_disable()
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| /Zephyr-latest/drivers/sdhc/ |
| D | rcar_mmc_registers.h | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/sys/util_macro.h> /* for BIT macro */
12 * The command type register is used to select the command type
16 #define RCAR_MMC_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
17 #define RCAR_MMC_CMD_MULTI BIT(13) /* multiple block transfer */
18 #define RCAR_MMC_CMD_RD BIT(12) /* 1: read, 0: write */
19 #define RCAR_MMC_CMD_DATA BIT(11) /* data transfer */
20 #define RCAR_MMC_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
21 #define RCAR_MMC_CMD_NORMAL (0 << 8) /* auto-detect of resp-type */
32 * The data stop register is used to enable or disable block counting at
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_aw9523b.c | 4 * SPDX-License-Identifier: Apache-2.0
20 #define AW9523B_GPOMD BIT(4)
61 const struct gpio_aw9523b_config *const config = dev->config; in gpio_aw9523b_pin_configure()
63 const uint8_t mask = BIT(pin % 8); in gpio_aw9523b_pin_configure()
70 return -EWOULDBLOCK; in gpio_aw9523b_pin_configure()
73 /* Either INPUT or OUTPUT must be set */ in gpio_aw9523b_pin_configure()
76 return -ENOTSUP; in gpio_aw9523b_pin_configure()
79 /* Open-drain support is per port, not per pin. in gpio_aw9523b_pin_configure()
80 * So can't really support the API as-is. in gpio_aw9523b_pin_configure()
82 if (port == 0 && !config->port0_push_pull) { in gpio_aw9523b_pin_configure()
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_tca954x.c | 4 * SPDX-License-Identifier: Apache-2.0
37 const struct tca954x_channel_config *channel_config = dev->config; in get_root_data_from_channel()
39 return channel_config->root->data; in get_root_data_from_channel()
45 const struct tca954x_channel_config *channel_config = dev->config; in get_root_config_from_channel()
47 return channel_config->root->config; in get_root_config_from_channel()
55 return i2c_configure(cfg->i2c.bus, dev_config); in tca954x_configure()
61 struct tca954x_root_data *data = dev->data; in tca954x_set_channel()
62 const struct tca954x_root_config *cfg = dev->config; in tca954x_set_channel()
65 if (data->selected_chan != select_mask) { in tca954x_set_channel()
66 res = i2c_write_dt(&cfg->i2c, &select_mask, 1); in tca954x_set_channel()
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| /Zephyr-latest/drivers/usb/bc12/ |
| D | emul_bc12_pi3usb9201.c | 4 * SPDX-License-Identifier: Apache-2.0
6 * Emulator for Diodes PI3USB9201 Dual-Role USB Charging-Type Detector.
31 #define DCP_DETECTED BIT(7)
32 #define SDP_DETECTED BIT(6)
33 #define CDP_DETECTED BIT(5)
34 #define PROPRIETARY_1A_DETECTED BIT(3)
35 #define PROPRIETARY_2A_DETECTED BIT(2)
36 #define PROPRIETARY_2_4A_DETECTED BIT(1)
38 /** Run-time data used by the emulator */
52 /** Pointer to run-time data */
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| /Zephyr-latest/drivers/can/ |
| D | can_tcan4x5x.c | 4 * SPDX-License-Identifier: Apache-2.0
21 * The register definitions correspond to those found in the TI TCAN4550-Q1 datasheet, revision D
39 #define CAN_TCAN4X5X_STATUS_INTERNAL_READ_ERROR BIT(29)
40 #define CAN_TCAN4X5X_STATUS_INTERNAL_WRITE_ERROR BIT(28)
41 #define CAN_TCAN4X5X_STATUS_INTERNAL_ERROR_LOG_WRITE BIT(27)
42 #define CAN_TCAN4X5X_STATUS_READ_FIFO_UNDERFLOW BIT(26)
43 #define CAN_TCAN4X5X_STATUS_READ_FIFO_EMPTY BIT(25)
44 #define CAN_TCAN4X5X_STATUS_WRITE_FIFO_OVERFLOW BIT(24)
45 #define CAN_TCAN4X5X_STATUS_SPI_END_ERROR BIT(21)
46 #define CAN_TCAN4X5X_STATUS_INVALID_COMMAND BIT(20)
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| /Zephyr-latest/drivers/spi/ |
| D | spi_opentitan.c | 4 * SPDX-License-Identifier: Apache-2.0
35 #define SPI_HOST_CONTROL_OUTPUT_EN_BIT BIT(29)
36 #define SPI_HOST_CONTROL_SW_RST_BIT BIT(30)
37 #define SPI_HOST_CONTROL_SPIEN_BIT BIT(31)
42 #define SPI_HOST_STATUS_BYTEORDER_BIT BIT(22)
43 #define SPI_HOST_STATUS_RXEMPTY_BIT BIT(24)
44 #define SPI_HOST_STATUS_ACTIVE_BIT BIT(30)
45 #define SPI_HOST_STATUS_READY_BIT BIT(31)
50 #define SPI_HOST_COMMAND_CSAAT_BIT BIT(9)
61 #define SPI_HOST_CONFIGOPTS_CPHA0_BIT BIT(30)
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| D | spi_mcux_flexcomm.c | 5 * SPDX-License-Identifier: Apache-2.0
72 /* Used to send the last word */
79 const struct spi_mcux_config *config = dev->config; in spi_mcux_transfer_next_packet()
80 struct spi_mcux_data *data = dev->data; in spi_mcux_transfer_next_packet()
81 SPI_Type *base = config->base; in spi_mcux_transfer_next_packet()
82 struct spi_context *ctx = &data->ctx; in spi_mcux_transfer_next_packet()
86 if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) { in spi_mcux_transfer_next_packet()
87 /* nothing left to rx or tx, we're done! */ in spi_mcux_transfer_next_packet()
88 spi_context_cs_control(&data->ctx, false); in spi_mcux_transfer_next_packet()
89 spi_context_complete(&data->ctx, dev, 0); in spi_mcux_transfer_next_packet()
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| /Zephyr-latest/soc/nxp/imxrt/imxrt11xx/ |
| D | soc.c | 2 * Copyright 2021-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/linker/linker-defs.h>
25 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
28 /* Memcpy macro to copy segments from secondary core image stored in flash
29 * to RAM section that secondary core boots from.
33 memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_##n) - ADJUSTED_LMA), \
69 * Check that the ARM PLL has a multiplier and divider set
72 "ARM PLL must have clock-mult property");
74 "ARM PLL must have clock-div property");
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| /Zephyr-latest/drivers/sensor/tdk/icm42688/ |
| D | icm42688_trigger.c | 4 * SPDX-License-Identifier: Apache-2.0
30 k_sem_give(&data->gpio_sem); in icm42688_gpio_callback()
32 k_work_submit(&data->work); in icm42688_gpio_callback()
35 icm42688_fifo_event(data->dev); in icm42688_gpio_callback()
42 struct icm42688_dev_data *data = dev->data; in icm42688_thread_cb()
46 if (data->data_ready_handler != NULL) { in icm42688_thread_cb()
47 data->data_ready_handler(dev, data->data_ready_trigger); in icm42688_thread_cb()
64 k_sem_take(&data->gpio_sem, K_FOREVER); in icm42688_thread()
65 icm42688_thread_cb(data->dev); in icm42688_thread()
75 icm42688_thread_cb(data->dev); in icm42688_work_handler()
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| /Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/ |
| D | soc.c | 2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
172 * some microseconds to make sure utmi clock valid in usb_device_clock_init()
176 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
177 while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { in usb_device_clock_init()
180 /* According to reference mannual, device mode setting has to be set by access in usb_device_clock_init()
183 USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; in usb_device_clock_init()
196 * set the stack pointer, since we are about to push to in soc_reset_hook()
203 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in soc_reset_hook()
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| /Zephyr-latest/drivers/flash/ |
| D | spi_nor.c | 2 * Copyright (c) 2018 Savoir-Faire Linux.
8 * SPDX-License-Identifier: Apache-2.0
36 * * Some devices support a Deep Power-Down mode which reduces current
37 * to as little as 0.1% of standby.
39 * When mapped to the Zephyr Device Power Management states:
41 * * PM_DEVICE_STATE_SUSPENDED corresponds to deep-power-down mode;
63 #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config)
66 /* MXICY Low-power/high perf mode is second bit in configuration register 2 */
72 /* Build-time data associated with the device. */
92 /* Expected JEDEC ID, from jedec-id property */
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_lan865x.c | 4 * SPDX-License-Identifier: Apache-2.0
26 struct lan865x_data *ctx = dev->data; in lan865x_mac_rxtx_control()
33 return oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_NCR, ctl); in lan865x_mac_rxtx_control()
39 struct lan865x_data *ctx = dev->data; in lan865x_iface_init()
41 net_if_set_link_addr(iface, ctx->mac_address, sizeof(ctx->mac_address), in lan865x_iface_init()
44 if (ctx->iface == NULL) { in lan865x_iface_init()
45 ctx->iface = iface; in lan865x_iface_init()
51 ctx->iface_initialized = true; in lan865x_iface_init()
65 const struct lan865x_config *cfg = dev->config; in lan865x_set_config()
66 struct lan865x_data *ctx = dev->data; in lan865x_set_config()
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| D | eth_adin2111.c | 4 * SPDX-License-Identifier: Apache-2.0
55 /* As per RM rev. A table 3, t3 >= 50ms, delay for SPI interface to be ready */
57 /* As per RM rev. A page 20: approximately 10 ms (maximum) for internal logic to be ready. */
86 return -EBUSY; in eth_adin2111_mac_reset()
111 struct adin2111_data *ctx = dev->data; in eth_adin2111_get_iface()
113 return ((struct adin2111_port_data *)ctx->port[port_idx]->data)->iface; in eth_adin2111_get_iface()
118 struct adin2111_data *ctx = dev->data; in eth_adin2111_lock()
120 return k_mutex_lock(&ctx->lock, timeout); in eth_adin2111_lock()
125 struct adin2111_data *ctx = dev->data; in eth_adin2111_unlock()
127 return k_mutex_unlock(&ctx->lock); in eth_adin2111_unlock()
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| /Zephyr-latest/dts/arm/st/mp1/ |
| D | stm32mp157.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32_common_clocks.h>
13 #include <zephyr/dt-bindings/clock/stm32_clock.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
17 #include <zephyr/dt-bindings/dma/stm32_dma.h>
18 #include <zephyr/dt-bindings/reset/stm32mp1_reset.h>
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