4  * SPDX-License-Identifier: Apache-2.0
35 #define SPI_HOST_CONTROL_OUTPUT_EN_BIT BIT(29)
36 #define SPI_HOST_CONTROL_SW_RST_BIT BIT(30)
37 #define SPI_HOST_CONTROL_SPIEN_BIT BIT(31)
42 #define SPI_HOST_STATUS_BYTEORDER_BIT BIT(22)
43 #define SPI_HOST_STATUS_RXEMPTY_BIT BIT(24)
44 #define SPI_HOST_STATUS_ACTIVE_BIT BIT(30)
45 #define SPI_HOST_STATUS_READY_BIT BIT(31)
50 #define SPI_HOST_COMMAND_CSAAT_BIT BIT(9)
61 #define SPI_HOST_CONFIGOPTS_CPHA0_BIT BIT(30)
62 #define SPI_HOST_CONFIGOPTS_CPOL0_BIT BIT(31)
78 	const struct spi_opentitan_cfg *cfg = dev->config;  in spi_config()
83 		return -ENOTSUP;  in spi_config()
87 		return -ENOTSUP;  in spi_config()
91 		return -ENOTSUP;  in spi_config()
95 		return -ENOTSUP;  in spi_config()
100 		return -ENOTSUP;  in spi_config()
103 	/* Most significant bit always transferred first. */  in spi_config()
105 		return -ENOTSUP;  in spi_config()
108 	/* Set the SPI frequency, polarity, and clock phase in CONFIGOPTS register.  in spi_config()
109 	 * Applied divider (divides f_in / 2) is CLKDIV register (16 bit) + 1.  in spi_config()
111 	reg = cfg->f_input / 2 / frequency;  in spi_config()
115 		reg--;  in spi_config()
125 	sys_write32(reg, cfg->base + SPI_HOST_CONFIGOPTS_REG_OFFSET);  in spi_config()
132 	/* Rx bytes are available if Tx FIFO is non-empty. */  in spi_opentitan_rx_available()
133 	return !(sys_read32(cfg->base + SPI_HOST_STATUS_REG_OFFSET) & SPI_HOST_STATUS_RXEMPTY_BIT);  in spi_opentitan_rx_available()
138 	const struct spi_opentitan_cfg *cfg = dev->config;  in spi_opentitan_xfer()
139 	struct spi_opentitan_data *data = dev->data;  in spi_opentitan_xfer()
140 	struct spi_context *ctx = &data->ctx;  in spi_opentitan_xfer()
143 		const size_t segment_len = MAX(ctx->tx_len, ctx->rx_len);  in spi_opentitan_xfer()
155 		size_t tx_bytes_to_queue = spi_context_tx_buf_on(ctx) ? ctx->tx_len : 0;  in spi_opentitan_xfer()
157 		/* First place Tx bytes in FIFO, packed four to a word. */  in spi_opentitan_xfer()
165 				fifo_word |= *ctx->tx_buf << (8 * byte);  in spi_opentitan_xfer()
167 				tx_bytes_to_queue--;  in spi_opentitan_xfer()
169 			sys_write32(fifo_word, cfg->base + SPI_HOST_TXDATA_REG_OFFSET);  in spi_opentitan_xfer()
176 		if (ctx->tx_count > 0 || ctx->rx_count > 1)  {  in spi_opentitan_xfer()
180 		host_command_reg |= segment_len - 1;  in spi_opentitan_xfer()
183 		sys_write32(host_command_reg, cfg->base + SPI_HOST_COMMAND_REG_OFFSET);  in spi_opentitan_xfer()
185 		size_t rx_bytes_to_read = spi_context_rx_buf_on(ctx) ? ctx->rx_len : 0;  in spi_opentitan_xfer()
192 			uint32_t rx_word = sys_read32(cfg->base +  in spi_opentitan_xfer()
198 				*ctx->rx_buf = (rx_word >> (8 * byte)) & 0xff;  in spi_opentitan_xfer()
200 				rx_bytes_to_read--;  in spi_opentitan_xfer()
205 	/* Deassert the CS line if required. */  in spi_opentitan_xfer()
215 	const struct spi_opentitan_cfg *cfg = dev->config;  in spi_opentitan_init()
216 	struct spi_opentitan_data *data = dev->data;  in spi_opentitan_init()
219 	/* Place SPI host peripheral in reset and wait for reset to complete. */  in spi_opentitan_init()
221 		cfg->base + SPI_HOST_CONTROL_REG_OFFSET);  in spi_opentitan_init()
222 	while (sys_read32(cfg->base + SPI_HOST_STATUS_REG_OFFSET)  in spi_opentitan_init()
229 		cfg->base + SPI_HOST_CONTROL_REG_OFFSET);  in spi_opentitan_init()
231 	err = spi_context_cs_configure_all(&data->ctx);  in spi_opentitan_init()
237 	spi_context_unlock_unconditionally(&data->ctx);  in spi_opentitan_init()
248 	struct spi_opentitan_data *data = dev->data;  in spi_opentitan_transceive()
251 	spi_context_lock(&data->ctx, false, NULL, NULL, config);  in spi_opentitan_transceive()
254 	data->ctx.config = config;  in spi_opentitan_transceive()
255 	rc = spi_config(dev, config->frequency, config->operation);  in spi_opentitan_transceive()
257 		spi_context_release(&data->ctx, rc);  in spi_opentitan_transceive()
261 	spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);  in spi_opentitan_transceive()
264 	 * (default CSID: 0), so GPIO CS control will work in addition to HW  in spi_opentitan_transceive()
267 	if (config->cs) {  in spi_opentitan_transceive()
269 		spi_context_cs_control(&data->ctx, true);  in spi_opentitan_transceive()
275 	rc = spi_context_wait_for_completion(&data->ctx);  in spi_opentitan_transceive()
277 	spi_context_release(&data->ctx, rc);  in spi_opentitan_transceive()
290 	return -ENOTSUP;  in spi_opentitan_transceive_async()
297 	struct spi_opentitan_data *data = dev->data;  in spi_opentitan_release()
299 	spi_context_unlock_unconditionally(&data->ctx);  in spi_opentitan_release()