Lines Matching +full:set +full:- +full:bit +full:- +full:to +full:- +full:deassert

2 # SPDX-License-Identifier: Apache-2.0
8 include: ["spi-controller.yaml", "pinctrl-device.yaml"]
20   pcs-sck-delay:
23       Delay in nanoseconds from the chip select assert to the first clock
24       edge. If not set, the minimum supported delay is used.
26   sck-pcs-delay:
29       Delay in nanoseconds from the last clock edge to the chip select
30       deassert. If not set, the minimum supported delay is used.
32   transfer-delay:
35       Delay in nanoseconds from the chip select deassert to the next chip
36       select assert. If not set, the minimum supported delay is used.
38   pinctrl-0:
41   nxp,rx-tx-chn-share:
48       ctar register selection range form 0-1 for master mode, 0 for slave mode
50   sample-point:
54       This field is valid only when the CPHA bit in the CTAR register is 0.
56   continuous-sck:
62   rx-fifo-overwrite:
67       is also ignored. If ROOE = 1, the incoming data is shifted to the
70   modified-timing-format:
73       Enables a modified transfer format to be used if true.
75   tx-fifo-size:
80   rx-fifo-size: