Lines Matching +full:set +full:- +full:bit +full:- +full:to +full:- +full:deassert
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/sys/util_macro.h> /* for BIT macro */
12 * The command type register is used to select the command type
16 #define RCAR_MMC_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
17 #define RCAR_MMC_CMD_MULTI BIT(13) /* multiple block transfer */
18 #define RCAR_MMC_CMD_RD BIT(12) /* 1: read, 0: write */
19 #define RCAR_MMC_CMD_DATA BIT(11) /* data transfer */
20 #define RCAR_MMC_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
21 #define RCAR_MMC_CMD_NORMAL (0 << 8) /* auto-detect of resp-type */
32 * The data stop register is used to enable or disable block counting at
33 * multiple block transfer, and to control the issuing of CMD12 within
37 #define RCAR_MMC_STOP_SEC BIT(8) /* use sector count */
38 #define RCAR_MMC_STOP_STP BIT(0) /* issue CMD12 */
41 * The block count register is used to specify the number of
58 #define RCAR_MMC_INFO1_CD BIT(5) /* state of card detect */
59 #define RCAR_MMC_INFO1_INSERT BIT(4) /* card inserted */
60 #define RCAR_MMC_INFO1_REMOVE BIT(3) /* card removed */
61 #define RCAR_MMC_INFO1_CMP BIT(2) /* data complete */
62 #define RCAR_MMC_INFO1_RSP BIT(0) /* response complete */
69 #define RCAR_MMC_INFO2_ERR_ILA BIT(15) /* illegal access err */
70 #define RCAR_MMC_INFO2_CBSY BIT(14) /* command busy */
71 #define RCAR_MMC_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */
72 #define RCAR_MMC_INFO2_CLEAR BIT(11) /* the write value should always be 1 */
73 #define RCAR_MMC_INFO2_BWE BIT(9) /* write buffer ready */
74 #define RCAR_MMC_INFO2_BRE BIT(8) /* read buffer ready */
75 #define RCAR_MMC_INFO2_DAT0 BIT(7) /* SDDAT0 */
76 #define RCAR_MMC_INFO2_ERR_RTO BIT(6) /* response time out */
77 #define RCAR_MMC_INFO2_ERR_ILR BIT(5) /* illegal read err */
78 #define RCAR_MMC_INFO2_ERR_ILW BIT(4) /* illegal write err */
79 #define RCAR_MMC_INFO2_ERR_TO BIT(3) /* time out error */
80 #define RCAR_MMC_INFO2_ERR_END BIT(2) /* END bit error */
81 #define RCAR_MMC_INFO2_ERR_CRC BIT(1) /* CRC error */
82 #define RCAR_MMC_INFO2_ERR_IDX BIT(0) /* cmd index error */
91 * The interrupt mask 1 register is used to enable or disable
97 * The interrupt mask 2 register is used to enable or disable
103 * The SD clock control register is used to control
104 * the SD clock output and to set the frequency.
108 #define RCAR_MMC_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
109 #define RCAR_MMC_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
110 #define RCAR_MMC_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
111 #define RCAR_MMC_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
112 #define RCAR_MMC_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
113 #define RCAR_MMC_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
114 #define RCAR_MMC_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
115 #define RCAR_MMC_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
118 #define RCAR_MMC_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
119 #define RCAR_MMC_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
122 * The transfer data length register is used to specify
128 * The SD card access control option register is used to set
151 #define RCAR_MMC_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
155 #define RCAR_MMC_SOFT_RST_RSTX BIT(0) /* reset deassert */
162 * The host interface mode setting register selects the width for access to
169 #define RCAR_MMC_IF_MODE_DDR BIT(0) /* DDR mode */
171 /* Set of DMAC registers */
173 #define RCAR_MMC_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
174 #define RCAR_MMC_DMA_MODE_WIDTH (BIT(4) | BIT(5))
175 #define RCAR_MMC_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
177 #define RCAR_MMC_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
179 #define RCAR_MMC_DMA_RST_DTRAN0 BIT(8)
180 #define RCAR_MMC_DMA_RST_DTRAN1 BIT(9)
182 #define RCAR_MMC_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */
183 #define RCAR_MMC_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */
184 #define RCAR_MMC_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
187 #define RCAR_MMC_DMA_INFO2_ERR_RD BIT(17)
188 #define RCAR_MMC_DMA_INFO2_ERR_WR BIT(16)
193 /* set of SCC registers */
197 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
203 #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
206 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
209 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
210 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
213 #define RENESAS_SDHI_SCC_RVSREQ_ERR BIT(2)
218 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
219 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)