2  * Copyright 2021-2024 NXP
4  * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/linker/linker-defs.h>
25 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
28 /* Memcpy macro to copy segments from secondary core image stored in flash
29  * to RAM section that secondary core boots from.
33 	memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_##n) - ADJUSTED_LMA),                             \
69  * Check that the ARM PLL has a multiplier and divider set
72 	     "ARM PLL must have clock-mult property");
74 	     "ARM PLL must have clock-div property");
106 	 * 30 bit numerator of fractional loop divider,
111 	 * 30 bit denominator of fractional loop divider,
173 	/* Check if FBB need to be enabled in OverDrive(OD) mode */  in clock_init()
174 	if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) {  in clock_init()
190 	if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &  in clock_init()
196 	if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &  in clock_init()
210 	ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;  in clock_init()
221 	ANADIG_OSC->OSC_24M_CTRL |=  in clock_init()
226 	/* Wait for 24M OSC to be stable. */  in clock_init()
228 	       (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) {  in clock_init()
234 	/* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */  in clock_init()
418 	/* Set ENET_REF_CLK as an input driven by PHY */  in clock_init()
419 	IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U);  in clock_init()
420 	IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U);  in clock_init()
422 	/* Set ENET_REF_CLK as an output driven by ENET1_CLK_ROOT */  in clock_init()
423 	IOMUXC_GPR->GPR4 |=  in clock_init()
433 	/* Set ENET1G TX_CLK to be driven by ENET2_CLK_ROOT and output on TX_CLK_IO pad */  in clock_init()
434 	IOMUXC_GPR->GPR5 = (IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(0x01U) |  in clock_init()
435 			    (IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x01U)));  in clock_init()
436 	/* Set ENET1G_REF_CLK as an input driven by PHY */  in clock_init()
437 	IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U);  in clock_init()
440 	 * 50 MHz clock for 10/100Mbit RMII PHY -  in clock_init()
446 	/* Set ENET1G_REF_CLK as an input driven by PHY */  in clock_init()
447 	IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U);  in clock_init()
448 	IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U);  in clock_init()
450 	/* Set ENET1G_REF_CLK as an output driven by ENET2_CLK_ROOT */  in clock_init()
451 	IOMUXC_GPR->GPR5 |= (IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U) |  in clock_init()
473 	/* MIPI CSI-2 Rx connects to CSI via Video Mux */  in clock_init()
475 	VIDEO_MUX->VID_MUX_CTRL.SET = VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK;  in clock_init()
477 	/* Enable power domain for MIPI CSI-2 */  in clock_init()
478 	PGMC_BPC4->BPC_POWER_CTRL |= (PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK |  in clock_init()
509 	 * PLL2 is fixed at 528MHz. Use desired panel clock clock to  in clock_init()
571 	CCM->GPR_PRIVATE1_SET = 0x1;  in clock_init()
581 	/* Enable the AHB clock while the CM7 is sleeping to allow debug access  in clock_init()
582 	 * to TCM  in clock_init()
584 	IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK;  in clock_init()
620 	/* elcdif output to MIPI DSI */  in imxrt_pre_init_display_interface()
622 	VIDEO_MUX->VID_MUX_CTRL.CLR = VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK;  in imxrt_pre_init_display_interface()
625 	PGMC_BPC4->BPC_POWER_CTRL |= (PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK |  in imxrt_pre_init_display_interface()
629 	IOMUXC_GPR->GPR62 &= ~(IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK |  in imxrt_pre_init_display_interface()
660 	/* Deassert PCLK and ESC reset. */  in imxrt_pre_init_display_interface()
661 	IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK |  in imxrt_pre_init_display_interface()
667 	/* deassert BYTE and DBI reset */  in imxrt_post_init_display_interface()
668 	IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK |  in imxrt_post_init_display_interface()
692 		return -EINVAL;  in mipi_csi2rx_clock_set_freq()
699 		return -EINVAL;  in mipi_csi2rx_clock_set_freq()
715  * If dual core operation is enabled, the second core image will be loaded to RAM
724 	 * Copy CM4 core from flash to memory. Note that depending on where the  in imxrt_init()
725 	 * user decided to store CM4 code, this is likely going to read from the  in imxrt_init()
726 	 * flexspi while using XIP. Provided we DO NOT WRITE TO THE FLEXSPI,  in imxrt_init()
729 	 * Note that this copy MUST occur before enabling the M7 caching to  in imxrt_init()
730 	 * ensure the data is written directly to RAM (since the M4 core will use it)  in imxrt_init()
733 	/* Set the boot address for the second core */  in imxrt_init()
735 	/* Set VTOR for the CM4 core */  in imxrt_init()
736 	IOMUXC_LPSR_GPR->GPR0 = IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(boot_address >> 3u);  in imxrt_init()
737 	IOMUXC_LPSR_GPR->GPR1 = IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(boot_address >> 16u);  in imxrt_init()
741 	/* Set boot flag in messaging unit to indicate boot to primary core */  in imxrt_init()
757  * Stack pointer is not set at this point in the early init, but we call C
759  * Set a stack pointer so that C functions will work correctly
788  * Kick the secondary core out of reset and wait for it to indicate boot. The
789  * core image was already copied to RAM (and the boot address was set) in
797 	SRC->CTRL_M4CORE = SRC_CTRL_M4CORE_SW_RESET_MASK;  in second_core_boot()
798 	SRC->SCR |= SRC_SCR_BT_RELEASE_M4_MASK;  in second_core_boot()
800 	/* Wait for the secondary core to start up and set boot flag in  in second_core_boot()
804 		/* Wait for secondary core to set flag */  in second_core_boot()