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/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,mcux-rt11xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "high";
16 slew-rate = "slow";
25 drive-open-drain: ODE/ODE_LPSR=1
26 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
27 bias-pull-down: PUE=1, PUS=0
28 bias-pull-up: PUE=1, PUS=1
29 bias-disable: PULL=11 (in supported registers)
30 slew-rate: SRE=<enum_idx>
31 drive-strength: DSE=<enum_idx>
[all …]
Dnxp,imx8mp-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 bias-pull-up;
16 slew-rate = "slow";
17 drive-strength = "x1";
26 input-schmitt-enable: HYS=1
27 bias-pull-up: PUE=1, PE=1
28 bias-pull-down: PUE=0, PE=1
29 drive-open-drain: ODE=1
30 slew-rate: FSEL=<enum_idx>
31 drive-strength: DSE=<enum_idx>
[all …]
Dnxp,mcux-rt-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "100-mhz";
21 Both pins will be configured with a weak latch, drive strength of "r0-6",
26 input-schmitt-enable: HYS=1
27 drive-open-drain: ODE=1
28 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
29 bias-pull-down: PUE=1, PUS=<bias-pull-down-value>
30 bias-pull-up: PUE=1, PUS=<bias-pull-up-value>
[all …]
Dnxp,imx8m-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "40-ohm";
16 slew-rate = "slow";
26 input-schmitt-enable: HYS=1
27 bias-pull-up: PUE=1
28 drive-open-drain: ODE=1
29 slew-rate: SRE=<enum_idx>
30 drive-strength: DSE=<enum_idx>
31 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
33 If only required properties are supplied, the pin will have the following
[all …]
Dnxp,imx-iomuxc.yaml2 # SPDX-License-Identifier: Apache-2.0
7 These options can then be used in a pinctrl node with the "nxp,mcux-rt-pinctrl"
8 compatible string to define pin groups.
13 compatible: "nxp,imx-iomuxc"
16 - name: base.yaml
22 child-binding:
23 description: MCUX RT pin mux option
29 An array of values defining the pin mux selection, in the following format:
33 input_reg: peripheral register that will direct peripheral signal to pin
35 cfg_reg: register that will configure pin pull, drive strength, and open drain
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/Zephyr-latest/drivers/gpio/
Dgpio_sifive.c2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
26 /* sifive GPIO register-set structure */
32 unsigned int pue; member
51 /* multi-level encoded interrupt corresponding to pin 0 */
65 ((const struct gpio_sifive_config * const)(dev)->config)
67 ((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
69 ((struct gpio_sifive_data *)(dev)->data)
72 /* Given gpio_irq_base and the pin number, return the IRQ number for the pin */
73 static inline unsigned int gpio_sifive_pin_irq(unsigned int base_irq, int pin) in gpio_sifive_pin_irq() argument
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Dgpio_mcux_rgpio.c2 * Copyright 2023-2024, NXP
4 * SPDX-License-Identifier: Apache-2.0
21 ((const struct mcux_rgpio_config *)(_dev)->config)
22 #define DEV_DATA(_dev) ((struct mcux_rgpio_data *)(_dev)->data)
45 gpio_pin_t pin, gpio_flags_t flags) in mcux_rgpio_configure() argument
48 const struct mcux_rgpio_config *config = dev->config; in mcux_rgpio_configure()
51 int cfg_idx = pin, i; in mcux_rgpio_configure()
53 /* Make sure pin is supported */ in mcux_rgpio_configure()
54 if ((config->common.port_pin_mask & BIT(pin)) == 0) { in mcux_rgpio_configure()
55 return -ENOTSUP; in mcux_rgpio_configure()
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Dgpio_mcux_igpio.c4 * SPDX-License-Identifier: Apache-2.0
23 #define DEV_CFG(_dev) ((const struct mcux_igpio_config *)(_dev)->config)
24 #define DEV_DATA(_dev) ((struct mcux_igpio_data *)(_dev)->data)
52 gpio_pin_t pin, gpio_flags_t flags) in mcux_igpio_configure() argument
54 const struct mcux_igpio_config *config = dev->config; in mcux_igpio_configure()
58 int cfg_idx = pin, i; in mcux_igpio_configure()
60 /* Make sure pin is supported */ in mcux_igpio_configure()
61 if ((config->common.port_pin_mask & BIT(pin)) == 0) { in mcux_igpio_configure()
62 return -ENOTSUP; in mcux_igpio_configure()
65 /* Some SOCs have non-contiguous gpio pin layouts, account for this */ in mcux_igpio_configure()
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/Zephyr-latest/soc/nxp/imxrt/imxrt118x/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
32 * RT11xx has multiple types of register layouts defined for pin configuration
79 uint8_t pue_mux: 1; /* Is pinmux reg pue type */
/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
34 * RT11xx has multiple types of register layouts defined for pin configuration
102 uint8_t pue_mux: 1; /* Is pinmux reg pue type */