2  * Copyright 2023-2024, NXP
4  * SPDX-License-Identifier: Apache-2.0
21 	((const struct mcux_rgpio_config *)(_dev)->config)
22 #define DEV_DATA(_dev) ((struct mcux_rgpio_data *)(_dev)->data)
45 				gpio_pin_t pin, gpio_flags_t flags)  in mcux_rgpio_configure()  argument
48 	const struct mcux_rgpio_config *config = dev->config;  in mcux_rgpio_configure()
51 	int cfg_idx = pin, i;  in mcux_rgpio_configure()
53 	/* Make sure pin is supported */  in mcux_rgpio_configure()
54 	if ((config->common.port_pin_mask & BIT(pin)) == 0) {  in mcux_rgpio_configure()
55 		return -ENOTSUP;  in mcux_rgpio_configure()
58 	/* Some SOCs have non-contiguous gpio pin layouts, account for this */  in mcux_rgpio_configure()
59 	for (i = 0; i < pin; i++) {  in mcux_rgpio_configure()
60 		if ((config->common.port_pin_mask & BIT(i)) == 0) {  in mcux_rgpio_configure()
61 			cfg_idx--;  in mcux_rgpio_configure()
65 	/* Init pin configuration struct, and use pinctrl api to apply settings */  in mcux_rgpio_configure()
66 	if (cfg_idx >= config->mux_count) {  in mcux_rgpio_configure()
67 		/* Pin is not connected to a mux */  in mcux_rgpio_configure()
68 		return -ENOTSUP;  in mcux_rgpio_configure()
71 	/* Set appropriate bits in pin configuration register */  in mcux_rgpio_configure()
73 			((size_t)config->pin_muxes[cfg_idx].config_register);  in mcux_rgpio_configure()
77 	/* PUE/PDRV types have the same ODE bit */  in mcux_rgpio_configure()
85 	if (config->pin_muxes[pin].pue_mux) {  in mcux_rgpio_configure()
92 			/* Set pin to highz */  in mcux_rgpio_configure()
104 			/* Set pin to no pull */  in mcux_rgpio_configure()
126 		/* Set pin to highz */  in mcux_rgpio_configure()
132 	memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg));  in mcux_rgpio_configure()
138 		return -ENOTSUP;  in mcux_rgpio_configure()
142 		RGPIO_WritePinOutput(base, pin, 1);  in mcux_rgpio_configure()
146 		RGPIO_WritePinOutput(base, pin, 0);  in mcux_rgpio_configure()
149 	WRITE_BIT(base->PDDR, pin, flags & GPIO_OUTPUT);  in mcux_rgpio_configure()
158 	*value = base->PDIR;  in mcux_rgpio_port_get_raw()
169 	base->PDOR = (base->PDOR & ~mask) | (mask & value);  in mcux_rgpio_port_set_masked_raw()
205 						  gpio_pin_t pin,  in mcux_rgpio_pin_interrupt_configure()  argument
210 	const struct mcux_rgpio_config *config = dev->config;  in mcux_rgpio_pin_interrupt_configure()
214 	/* Make sure pin is supported */  in mcux_rgpio_pin_interrupt_configure()
215 	if ((config->common.port_pin_mask & BIT(pin)) == 0) {  in mcux_rgpio_pin_interrupt_configure()
216 		return -ENOTSUP;  in mcux_rgpio_pin_interrupt_configure()
239 		return -EINVAL; /* should never end up here */  in mcux_rgpio_pin_interrupt_configure()
243 	RGPIO_SetPinInterruptConfig(base, pin, irqs, irqc);  in mcux_rgpio_pin_interrupt_configure()
253 	struct mcux_rgpio_data *data = dev->data;  in mcux_rgpio_manage_callback()
255 	return gpio_manage_callback(&data->callbacks, callback, set);  in mcux_rgpio_manage_callback()
261 	struct mcux_rgpio_data *data = dev->data;  in mcux_rgpio_port_isr()
264 	int_flags = base->ISFR[0]; /* Notice: only irq0 is used for now */  in mcux_rgpio_port_isr()
265 	base->ISFR[0] = int_flags;  in mcux_rgpio_port_isr()
267 	gpio_fire_callbacks(&data->callbacks, dev, int_flags);  in mcux_rgpio_port_isr()