1 /*
2 * Copyright (c) 2017, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_gpio
8
9 #include <errno.h>
10 #include <zephyr/device.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/irq.h>
13 #if __has_include("soc.h")
14 #include <soc.h>
15 #endif
16 #include <fsl_common.h>
17 #include <fsl_gpio.h>
18
19 #include <zephyr/drivers/pinctrl.h>
20
21 #include <zephyr/drivers/gpio/gpio_utils.h>
22
23 #define DEV_CFG(_dev) ((const struct mcux_igpio_config *)(_dev)->config)
24 #define DEV_DATA(_dev) ((struct mcux_igpio_data *)(_dev)->data)
25
26 struct mcux_igpio_config {
27 /* gpio_driver_config needs to be first */
28 struct gpio_driver_config common;
29
30 DEVICE_MMIO_NAMED_ROM(igpio_mmio);
31
32 const struct pinctrl_soc_pinmux *pin_muxes;
33 uint8_t mux_count;
34 };
35
36 struct mcux_igpio_data {
37 /* gpio_driver_data needs to be first */
38 struct gpio_driver_data general;
39
40 DEVICE_MMIO_NAMED_RAM(igpio_mmio);
41
42 /* port ISR callback routine address */
43 sys_slist_t callbacks;
44 };
45
get_base(const struct device * dev)46 static GPIO_Type *get_base(const struct device *dev)
47 {
48 return (GPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, igpio_mmio);
49 }
50
mcux_igpio_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)51 static int mcux_igpio_configure(const struct device *dev,
52 gpio_pin_t pin, gpio_flags_t flags)
53 {
54 const struct mcux_igpio_config *config = dev->config;
55 GPIO_Type *base = get_base(dev);
56
57 struct pinctrl_soc_pin pin_cfg;
58 int cfg_idx = pin, i;
59
60 /* Make sure pin is supported */
61 if ((config->common.port_pin_mask & BIT(pin)) == 0) {
62 return -ENOTSUP;
63 }
64
65 /* Some SOCs have non-contiguous gpio pin layouts, account for this */
66 for (i = 0; i < pin; i++) {
67 if ((config->common.port_pin_mask & BIT(i)) == 0) {
68 cfg_idx--;
69 }
70 }
71
72 /* Init pin configuration struct, and use pinctrl api to apply settings */
73 if (cfg_idx >= config->mux_count) {
74 /* Pin is not connected to a mux */
75 return -ENOTSUP;
76 }
77
78 /* Set appropriate bits in pin configuration register */
79 volatile uint32_t *gpio_cfg_reg =
80 (volatile uint32_t *)(uintptr_t)config->pin_muxes[cfg_idx].config_register;
81 uint32_t reg = *gpio_cfg_reg;
82
83 #ifdef CONFIG_SOC_SERIES_IMXRT10XX
84 if ((flags & GPIO_SINGLE_ENDED) != 0) {
85 /* Set ODE bit */
86 reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
87 } else {
88 reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
89 }
90 if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
91 reg |= IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
92 if (((flags & GPIO_PULL_UP) != 0)) {
93 /* Use 100K pullup */
94 reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(2);
95 } else {
96 /* 100K pulldown */
97 reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
98 }
99 } else {
100 /* Set pin to keeper */
101 reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
102 }
103 #elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
104 if (config->pin_muxes[pin].pue_mux) {
105 /* PUE type register layout (GPIO_AD pins) */
106 if ((flags & GPIO_SINGLE_ENDED) != 0) {
107 /* Set ODE bit */
108 reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
109 } else {
110 reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
111 }
112
113 if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
114 reg |= IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
115 if (((flags & GPIO_PULL_UP) != 0)) {
116 reg |= IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
117 } else {
118 reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
119 }
120 } else {
121 /* Set pin to highz */
122 reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
123 }
124 } else {
125 /* PDRV/SNVS/LPSR type register layout */
126 if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
127 reg &= ~IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
128 if (((flags & GPIO_PULL_UP) != 0)) {
129 reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x1U);
130 } else {
131 reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x2U);
132 }
133 } else {
134 /* Set pin to no pull */
135 reg |= IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
136 }
137 /* PDRV/SNVS/LPSR reg have different ODE bits */
138 if (config->pin_muxes[cfg_idx].pdrv_mux) {
139 if ((flags & GPIO_SINGLE_ENDED) != 0) {
140 /* Set ODE bit */
141 reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
142 } else {
143 reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
144 }
145 } else if (config->pin_muxes[cfg_idx].lpsr_mux) {
146 if ((flags & GPIO_SINGLE_ENDED) != 0) {
147 /* Set ODE bit */
148 reg |= (IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 1);
149 } else {
150 reg &= ~(IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 1);
151 }
152 } else if (config->pin_muxes[cfg_idx].snvs_mux) {
153 if ((flags & GPIO_SINGLE_ENDED) != 0) {
154 /* Set ODE bit */
155 reg |= (IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 2);
156 } else {
157 reg &= ~(IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 2);
158 }
159 }
160
161
162 }
163 #elif defined(CONFIG_SOC_MIMX8MQ6_M4)
164 if ((flags & GPIO_SINGLE_ENDED) != 0) {
165 /* Set ODE bit */
166 reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
167 } else {
168 reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
169 }
170 if ((flags & GPIO_PULL_UP) != 0) {
171 reg |= (0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
172 }
173 if ((flag & GPIO_PULL_DOWN) != 0) {
174 return -ENOTSUP;
175 }
176 #else
177 /* Default flags, should work for most SOCs */
178 if ((flags & GPIO_SINGLE_ENDED) != 0) {
179 /* Set ODE bit */
180 reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
181 } else {
182 reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
183 }
184 if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
185 reg |= (0x1 << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT);
186 if (((flags & GPIO_PULL_UP) != 0)) {
187 reg |= (0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
188 } else {
189 reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
190 }
191 } else {
192 /* Set pin to highz */
193 reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT);
194 }
195 #endif /* CONFIG_SOC_SERIES_IMXRT10XX */
196
197 memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg.pinmux));
198 /* cfg register will be set by pinctrl_configure_pins */
199 pin_cfg.pin_ctrl_flags = reg;
200 pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE);
201
202 if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
203 return -ENOTSUP;
204 }
205
206 if (flags & GPIO_OUTPUT_INIT_HIGH) {
207 GPIO_WritePinOutput(base, pin, 1);
208 }
209
210 if (flags & GPIO_OUTPUT_INIT_LOW) {
211 GPIO_WritePinOutput(base, pin, 0);
212 }
213
214 WRITE_BIT(base->GDIR, pin, flags & GPIO_OUTPUT);
215
216 return 0;
217 }
218
mcux_igpio_port_get_raw(const struct device * dev,uint32_t * value)219 static int mcux_igpio_port_get_raw(const struct device *dev, uint32_t *value)
220 {
221 GPIO_Type *base = get_base(dev);
222
223 *value = base->DR;
224
225 return 0;
226 }
227
mcux_igpio_port_set_masked_raw(const struct device * dev,uint32_t mask,uint32_t value)228 static int mcux_igpio_port_set_masked_raw(const struct device *dev,
229 uint32_t mask,
230 uint32_t value)
231 {
232 GPIO_Type *base = get_base(dev);
233
234 base->DR = (base->DR & ~mask) | (mask & value);
235
236 return 0;
237 }
238
mcux_igpio_port_set_bits_raw(const struct device * dev,uint32_t mask)239 static int mcux_igpio_port_set_bits_raw(const struct device *dev,
240 uint32_t mask)
241 {
242 GPIO_Type *base = get_base(dev);
243
244 GPIO_PortSet(base, mask);
245
246 return 0;
247 }
248
mcux_igpio_port_clear_bits_raw(const struct device * dev,uint32_t mask)249 static int mcux_igpio_port_clear_bits_raw(const struct device *dev,
250 uint32_t mask)
251 {
252 GPIO_Type *base = get_base(dev);
253
254 GPIO_PortClear(base, mask);
255
256 return 0;
257 }
258
mcux_igpio_port_toggle_bits(const struct device * dev,uint32_t mask)259 static int mcux_igpio_port_toggle_bits(const struct device *dev,
260 uint32_t mask)
261 {
262 GPIO_Type *base = get_base(dev);
263
264 GPIO_PortToggle(base, mask);
265
266 return 0;
267 }
268
mcux_igpio_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)269 static int mcux_igpio_pin_interrupt_configure(const struct device *dev,
270 gpio_pin_t pin,
271 enum gpio_int_mode mode,
272 enum gpio_int_trig trig)
273 {
274 const struct mcux_igpio_config *config = dev->config;
275 GPIO_Type *base = get_base(dev);
276 unsigned int key;
277 uint8_t icr;
278 int shift;
279
280 /* Make sure pin is supported */
281 if ((config->common.port_pin_mask & BIT(pin)) == 0) {
282 return -ENOTSUP;
283 }
284
285 if (mode == GPIO_INT_MODE_DISABLED) {
286 key = irq_lock();
287
288 WRITE_BIT(base->IMR, pin, 0);
289
290 irq_unlock(key);
291
292 return 0;
293 }
294
295 if ((mode == GPIO_INT_MODE_EDGE) && (trig == GPIO_INT_TRIG_LOW)) {
296 icr = 3;
297 } else if ((mode == GPIO_INT_MODE_EDGE) &&
298 (trig == GPIO_INT_TRIG_HIGH)) {
299 icr = 2;
300 } else if ((mode == GPIO_INT_MODE_LEVEL) &&
301 (trig == GPIO_INT_TRIG_HIGH)) {
302 icr = 1;
303 } else {
304 icr = 0;
305 }
306
307 if (pin < 16) {
308 shift = 2 * pin;
309 base->ICR1 = (base->ICR1 & ~(3 << shift)) | (icr << shift);
310 } else if (pin < 32) {
311 shift = 2 * (pin - 16);
312 base->ICR2 = (base->ICR2 & ~(3 << shift)) | (icr << shift);
313 } else {
314 return -EINVAL;
315 }
316
317 key = irq_lock();
318
319 WRITE_BIT(base->EDGE_SEL, pin, trig == GPIO_INT_TRIG_BOTH);
320 WRITE_BIT(base->ISR, pin, 1);
321 WRITE_BIT(base->IMR, pin, 1);
322
323 irq_unlock(key);
324
325 return 0;
326 }
327
mcux_igpio_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)328 static int mcux_igpio_manage_callback(const struct device *dev,
329 struct gpio_callback *callback,
330 bool set)
331 {
332 struct mcux_igpio_data *data = dev->data;
333
334 return gpio_manage_callback(&data->callbacks, callback, set);
335 }
336
mcux_igpio_port_isr(const struct device * dev)337 static void mcux_igpio_port_isr(const struct device *dev)
338 {
339 struct mcux_igpio_data *data = dev->data;
340 GPIO_Type *base = get_base(dev);
341 uint32_t int_flags;
342
343 int_flags = base->ISR;
344 base->ISR = int_flags;
345
346 gpio_fire_callbacks(&data->callbacks, dev, int_flags);
347 }
348
349 static DEVICE_API(gpio, mcux_igpio_driver_api) = {
350 .pin_configure = mcux_igpio_configure,
351 .port_get_raw = mcux_igpio_port_get_raw,
352 .port_set_masked_raw = mcux_igpio_port_set_masked_raw,
353 .port_set_bits_raw = mcux_igpio_port_set_bits_raw,
354 .port_clear_bits_raw = mcux_igpio_port_clear_bits_raw,
355 .port_toggle_bits = mcux_igpio_port_toggle_bits,
356 .pin_interrupt_configure = mcux_igpio_pin_interrupt_configure,
357 .manage_callback = mcux_igpio_manage_callback,
358 };
359
360
361 /* These macros will declare an array of pinctrl_soc_pinmux types */
362 #define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
363 #define MCUX_IGPIO_PIN_DECLARE(n) \
364 const struct pinctrl_soc_pinmux mcux_igpio_pinmux_##n[] = { \
365 DT_FOREACH_PROP_ELEM(DT_DRV_INST(n), pinmux, PINMUX_INIT) \
366 };
367 #define MCUX_IGPIO_PIN_INIT(n) \
368 .pin_muxes = mcux_igpio_pinmux_##n, \
369 .mux_count = DT_PROP_LEN(DT_DRV_INST(n), pinmux)
370
371 #define MCUX_IGPIO_IRQ_INIT(n, i) \
372 do { \
373 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, i, irq), \
374 DT_INST_IRQ_BY_IDX(n, i, priority), \
375 mcux_igpio_port_isr, \
376 DEVICE_DT_INST_GET(n), 0); \
377 \
378 irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq)); \
379 } while (false)
380
381 #define MCUX_IGPIO_INIT(n) \
382 MCUX_IGPIO_PIN_DECLARE(n) \
383 static int mcux_igpio_##n##_init(const struct device *dev); \
384 \
385 static const struct mcux_igpio_config mcux_igpio_##n##_config = {\
386 DEVICE_MMIO_NAMED_ROM_INIT(igpio_mmio, DT_DRV_INST(n)), \
387 .common = { \
388 .port_pin_mask = GPIO_DT_INST_PORT_PIN_MASK_NGPIOS_EXC(\
389 n, DT_INST_PROP(n, ngpios)),\
390 }, \
391 MCUX_IGPIO_PIN_INIT(n) \
392 }; \
393 \
394 static struct mcux_igpio_data mcux_igpio_##n##_data; \
395 \
396 DEVICE_DT_INST_DEFINE(n, \
397 mcux_igpio_##n##_init, \
398 NULL, \
399 &mcux_igpio_##n##_data, \
400 &mcux_igpio_##n##_config, \
401 POST_KERNEL, \
402 CONFIG_GPIO_INIT_PRIORITY, \
403 &mcux_igpio_driver_api); \
404 \
405 static int mcux_igpio_##n##_init(const struct device *dev) \
406 { \
407 IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \
408 (MCUX_IGPIO_IRQ_INIT(n, 0);)) \
409 \
410 IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 1), \
411 (MCUX_IGPIO_IRQ_INIT(n, 1);)) \
412 \
413 DEVICE_MMIO_NAMED_MAP(dev, igpio_mmio, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); \
414 \
415 return 0; \
416 }
417
418 DT_INST_FOREACH_STATUS_OKAY(MCUX_IGPIO_INIT)
419
