1 /* 2 * Copyright 2024, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT118X_H_ 8 #define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT118X_H_ 9 10 #include <zephyr/devicetree.h> 11 #include <zephyr/types.h> 12 #include "fsl_common.h" 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 #define MCUX_IMX_ODE_SHIFT 4 19 #define MCUX_IMX_PUS_SHIFT 3 20 #define MCUX_IMX_PUE_SHIFT 2 21 #define MCUX_IMX_DSE_SHIFT 1 22 #define MCUX_IMX_SRE_SHIFT 0 23 #define MCUX_IMX_PULL_SHIFT 2 24 #define MCUX_IMX_PULL_PULLDOWN 0x2 25 #define MCUX_IMX_PULL_PULLUP 0x1 26 #define MCUX_IMX_PDRV_SHIFT 1 27 #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ 28 #define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1) 29 30 31 /* 32 * RT11xx has multiple types of register layouts defined for pin configuration 33 * registers. There are four types defined: 34 * pdrv_pull: registers lack a slew rate and pus field 35 * pue_pus: registers have a slew rate and ode field 36 * pue_pus_lpsr: in low power state retention domain, shifted ode field 37 * pue_pus_snvs: in SNVS domain, shifted ode field 38 */ 39 40 #define MCUX_IMX_PUS_PUE 0 41 #define MCUX_IMX_PDRV_PULL 1 42 #define MCUX_IMX_LPSR 2 43 #define MCUX_IMX_SNVS 3 44 45 /* 46 * Macro for MCUX_IMX_PULL_NOPULL, which needs to set field to 0x3 if two 47 * properties are false 48 */ 49 #define MCUX_IMX_NOPULL(node_id) \ 50 ((0x2 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 1)) |\ 51 (0x1 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 0))) \ 52 53 #define Z_PINCTRL_MCUX_IMX_PDRV(node_id) \ 54 IF_ENABLED(DT_PROP(node_id, bias_pull_down), \ 55 (MCUX_IMX_PULL_PULLDOWN << MCUX_IMX_PULL_SHIFT) |) \ 56 IF_ENABLED(DT_PROP(node_id, bias_pull_up), \ 57 (MCUX_IMX_PULL_PULLUP << MCUX_IMX_PULL_SHIFT) |) \ 58 (MCUX_IMX_NOPULL(node_id) << MCUX_IMX_PULL_SHIFT) | \ 59 ((!DT_ENUM_IDX_OR(node_id, drive_strength, 0)) << MCUX_IMX_PDRV_SHIFT) | \ 60 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \ 61 (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT) 62 63 #define Z_PINCTRL_MCUX_IMX_PUE_PUS(node_id) \ 64 (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \ 65 ((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \ 66 << MCUX_IMX_PUE_SHIFT) | \ 67 (DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) | \ 68 (DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) | \ 69 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \ 70 (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT) 71 72 /* This struct must be present. It is used by the mcux gpio driver */ 73 struct pinctrl_soc_pinmux { 74 uint32_t mux_register; /* IOMUXC SW_PAD_MUX register */ 75 uint32_t config_register; /* IOMUXC SW_PAD_CTL register */ 76 uint32_t input_register; /* IOMUXC SELECT_INPUT DAISY register */ 77 uint8_t mux_mode: 4; /* Mux value for SW_PAD_MUX register */ 78 uint32_t input_daisy:4; /* Mux value for SELECT_INPUT_DAISY register */ 79 uint8_t pue_mux: 1; /* Is pinmux reg pue type */ 80 uint8_t pdrv_mux: 1; /* Is pinmux reg pdrv type */ 81 }; 82 83 struct pinctrl_soc_pin { 84 struct pinctrl_soc_pinmux pinmux; 85 uint32_t pin_ctrl_flags; /* value to write to IOMUXC_SW_PAD_CTL register */ 86 }; 87 88 typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; 89 90 /* This definition must be present. It is used by the mcux gpio driver */ 91 #define MCUX_IMX_PINMUX(node_id) \ 92 { \ 93 .mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \ 94 .config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \ 95 .input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \ 96 .mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \ 97 .input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \ 98 .pue_mux = DT_PROP(node_id, pin_pue), \ 99 .pdrv_mux = DT_PROP(node_id, pin_pdrv), \ 100 } 101 102 #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ 103 MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) 104 105 #define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ 106 { \ 107 .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \ 108 IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pue), \ 109 (.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PUE_PUS(group_id),)) \ 110 IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pdrv), \ 111 (.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PDRV(group_id),)) \ 112 }, 113 114 #define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ 115 {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ 116 DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \ 117 118 119 #ifdef __cplusplus 120 } 121 #endif 122 123 #endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT118X_H_ */ 124
