1# Copyright (c) 2022 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree. These
6  nodes can be autogenerated using the MCUXpresso config tools combined with
7  the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
8  fields in a group select the pins to be configured, and the remaining
9  devicetree properties set configuration values for those pins
10  for example, here is an group configuring LPUART1 pins:
11
12  group0 {
13      pinmux = <&iomuxc_gpio_ad_25_lpuart1_rxd>,
14          <&iomuxc_gpio_ad_24_lpuart1_txd>;
15      drive-strength = "high";
16      slew-rate = "slow";
17  };
18
19  This will select GPIO_AD_25 as LPUART1 RX, and GPIO_AD_24 as LPUART1 TX.
20  Both pins will be configured with a weak latch, high drive strength,
21  and slow slew rates.
22  Note that the soc level iomuxc dts file can be examined to find the possible
23  pinmux options. Here are the affects of each property on the
24  IOMUXC SW_PAD_CTL register:
25  drive-open-drain: ODE/ODE_LPSR=1
26  input-enable: SION=1 (in SW_MUX_CTL_PAD register)
27  bias-pull-down: PUE=1, PUS=0
28  bias-pull-up: PUE=1, PUS=1
29  bias-disable: PULL=11 (in supported registers)
30  slew-rate: SRE=<enum_idx>
31  drive-strength: DSE=<enum_idx>
32
33  If only required properties are supplied, the pin will have the following
34  configuration:
35  ODE=0
36  SION=0
37  PUE=0
38  PUS=0
39  SRE=0
40  DSE=0
41
42  For registers with PDVR and PULL fields, these are the defaults:
43  PULL=11
44  PDRV=0
45
46
47compatible: "nxp,mcux-rt11xx-pinctrl"
48
49include: base.yaml
50
51child-binding:
52  description: MCUX RT pin controller pin group
53  child-binding:
54    description: |
55      MCUX RT pin controller pin configuration node.
56
57    include:
58      - name: pincfg-node.yaml
59        property-allowlist:
60          - drive-open-drain
61          - input-enable
62          - bias-disable
63          - bias-pull-down
64          - bias-pull-up
65
66    properties:
67      pinmux:
68        required: true
69        type: phandles
70        description: |
71          Pin mux selections for this group. See the soc level iomuxc DTSI file
72          for a defined list of these options.
73      drive-strength:
74        type: string
75        enum:
76          - "normal"
77          - "high"
78        description: |
79          Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
80          0 (normal) - sets pin to normal drive strength
81          1 (high) - sets pin to high drive strength
82      slew-rate:
83        type: string
84        enum:
85          - "fast"
86          - "slow"
87        description: |
88          Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
89          0 (fast) — Fast Slew Rate
90          1 (slow) — Slow Slew Rate
91