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/Zephyr-latest/dts/bindings/video/
Dnxp,video-smartdma.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,video-smartdma"
8 include: [base.yaml, pinctrl-device.yaml]
15 vsync-pin:
19 GPIO0 pin index to use for VSYNC input. Only pins 0-15 may be used.
20 hsync-pin:
24 GPIO0 pin index to use for HSYNC input. Only pins 0-15 may be used.
25 pclk-pin:
29 GPIO0 pin index to use for PCLK input. Only pins 0-15 may be used.
/Zephyr-latest/dts/bindings/gpio/
Dnxp,cam-44pins-connector.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on NXP 44-pin board-to-board camera connector.
14 12 GPIO0 PCLK 11
31 compatible: "nxp,cam-44pins-connector"
33 include: [gpio-nexus.yaml, base.yaml]
/Zephyr-latest/drivers/serial/
Duart_ns16550.c1 /* ns16550.c - NS16550D serial driver */
6 * Copyright (c) 2010, 2012-2015 Wind River Systems, Inc.
7 * Copyright (c) 2020-2023 Intel Corp.
9 * SPDX-License-Identifier: Apache-2.0
72 /* If any node has property io-mapped set, we need to support IO port
76 * as io-mapped property is considered always exists and present,
78 * resort to the follow helper to see if any okay nodes have io-mapped
164 * RXRDY pin (29) will be low active. Once it is activated the
165 * RXRDY pin will go inactive when there are no more charac-
170 * reached, the RXRDY pin will go low active. Once it is acti-
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Duart_lpc11u6x.c4 * SPDX-License-Identifier: Apache-2.0
19 const struct lpc11u6x_uart0_config *cfg = dev->config; in lpc11u6x_uart0_poll_in()
21 if (!(cfg->uart0->lsr & LPC11U6X_UART0_LSR_RDR)) { in lpc11u6x_uart0_poll_in()
22 return -1; in lpc11u6x_uart0_poll_in()
24 *c = cfg->uart0->rbr; in lpc11u6x_uart0_poll_in()
31 const struct lpc11u6x_uart0_config *cfg = dev->config; in lpc11u6x_uart0_poll_out()
33 while (!(cfg->uart0->lsr & LPC11U6X_UART0_LSR_THRE)) { in lpc11u6x_uart0_poll_out()
35 cfg->uart0->thr = c; in lpc11u6x_uart0_poll_out()
40 const struct lpc11u6x_uart0_config *cfg = dev->config; in lpc11u6x_uart0_err_check()
44 lsr = cfg->uart0->lsr; in lpc11u6x_uart0_err_check()
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/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dfrdm_mcxn947.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include "frdm_mcxn947-pinctrl.dtsi"
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
19 mcuboot-button0 = &user_button_2;
23 compatible = "gpio-leds";
42 compatible = "gpio-keys";
58 * This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface.
60 nxp_lcd_8080_connector: lcd-8080-connector {
61 compatible = "nxp,lcd-8080";
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/Zephyr-latest/dts/arm/silabs/
Defr32bg2x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/pinctrl/gecko-pinctrl.h>
11 #include <dt-bindings/adc/adc.h>
16 zephyr,flash-controller = &msc;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
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Defr32mg21.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <dt-bindings/clock/silabs/xg21-clock.h>
17 zephyr,flash-controller = &msc;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
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Defr32mg24.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/adc/adc.h>
11 #include <dt-bindings/clock/silabs/xg24-clock.h>
16 zephyr,flash-controller = &msc;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
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Defr32xg23.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/adc/adc.h>
11 #include <dt-bindings/clock/silabs/xg23-clock.h>
16 zephyr,flash-controller = &msc;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
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/Zephyr-latest/drivers/spi/
Dspi_b91.c4 * SPDX-License-Identifier: Apache-2.0
38 #define SPI_CFG(dev) ((struct spi_b91_cfg *) ((dev)->config))
44 #define SPI_DATA(dev) ((struct spi_b91_data *) ((dev)->data))
50 gpio_pin_e pin; in spi_b91_hw_cs_disable() local
54 /* get CS pin defined in device tree */ in spi_b91_hw_cs_disable()
55 pin = config->cs_pin[i]; in spi_b91_hw_cs_disable()
57 /* if CS pin is defined in device tree */ in spi_b91_hw_cs_disable()
58 if (pin != 0) { in spi_b91_hw_cs_disable()
59 if (config->peripheral_id == PSPI_MODULE) { in spi_b91_hw_cs_disable()
60 /* disable CS pin for PSPI */ in spi_b91_hw_cs_disable()
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/Zephyr-latest/boards/shields/nxp_btb44_ov5640/doc/
Dindex.rst3 NXP BTB-44 OV5640 Camera Module
9 This shield supports ov5640 camera modules which use a 44-pin board-to-board connector and
15 Pins assignment of the NXP board-to-board 44-pin OV5640 camera module
18 +----------------------+--------------------+
19 | Camera Connector Pin | Function |
22 +----------------------+--------------------+
24 +----------------------+--------------------+
26 +----------------------+--------------------+
28 +----------------------+--------------------+
30 +----------------------+--------------------+
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/Zephyr-latest/drivers/video/
Dov7670.c4 * SPDX-License-Identifier: Apache-2.0
210 /* PCLK does not toggle during horizontal blank, one PCLK, one pixel */
213 /* Brightness Control, with signal -128 to +128, 0x00 is middle value */
216 /* Internal clock pre-scalar,F(internal clock) = F(input clock)/(Bit[5:0]+1) */
233 {OV7670_DNSTH, 0x00}, /* De-noise Strength */
268 /* AGC/AEC - Automatic Gain Control/Automatic exposure Control */
327 /* Histogram-based AEC/AGC Control */
347 caps->format_caps = fmts; in ov7670_get_caps()
354 const struct ov7670_config *config = dev->config; in ov7670_set_fmt()
355 struct ov7670_data *data = dev->data; in ov7670_set_fmt()
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/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo3_blue.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
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Dambiq_apollo4p.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
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Dambiq_apollo4p_blue.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/i2c/i2c.h>
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 uartclk: apb-pclk {
12 compatible = "fixed-clock";
13 clock-frequency = <DT_FREQ_M(24)>;
14 #clock-cells = <0>;
18 clock-frequency = <DT_FREQ_M(32)>;
19 #clock-cells = <1>;
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Dambiq_apollo3p_blue.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
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/Zephyr-latest/modules/hal_silabs/simplicity_sdk/config/
Dsl_clock_manager_tree_config.h4 * SPDX-License-Identifier: Apache-2.0
44 CONCAT(CMU_SYSCLKCTRL_PCLKPRESC_DIV, DT_PROP(DT_NODELABEL(pclk), clock_div))
304 /* FIXME: allow clock selection from S0 pin */
/Zephyr-latest/boards/espressif/esp_wrover_kit/doc/
Dindex.rst6 ESP-WROVER-KIT is an ESP32-based development board produced by `Espressif <https://www.espressif.co…
8 ESP-WROVER-KIT features the following integrated components:
10 - ESP32-WROVER-E module
11 - LCD screen
12 - MicroSD card slot
14 Its another distinguishing feature is the embedded FTDI FT2232HL chip - an advanced multi-interface
16 without a separate JTAG debugger. ESP-WROVER-KIT makes development convenient, easy, and
17 cost-effective.
19 Most of the ESP32 I/O pins are broken out to the board's pin headers for easy access.
24 GPIOs are not broken out to the board's pin headers in order to ensure reliable performance.
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/Zephyr-latest/doc/releases/
Drelease-notes-4.0.rst15 is now the standard way to provide device-specific protection to data at rest. (:github:`76222`)
18 :ref:`ZMS <zms_api>` is a new key-value storage subsystem compatible with all non-volatile storage
25 runtime configuration through vendor specific APIs. Initially the :dtcompatible:`nordic,nrf-comp`,
26 :dtcompatible:`nordic,nrf-lpcomp` and :dtcompatible:`nxp,kinetis-acmp` are supported.
31 Initially implemented drivers include a simple :dtcompatible:`zephyr,gpio-steppers` and a complex
32 sensor-less stall-detection capable with integrated ramp-controller :dtcompatible:`adi,tmc5041`.
50 directory for :zephyr:code-sample-category:`code samples <samples>`.
70 * :cve:`2024-8798`: Under embargo until 2024-11-22
71 * :cve:`2024-10395`: Under embargo until 2025-01-23
72 * :cve:`2024-11263` `Zephyr project bug tracker GHSA-jjf3-7x72-pqm9
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