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/Zephyr-latest/dts/bindings/interrupt-controller/
Dintel,ace-intc.yaml3 compatible: "intel,ace-intc"
5 include: [interrupt-controller.yaml, base.yaml]
14 "#interrupt-cells":
17 num-irqs:
22 interrupt-cells:
23 - irq
24 - sense
25 - priority
Dsnps,designware-intc.yaml3 compatible: "snps,designware-intc"
5 include: [interrupt-controller.yaml, base.yaml]
14 "#interrupt-cells":
17 num-irqs:
22 interrupt-cells:
23 - irq
24 - sense
25 - priority
/Zephyr-latest/tests/drivers/build_all/interrupt_controller/common/boards/
Dintel_adsp_ace20_lnl.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Made-up devicetree to build intc_dw.c */
12 compatible = "snps,designware-intc";
14 interrupt-controller;
15 #interrupt-cells = <3>;
17 num-irqs = <28>;
18 interrupt-parent = <&core_intc>;
/Zephyr-latest/drivers/interrupt_controller/
DKconfig.multilevel5 # SPDX-License-Identifier: Apache-2.0
8 bool "Multi-level interrupt support"
31 int "Max IRQs per interrupt aggregator"
39 bool "Second-level interrupt support"
71 prev-level-num = 1
72 cur-level-num = 2
73 cur-level = 2ND
92 bool "Third-level interrupt support"
125 prev-level-num = 2
126 cur-level-num = 3
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/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8m1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(20)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
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Dr7fa8d1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 sdram: sdram-controller@40002000 {
13 compatible = "renesas,ra-sdram";
14 #address-cells = <1>;
15 #size-cells = <0>;
20 lcdif: display-controller@40342000 {
21 compatible = "renesas,ra-glcdc";
25 interrupt-names = "line";
30 compatible = "renesas,ra-mipi-dsi";
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/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6m3ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-gpio-ioport";
22 gpio-controller;
23 #gpio-cells = <2>;
29 compatible = "renesas,ra-gpio-ioport";
32 gpio-controller;
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Dr7fa6m5xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-gpio-ioport";
22 gpio-controller;
23 #gpio-cells = <2>;
29 compatible = "renesas,ra-gpio-ioport";
32 gpio-controller;
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/Zephyr-latest/lib/acpi/
Dacpi_shell.c4 * SPDX-License-Identifier: Apache-2.0
23 if (!res->Length) { in dump_dev_res()
28 switch (res->Type) { in dump_dev_res()
31 ACPI_RESOURCE_IRQ *irq_res = &res->Data.Irq; in dump_dev_res()
33 shell_print(sh, "\tDescriptorLength: %x", irq_res->DescriptorLength); in dump_dev_res()
34 shell_print(sh, "\tTriggering: %x", irq_res->Triggering); in dump_dev_res()
35 shell_print(sh, "\tPolarity: %x", irq_res->Polarity); in dump_dev_res()
36 shell_print(sh, "\tShareable: %x", irq_res->Shareable); in dump_dev_res()
37 shell_print(sh, "\tInterruptCount: %d", irq_res->InterruptCount); in dump_dev_res()
38 shell_print(sh, "\tInterrupts[0]: %x", irq_res->Interrupts[0]); in dump_dev_res()
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/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dr7fa4l1bx.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
10 #include <zephyr/dt-bindings/clock/ra_clock.h>
11 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m33";
23 #address-cells = <1>;
24 #size-cells = <1>;
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/Zephyr-latest/arch/arm64/core/cortex_r/
Darm_mpu.c5 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/linker/linker-defs.h>
20 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
29 "`zephyr,memory-region-mpu` was deprecated in favor of `zephyr,memory-attr`");
49 #define MPU_DYNAMIC_REGIONS_AREA_SIZE ((size_t)((uintptr_t)&__kernel_ram_end - \
58 * Armv8, for Armv8-R AArch64 architecture profile, G1.3.7
124 * Configure the cache-ability attributes for all the
129 /* Device region(s): Attribute-0 in mpu_init()
130 * Flash region(s): Attribute-1 in mpu_init()
131 * SRAM region(s): Attribute-2 in mpu_init()
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/Zephyr-latest/tests/kernel/mem_protect/demand_paging/mem_map/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
15 #define EXTRA_PAGES (CONFIG_BACKING_STORE_RAM_PAGES - 1)
69 printk("Caught system error -- reason %d\n", reason); in k_sys_fatal_error_handler()
102 printk(" - Total: %lu\n", stats->pagefaults.cnt); in print_paging_stats()
103 printk(" - IRQ locked: %lu\n", stats->pagefaults.irq_locked); in print_paging_stats()
104 printk(" - IRQ unlocked: %lu\n", stats->pagefaults.irq_unlocked); in print_paging_stats()
106 printk(" - in ISR: %lu\n", stats->pagefaults.in_isr); in print_paging_stats()
110 printk(" - Total pages evicted: %lu\n", in print_paging_stats()
111 stats->eviction.clean + stats->eviction.dirty); in print_paging_stats()
112 printk(" - Clean pages evicted: %lu\n", in print_paging_stats()
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/Zephyr-latest/dts/xtensa/intel/
Dintel_adsp_ace20_lnl.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx7";
19 cpu-power-states = <&d0i3 &d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx7";
28 cpu-power-states = <&d0i3 &d3>;
33 compatible = "cdns,tensilica-xtensa-lx7";
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Dintel_adsp_ace30_ptl.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx7";
19 cpu-power-states = <&d0i3 &d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx7";
28 cpu-power-states = <&d0i3 &d3>;
33 compatible = "cdns,tensilica-xtensa-lx7";
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Dintel_adsp_ace30.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx7";
19 cpu-power-states = <&d0i3 &d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx7";
28 cpu-power-states = <&d0i3 &d3>;
33 compatible = "cdns,tensilica-xtensa-lx7";
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Dintel_adsp_ace15_mtpm.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx7";
19 cpu-power-states = <&d0i3 &d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx7";
28 cpu-power-states = <&d3>;
33 compatible = "cdns,tensilica-xtensa-lx7";
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/Zephyr-latest/doc/hardware/arch/
Darm_cortex_m.rst3 Arm Cortex-M Developer Guide
9 This page contains detailed information about the status of the Arm Cortex-M
11 developing Zephyr applications for Arm Cortex-M-based platforms.
17 Arm Cortex-M implementation variants.
20 …---------------------------------+-----------------------------------+-----------------+---------+…
22 …---------------------------------+-----------------------------------+-----------------+---------+…
23 … | Arm v6-M | Arm v7-M | Arm v8-M …
24 …---------------------------------+-----------------------------------+-----------------+---------+…
26 …---------------------------------+-----------------------------------+-----------------+---------+…
28 …---------------------------------+-----------------------------------+-----------------+---------+…
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