1/* 2 * Copyright (c) 2024 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <xtensa/xtensa.dtsi> 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "cdns,tensilica-xtensa-lx7"; 18 reg = <0>; 19 cpu-power-states = <&d0i3 &d3>; 20 i-cache-line-size = <64>; 21 d-cache-line-size = <64>; 22 }; 23 24 cpu1: cpu@1 { 25 device_type = "cpu"; 26 compatible = "cdns,tensilica-xtensa-lx7"; 27 reg = <1>; 28 cpu-power-states = <&d0i3 &d3>; 29 }; 30 31 cpu2: cpu@2 { 32 device_type = "cpu"; 33 compatible = "cdns,tensilica-xtensa-lx7"; 34 reg = <2>; 35 cpu-power-states = <&d0i3 &d3>; 36 }; 37 38 cpu3: cpu@3 { 39 device_type = "cpu"; 40 compatible = "cdns,tensilica-xtensa-lx7"; 41 reg = <3>; 42 cpu-power-states = <&d0i3 &d3>; 43 }; 44 45 cpu4: cpu@4 { 46 device_type = "cpu"; 47 compatible = "cdns,tensilica-xtensa-lx7"; 48 reg = <4>; 49 cpu-power-states = <&d0i3 &d3>; 50 }; 51 }; 52 53 power-states { 54 d0i3: idle { 55 compatible = "zephyr,power-state"; 56 power-state-name = "runtime-idle"; 57 min-residency-us = <200>; 58 exit-latency-us = <100>; 59 }; 60 /* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force. 61 * The procedure is triggered by IPC from the HOST (SET_DX). 62 */ 63 d3: off { 64 compatible = "zephyr,power-state"; 65 power-state-name = "soft-off"; 66 min-residency-us = <0>; 67 exit-latency-us = <0>; 68 status = "disabled"; 69 }; 70 }; 71 72 sram0: memory@a0020000 { 73 device_type = "memory"; 74 compatible = "mmio-sram"; 75 reg = <0xa0020000 DT_SIZE_K(4608)>; 76 }; 77 78 sram0virtual: virtualmemory@a0020000 { 79 device_type = "memory"; 80 compatible = "mmio-sram"; 81 reg = <0xa0020000 DT_SIZE_K(8192)>; 82 }; 83 84 sram1: memory@a0000000 { 85 device_type = "memory"; 86 compatible = "mmio-sram"; 87 reg = <0xa0000000 DT_SIZE_K(64)>; 88 }; 89 90 sysclk: system-clock { 91 compatible = "fixed-clock"; 92 clock-frequency = <38400000>; 93 #clock-cells = <0>; 94 }; 95 96 clkctl: clkctl { 97 compatible = "intel,adsp-shim-clkctl"; 98 adsp-clkctl-clk-wovcro = <0>; 99 adsp-clkctl-clk-ipll = <1>; 100 adsp-clkctl-freq-enc = <0xc 0x4>; 101 adsp-clkctl-freq-mask = <0x0 0x0>; 102 adsp-clkctl-freq-default = <1>; 103 adsp-clkctl-freq-lowest = <0>; 104 wovcro-supported; 105 }; 106 107 audioclk: audio-clock { 108 compatible = "fixed-clock"; 109 clock-frequency = <24576000>; 110 #clock-cells = <0>; 111 }; 112 113 pllclk: pll-clock { 114 compatible = "fixed-clock"; 115 clock-frequency = <96000000>; 116 #clock-cells = <0>; 117 }; 118 119 IMR1: memory@A1000000 { 120 compatible = "intel,adsp-imr"; 121 reg = <0xA1000000 DT_SIZE_M(16)>; 122 block-size = <0x1000>; 123 zephyr,memory-region = "IMR1"; 124 }; 125 126 soc { 127 l1ccap: l1ccap@3fe80080 { 128 compatible = "intel,adsp-l1ccap"; 129 reg = <0x3fe80080 0x4>; 130 }; 131 132 l1ccfg: l1ccfg@3fe80084 { 133 compatible = "intel,adsp-l1ccfg"; 134 reg = <0x3fe80084 0x4>; 135 }; 136 137 l1pcfg: l1pcfg@3fe80088 { 138 compatible = "intel,adsp-l1pcfg"; 139 reg = <0x3fe80088 0x4>; 140 }; 141 142 hsbcap: hsbcap@71d00 { 143 compatible = "intel,adsp-hsbcap"; 144 reg = <0x71d00 0x4>; 145 }; 146 147 lsbpm: lsbpm@71d80 { 148 compatible = "intel,adsp-lsbpm"; 149 reg = <0x71d80 0x0008>; 150 }; 151 152 hsbpm: hsbpm@17a800 { 153 compatible = "intel,adsp-hsbpm"; 154 reg = <0x17a800 0x0008>; 155 }; 156 157 core_intc: core_intc@0 { 158 compatible = "cdns,xtensa-core-intc"; 159 reg = <0x00 0x400>; 160 interrupt-controller; 161 #interrupt-cells = <3>; 162 }; 163 164 hdamlddmic: hdamlddmic@cc0 { 165 compatible = "intel,adsp-hda-dmic-cap"; 166 reg = <0xcc0 0x40>; 167 status = "okay"; 168 }; 169 170 dmic0: dai-dmic0@10100 { 171 compatible = "intel,dai-dmic"; 172 reg = <0x10100 0x8000>; 173 shim = <0x10000>; 174 fifo = <0x0008>; 175 interrupts = <0x08 0 0>; 176 interrupt-parent = <&ace_intc>; 177 power-domains = <&hub_ulp_domain>; 178 zephyr,pm-device-runtime-auto; 179 }; 180 181 dmic1: dai-dmic1@10100 { 182 compatible = "intel,dai-dmic"; 183 reg = <0x10100 0x8000>; 184 shim = <0x10000>; 185 fifo = <0x0108>; 186 interrupts = <0x08 0 0>; 187 interrupt-parent = <&ace_intc>; 188 power-domains = <&hub_ulp_domain>; 189 zephyr,pm-device-runtime-auto; 190 }; 191 192 dmicvss: dmicvss@16000 { 193 compatible = "intel,adsp-dmic-vss"; 194 reg = <0x16000 0x2000>; 195 status = "okay"; 196 }; 197 198 sspbase: ssp_base@28000 { 199 compatible = "intel,ssp-sspbase"; 200 reg = <0x28000 0x1000>; 201 }; 202 203 hdamlssp: hdamlssp@d00 { 204 compatible = "intel,adsp-hda-ssp-cap"; 205 reg = <0xD00 0x40>; 206 status = "okay"; 207 }; 208 209 ssp0: ssp@28100 { 210 compatible = "intel,ssp"; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 reg = <0x00028100 0x1000 214 0x00079C00 0x200>; 215 i2svss = <0x00028C00 0x1000>; 216 interrupts = <0x00 0 0>; 217 interrupt-parent = <&ace_intc>; 218 dmas = <&hda_link_out 1 219 &hda_link_in 1>; 220 dma-names = "tx", "rx"; 221 ssp-index = <0>; 222 status = "okay"; 223 224 ssp00: ssp@0 { 225 compatible = "intel,ssp-dai"; 226 power-domains = <&io0_domain>; 227 zephyr,pm-device-runtime-auto; 228 reg = <0x0>; 229 status = "okay"; 230 }; 231 232 ssp01: ssp@1 { 233 compatible = "intel,ssp-dai"; 234 power-domains = <&io0_domain>; 235 zephyr,pm-device-runtime-auto; 236 reg = <0x1>; 237 status = "okay"; 238 }; 239 240 ssp02: ssp@2 { 241 compatible = "intel,ssp-dai"; 242 power-domains = <&io0_domain>; 243 zephyr,pm-device-runtime-auto; 244 reg = <0x2>; 245 status = "okay"; 246 }; 247 248 ssp03: ssp@3 { 249 compatible = "intel,ssp-dai"; 250 power-domains = <&io0_domain>; 251 zephyr,pm-device-runtime-auto; 252 reg = <0x3>; 253 status = "okay"; 254 }; 255 256 ssp04: ssp@4 { 257 compatible = "intel,ssp-dai"; 258 power-domains = <&io0_domain>; 259 zephyr,pm-device-runtime-auto; 260 reg = <0x4>; 261 status = "okay"; 262 }; 263 264 ssp05: ssp@5 { 265 compatible = "intel,ssp-dai"; 266 power-domains = <&io0_domain>; 267 zephyr,pm-device-runtime-auto; 268 reg = <0x5>; 269 status = "okay"; 270 }; 271 272 ssp06: ssp@6 { 273 compatible = "intel,ssp-dai"; 274 power-domains = <&io0_domain>; 275 zephyr,pm-device-runtime-auto; 276 reg = <0x6>; 277 status = "okay"; 278 }; 279 280 ssp07: ssp@7 { 281 compatible = "intel,ssp-dai"; 282 power-domains = <&io0_domain>; 283 zephyr,pm-device-runtime-auto; 284 reg = <0x7>; 285 status = "okay"; 286 }; 287 }; 288 289 ssp1: ssp@29100 { 290 compatible = "intel,ssp"; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 reg = <0x00029100 0x1000 294 0x00079C00 0x200>; 295 i2svss = <0x00029C00 0x1000>; 296 interrupts = <0x01 0 0>; 297 interrupt-parent = <&ace_intc>; 298 dmas = <&hda_link_out 2 299 &hda_link_in 2>; 300 dma-names = "tx", "rx"; 301 ssp-index = <1>; 302 status = "okay"; 303 304 ssp10: ssp@10 { 305 compatible = "intel,ssp-dai"; 306 power-domains = <&io0_domain>; 307 zephyr,pm-device-runtime-auto; 308 reg = <0x10>; 309 status = "okay"; 310 }; 311 312 ssp11: ssp@11 { 313 compatible = "intel,ssp-dai"; 314 power-domains = <&io0_domain>; 315 zephyr,pm-device-runtime-auto; 316 reg = <0x11>; 317 status = "okay"; 318 }; 319 320 ssp12: ssp@12 { 321 compatible = "intel,ssp-dai"; 322 power-domains = <&io0_domain>; 323 zephyr,pm-device-runtime-auto; 324 reg = <0x12>; 325 status = "okay"; 326 }; 327 328 ssp13: ssp@13 { 329 compatible = "intel,ssp-dai"; 330 power-domains = <&io0_domain>; 331 zephyr,pm-device-runtime-auto; 332 reg = <0x13>; 333 status = "okay"; 334 }; 335 336 ssp14: ssp@14 { 337 compatible = "intel,ssp-dai"; 338 power-domains = <&io0_domain>; 339 zephyr,pm-device-runtime-auto; 340 reg = <0x14>; 341 status = "okay"; 342 }; 343 344 ssp15: ssp@15 { 345 compatible = "intel,ssp-dai"; 346 power-domains = <&io0_domain>; 347 zephyr,pm-device-runtime-auto; 348 reg = <0x15>; 349 status = "okay"; 350 }; 351 352 ssp16: ssp@16 { 353 compatible = "intel,ssp-dai"; 354 power-domains = <&io0_domain>; 355 zephyr,pm-device-runtime-auto; 356 reg = <0x16>; 357 status = "okay"; 358 }; 359 360 ssp17: ssp@17 { 361 compatible = "intel,ssp-dai"; 362 power-domains = <&io0_domain>; 363 zephyr,pm-device-runtime-auto; 364 reg = <0x17>; 365 status = "okay"; 366 }; 367 }; 368 369 ssp2: ssp@2a100 { 370 compatible = "intel,ssp"; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 reg = <0x0002a100 0x1000 374 0x00079C00 0x200>; 375 i2svss = <0x0002AC00 0x1000>; 376 interrupts = <0x02 0 0>; 377 interrupt-parent = <&ace_intc>; 378 dmas = <&hda_link_out 3 379 &hda_link_in 3>; 380 dma-names = "tx", "rx"; 381 ssp-index = <2>; 382 status = "okay"; 383 384 ssp20: ssp@20 { 385 compatible = "intel,ssp-dai"; 386 power-domains = <&io0_domain>; 387 zephyr,pm-device-runtime-auto; 388 reg = <0x20>; 389 status = "okay"; 390 }; 391 392 ssp21: ssp@21 { 393 compatible = "intel,ssp-dai"; 394 power-domains = <&io0_domain>; 395 zephyr,pm-device-runtime-auto; 396 reg = <0x21>; 397 status = "okay"; 398 }; 399 400 ssp22: ssp@22 { 401 compatible = "intel,ssp-dai"; 402 power-domains = <&io0_domain>; 403 zephyr,pm-device-runtime-auto; 404 reg = <0x22>; 405 status = "okay"; 406 }; 407 408 ssp23: ssp@23 { 409 compatible = "intel,ssp-dai"; 410 power-domains = <&io0_domain>; 411 zephyr,pm-device-runtime-auto; 412 reg = <0x23>; 413 status = "okay"; 414 }; 415 416 ssp24: ssp@24 { 417 compatible = "intel,ssp-dai"; 418 power-domains = <&io0_domain>; 419 zephyr,pm-device-runtime-auto; 420 reg = <0x24>; 421 status = "okay"; 422 }; 423 424 ssp25: ssp@25 { 425 compatible = "intel,ssp-dai"; 426 power-domains = <&io0_domain>; 427 zephyr,pm-device-runtime-auto; 428 reg = <0x25>; 429 status = "okay"; 430 }; 431 432 ssp26: ssp@26 { 433 compatible = "intel,ssp-dai"; 434 power-domains = <&io0_domain>; 435 zephyr,pm-device-runtime-auto; 436 reg = <0x26>; 437 status = "okay"; 438 }; 439 440 ssp27: ssp@27 { 441 compatible = "intel,ssp-dai"; 442 power-domains = <&io0_domain>; 443 zephyr,pm-device-runtime-auto; 444 reg = <0x27>; 445 status = "okay"; 446 }; 447 }; 448 449 mem_window0: mem_window@70200 { 450 compatible = "intel,adsp-mem-window"; 451 reg = <0x70200 0x8>; 452 offset = <0x4000>; 453 memory = <&sram0>; 454 initialize; 455 read-only; 456 }; 457 458 mem_window1: mem_window@70208 { 459 compatible = "intel,adsp-mem-window"; 460 reg = <0x70208 0x8>; 461 memory = <&sram0>; 462 }; 463 464 mem_window2: mem_window@70210 { 465 compatible = "intel,adsp-mem-window"; 466 reg = <0x70210 0x8>; 467 memory = <&sram0>; 468 }; 469 470 mem_window3: mem_window@70218 { 471 compatible = "intel,adsp-mem-window"; 472 reg = <0x70218 0x8>; 473 memory = <&sram0>; 474 read-only; 475 }; 476 477 adsp_idc: ace_idc@92000 { 478 compatible = "intel,adsp-idc"; 479 reg = <0x92000 0x0400>; 480 interrupts = <24 0 0>; 481 interrupt-parent = <&ace_intc>; 482 }; 483 484 dfpmcch: dfpmcch@71ac0 { 485 compatible = "intel,adsp-dfpmcch"; 486 reg = <0x00071ac0 0x40>; 487 }; 488 489 dfpmccu: dfpmccu@71b00 { 490 compatible = "intel,adsp-dfpmccu"; 491 reg = <0x71b00 0x100>; 492 493 hub_ulp_domain: hub_ulp_domain { 494 compatible = "intel,adsp-power-domain"; 495 bit-position = <15>; 496 #power-domain-cells = <0>; 497 }; 498 ml0_domain: ml0_domain { 499 compatible = "intel,adsp-power-domain"; 500 bit-position = <12>; 501 #power-domain-cells = <0>; 502 }; 503 io1_domain: io1_domain { 504 compatible = "intel,adsp-power-domain"; 505 bit-position = <9>; 506 #power-domain-cells = <0>; 507 }; 508 io0_domain: io0_domain { 509 compatible = "intel,adsp-power-domain"; 510 bit-position = <8>; 511 #power-domain-cells = <0>; 512 }; 513 hub_hp_domain: hub_hpp_domain { 514 compatible = "intel,adsp-power-domain"; 515 bit-position = <6>; 516 #power-domain-cells = <0>; 517 }; 518 hst_domain: hst_domain { 519 compatible = "intel,adsp-power-domain"; 520 bit-position = <5>; 521 #power-domain-cells = <0>; 522 }; 523 }; 524 525 shim: shim@71f00 { 526 compatible = "intel,cavs-shim"; 527 reg = <0x71f00 0x100>; 528 }; 529 530 tts: tts@72000 { 531 compatible = "intel,adsp-tts"; 532 reg = <0x72000 0x70>; 533 status = "okay"; 534 }; 535 536 ace_rtc_counter: ace_rtc_counter@72008 { 537 compatible = "intel,ace-rtc-counter"; 538 reg = <0x72008 0x0064>; 539 }; 540 541 ace_timestamp: ace_timestamp@72040 { 542 compatible = "intel,ace-timestamp"; 543 reg = <0x72040 0x0032>; 544 }; 545 546 ace_art_counter: ace_art_counter@72058 { 547 compatible = "intel,ace-art-counter"; 548 reg = <0x72058 0x0064>; 549 }; 550 551 hda_host_out: dma@72800 { 552 compatible = "intel,adsp-hda-host-out"; 553 #dma-cells = <1>; 554 reg = <0x00072800 0x40>; 555 dma-channels = <9>; 556 dma-buf-addr-alignment = <128>; 557 dma-buf-size-alignment = <32>; 558 dma-copy-alignment = <32>; 559 power-domains = <&hst_domain>; 560 zephyr,pm-device-runtime-auto; 561 interrupts = <13 0 0>; 562 interrupt-parent = <&ace_intc>; 563 status = "okay"; 564 }; 565 566 hda_host_in: dma@72c00 { 567 compatible = "intel,adsp-hda-host-in"; 568 #dma-cells = <1>; 569 reg = <0x00072c00 0x40>; 570 dma-channels = <11>; 571 dma-buf-addr-alignment = <128>; 572 dma-buf-size-alignment = <32>; 573 dma-copy-alignment = <32>; 574 power-domains = <&hst_domain>; 575 zephyr,pm-device-runtime-auto; 576 interrupts = <12 0 0>; 577 interrupt-parent = <&ace_intc>; 578 status = "okay"; 579 }; 580 581 adsp_host_ipc: ace_host_ipc@73000 { 582 compatible = "intel,adsp-host-ipc"; 583 status = "okay"; 584 reg = <0x73000 0x30>; 585 interrupts = <0 0 0>; 586 interrupt-parent = <&ace_intc>; 587 }; 588 589 hda_link_out: dma@79400 { 590 compatible = "intel,adsp-hda-link-out"; 591 #dma-cells = <1>; 592 reg = <0x00079400 0x40>; 593 dma-channels = <9>; 594 dma-buf-addr-alignment = <128>; 595 dma-buf-size-alignment = <32>; 596 dma-copy-alignment = <32>; 597 power-domains = <&hub_ulp_domain>; 598 zephyr,pm-device-runtime-auto; 599 status = "okay"; 600 }; 601 602 hda_link_in: dma@79800 { 603 compatible = "intel,adsp-hda-link-in"; 604 #dma-cells = <1>; 605 reg = <0x00079800 0x40>; 606 dma-channels = <11>; 607 dma-buf-addr-alignment = <128>; 608 dma-buf-size-alignment = <32>; 609 dma-copy-alignment = <32>; 610 power-domains = <&hub_ulp_domain>; 611 zephyr,pm-device-runtime-auto; 612 status = "okay"; 613 }; 614 615 /* This is actually an array of per-core designware 616 * controllers, but the special setup and extra 617 * masking layer makes it easier for MTL to handle 618 * this internally. 619 */ 620 ace_intc: ace_intc@94000 { 621 compatible = "intel,ace-intc"; 622 reg = <0x94000 0xc00>; 623 interrupt-controller; 624 #interrupt-cells = <3>; 625 interrupts = <4 0 0>; 626 num-irqs = <28>; 627 interrupt-parent = <&core_intc>; 628 }; 629 630 tlb: tlb@17e000 { 631 compatible = "intel,adsp-mtl-tlb"; 632 reg = <0x17e000 0x1000>; 633 paddr-size = <12>; 634 exec-bit-idx = <14>; 635 write-bit-idx= <15>; 636 }; 637 638 timer: timer { 639 compatible = "intel,adsp-timer"; 640 syscon = <&tts>; 641 }; 642 }; 643 644 hdas { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 648 hda0: hda@0 { 649 compatible = "intel,hda-dai"; 650 power-domains = <&io0_domain>; 651 zephyr,pm-device-runtime-auto; 652 status = "okay"; 653 reg = <0>; 654 }; 655 hda1: hda@1 { 656 compatible = "intel,hda-dai"; 657 power-domains = <&io0_domain>; 658 zephyr,pm-device-runtime-auto; 659 status = "okay"; 660 reg = <1>; 661 }; 662 hda2: hda@2 { 663 compatible = "intel,hda-dai"; 664 power-domains = <&io0_domain>; 665 zephyr,pm-device-runtime-auto; 666 status = "okay"; 667 reg = <2>; 668 }; 669 hda3: hda@3 { 670 compatible = "intel,hda-dai"; 671 power-domains = <&io0_domain>; 672 zephyr,pm-device-runtime-auto; 673 status = "okay"; 674 reg = <3>; 675 }; 676 hda4: hda@4 { 677 compatible = "intel,hda-dai"; 678 power-domains = <&io0_domain>; 679 zephyr,pm-device-runtime-auto; 680 status = "okay"; 681 reg = <4>; 682 }; 683 hda5: hda@5 { 684 compatible = "intel,hda-dai"; 685 power-domains = <&io0_domain>; 686 zephyr,pm-device-runtime-auto; 687 status = "okay"; 688 reg = <5>; 689 }; 690 hda6: hda@6 { 691 compatible = "intel,hda-dai"; 692 power-domains = <&io0_domain>; 693 zephyr,pm-device-runtime-auto; 694 status = "okay"; 695 reg = <6>; 696 }; 697 hda7: hda@7 { 698 compatible = "intel,hda-dai"; 699 power-domains = <&io0_domain>; 700 zephyr,pm-device-runtime-auto; 701 status = "okay"; 702 reg = <7>; 703 }; 704 hda8: hda@8 { 705 compatible = "intel,hda-dai"; 706 power-domains = <&io0_domain>; 707 zephyr,pm-device-runtime-auto; 708 status = "okay"; 709 reg = <8>; 710 }; 711 hda9: hda@9 { 712 compatible = "intel,hda-dai"; 713 power-domains = <&io0_domain>; 714 zephyr,pm-device-runtime-auto; 715 status = "okay"; 716 reg = <9>; 717 }; 718 hda10: hda@a { 719 compatible = "intel,hda-dai"; 720 power-domains = <&io0_domain>; 721 zephyr,pm-device-runtime-auto; 722 status = "okay"; 723 reg = <0x0a>; 724 }; 725 hda11: hda@b { 726 compatible = "intel,hda-dai"; 727 power-domains = <&io0_domain>; 728 zephyr,pm-device-runtime-auto; 729 status = "okay"; 730 reg = <0x0b>; 731 }; 732 hda12: hda@c { 733 compatible = "intel,hda-dai"; 734 power-domains = <&io0_domain>; 735 zephyr,pm-device-runtime-auto; 736 status = "okay"; 737 reg = <0x0c>; 738 }; 739 hda13: hda@d { 740 compatible = "intel,hda-dai"; 741 power-domains = <&io0_domain>; 742 zephyr,pm-device-runtime-auto; 743 status = "okay"; 744 reg = <0x0d>; 745 }; 746 hda14: hda@e { 747 compatible = "intel,hda-dai"; 748 power-domains = <&io0_domain>; 749 zephyr,pm-device-runtime-auto; 750 status = "okay"; 751 reg = <0x0e>; 752 }; 753 hda15: hda@f { 754 compatible = "intel,hda-dai"; 755 power-domains = <&io0_domain>; 756 zephyr,pm-device-runtime-auto; 757 status = "okay"; 758 reg = <0x0f>; 759 }; 760 hda16: hda@10 { 761 compatible = "intel,hda-dai"; 762 power-domains = <&io0_domain>; 763 zephyr,pm-device-runtime-auto; 764 status = "okay"; 765 reg = <0x10>; 766 }; 767 hda17: hda@11 { 768 compatible = "intel,hda-dai"; 769 power-domains = <&io0_domain>; 770 zephyr,pm-device-runtime-auto; 771 status = "okay"; 772 reg = <0x11>; 773 }; 774 hda18: hda@12 { 775 compatible = "intel,hda-dai"; 776 power-domains = <&io0_domain>; 777 zephyr,pm-device-runtime-auto; 778 status = "okay"; 779 reg = <0x12>; 780 }; 781 }; 782}; 783
