1/* 2 * Copyright (c) 2022 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <xtensa/xtensa.dtsi> 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "cdns,tensilica-xtensa-lx7"; 18 reg = <0>; 19 cpu-power-states = <&d0i3 &d3>; 20 i-cache-line-size = <64>; 21 d-cache-line-size = <64>; 22 }; 23 24 cpu1: cpu@1 { 25 device_type = "cpu"; 26 compatible = "cdns,tensilica-xtensa-lx7"; 27 reg = <1>; 28 cpu-power-states = <&d3>; 29 }; 30 31 cpu2: cpu@2 { 32 device_type = "cpu"; 33 compatible = "cdns,tensilica-xtensa-lx7"; 34 reg = <2>; 35 cpu-power-states = <&d3>; 36 }; 37 38 power-states { 39 d0i3: idle { 40 compatible = "zephyr,power-state"; 41 power-state-name = "runtime-idle"; 42 min-residency-us = <200>; 43 exit-latency-us = <100>; 44 }; 45 /* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force. 46 * The procedure is triggered by IPC from the HOST (SET_DX). 47 */ 48 d3: off { 49 compatible = "zephyr,power-state"; 50 power-state-name = "soft-off"; 51 min-residency-us = <0>; 52 exit-latency-us = <0>; 53 status = "disabled"; 54 }; 55 }; 56 }; 57 58 sram0: memory@a0020000 { 59 device_type = "memory"; 60 compatible = "mmio-sram"; 61 reg = <0xa0020000 DT_SIZE_K(2816)>; 62 }; 63 64 sram0virtual: virtualmemory@a0020000 { 65 device_type = "memory"; 66 compatible = "mmio-sram"; 67 reg = <0xa0020000 DT_SIZE_K(8192)>; 68 }; 69 70 sram1: memory@a0000000 { 71 device_type = "memory"; 72 compatible = "mmio-sram"; 73 reg = <0xa0000000 DT_SIZE_K(64)>; 74 }; 75 76 sysclk: system-clock { 77 compatible = "fixed-clock"; 78 clock-frequency = <38400000>; 79 #clock-cells = <0>; 80 }; 81 82 clkctl: clkctl { 83 compatible = "intel,adsp-shim-clkctl"; 84 adsp-clkctl-clk-wovcro = <0>; 85 adsp-clkctl-clk-ipll = <1>; 86 adsp-clkctl-freq-enc = <0xc 0x4>; 87 adsp-clkctl-freq-mask = <0x0 0x0>; 88 adsp-clkctl-freq-default = <1>; 89 adsp-clkctl-freq-lowest = <0>; 90 wovcro-supported; 91 }; 92 93 audioclk: audio-clock { 94 compatible = "fixed-clock"; 95 clock-frequency = <24576000>; 96 #clock-cells = <0>; 97 }; 98 99 pllclk: pll-clock { 100 compatible = "fixed-clock"; 101 clock-frequency = <96000000>; 102 #clock-cells = <0>; 103 }; 104 105 IMR1: memory@A1000000 { 106 compatible = "intel,adsp-imr"; 107 reg = <0xA1000000 DT_SIZE_M(16)>; 108 block-size = <0x1000>; 109 zephyr,memory-region = "IMR1"; 110 }; 111 112 soc { 113 114 l1ccap: l1ccap@1fe80080 { 115 compatible = "intel,adsp-l1ccap"; 116 reg = <0x1fe80080 0x4>; 117 }; 118 119 l1ccfg: l1ccfg@1fe80084 { 120 compatible = "intel,adsp-l1ccfg"; 121 reg = <0x1fe80084 0x4>; 122 }; 123 124 l1pcfg: l1pcfg@1fe80088 { 125 compatible = "intel,adsp-l1pcfg"; 126 reg = <0x1fe80088 0x4>; 127 }; 128 129 hsbcap: hsbcap@71d00 { 130 compatible = "intel,adsp-hsbcap"; 131 reg = <0x71d00 0x4>; 132 }; 133 134 lsbpm: lsbpm@71d80 { 135 compatible = "intel,adsp-lsbpm"; 136 reg = <0x71d80 0x0008>; 137 }; 138 139 hsbpm: hsbpm@17a800 { 140 compatible = "intel,adsp-hsbpm"; 141 reg = <0x17a800 0x0008>; 142 }; 143 144 core_intc: core_intc@0 { 145 compatible = "cdns,xtensa-core-intc"; 146 reg = <0x00 0x400>; 147 interrupt-controller; 148 #interrupt-cells = <3>; 149 }; 150 151 dmic0: dmic0@10000 { 152 compatible = "intel,dai-dmic"; 153 reg = <0x10000 0x8000>; 154 shim = <0xC000>; 155 fifo = <0x0008>; 156 interrupts = <0x08 0 0>; 157 interrupt-parent = <&ace_intc>; 158 power-domains = <&hub_ulp_domain>; 159 zephyr,pm-device-runtime-auto; 160 }; 161 162 dmic1: dmic1@10000 { 163 compatible = "intel,dai-dmic"; 164 reg = <0x10000 0x8000>; 165 shim = <0xC000>; 166 fifo = <0x0108>; 167 interrupts = <0x09 0 0>; 168 interrupt-parent = <&ace_intc>; 169 power-domains = <&hub_ulp_domain>; 170 zephyr,pm-device-runtime-auto; 171 }; 172 173 /* 174 * FIXME this is modeling individual alh channels/instances 175 * with node labels, which has problems. A better representation 176 * is discussed here: 177 * 178 * https://github.com/zephyrproject-rtos/zephyr/pull/50287#discussion_r974591009 179 * 180 * The hardware actually supports 16 ALH streams/FIFOs. Below description does 181 * not fully represent hardware capabilities and is expected to be modified. 182 */ 183 alh0: alh0@24400 { 184 compatible = "intel,alh-dai"; 185 reg = <0x00024400 0x00024600>; 186 status = "okay"; 187 }; 188 189 alh1: alh1@24400 { 190 compatible = "intel,alh-dai"; 191 reg = <0x00024400 0x00024600>; 192 status = "okay"; 193 }; 194 195 alh2: alh2@24400 { 196 compatible = "intel,alh-dai"; 197 reg = <0x00024400 0x00024600>; 198 status = "okay"; 199 }; 200 201 alh3: alh3@24400 { 202 compatible = "intel,alh-dai"; 203 reg = <0x00024400 0x00024600>; 204 status = "okay"; 205 }; 206 207 alh4: alh4@24400 { 208 compatible = "intel,alh-dai"; 209 reg = <0x00024400 0x00024600>; 210 status = "okay"; 211 }; 212 213 alh5: alh5@24400 { 214 compatible = "intel,alh-dai"; 215 reg = <0x00024400 0x00024600>; 216 status = "okay"; 217 }; 218 219 alh6: alh6@24400 { 220 compatible = "intel,alh-dai"; 221 reg = <0x00024400 0x00024600>; 222 status = "okay"; 223 }; 224 225 alh7: alh7@24400 { 226 compatible = "intel,alh-dai"; 227 reg = <0x00024400 0x00024600>; 228 status = "okay"; 229 }; 230 231 alh8: alh8@24400 { 232 compatible = "intel,alh-dai"; 233 reg = <0x00024400 0x00024600>; 234 status = "okay"; 235 }; 236 237 alh9: alh9@24400 { 238 compatible = "intel,alh-dai"; 239 reg = <0x00024400 0x00024600>; 240 status = "okay"; 241 }; 242 243 alh10: alh10@24400 { 244 compatible = "intel,alh-dai"; 245 reg = <0x00024400 0x00024600>; 246 status = "okay"; 247 }; 248 249 alh11: alh11@24400 { 250 compatible = "intel,alh-dai"; 251 reg = <0x00024400 0x00024600>; 252 status = "okay"; 253 }; 254 255 alh12: alh12@24400 { 256 compatible = "intel,alh-dai"; 257 reg = <0x00024400 0x00024600>; 258 status = "okay"; 259 }; 260 261 alh13: alh13@24400 { 262 compatible = "intel,alh-dai"; 263 reg = <0x00024400 0x00024600>; 264 status = "okay"; 265 }; 266 267 alh14: alh14@24400 { 268 compatible = "intel,alh-dai"; 269 reg = <0x00024400 0x00024600>; 270 status = "okay"; 271 }; 272 273 alh15: alh15@24400 { 274 compatible = "intel,alh-dai"; 275 reg = <0x00024400 0x00024600>; 276 status = "okay"; 277 }; 278 279 sspbase: ssp_base@28800 { 280 compatible = "intel,ssp-sspbase"; 281 reg = <0x28800 0x1000>; 282 }; 283 284 ssp0: ssp@28000 { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 compatible = "intel,ssp"; 288 reg = <0x00028000 0x1000 289 0x00079C00 0x200>; 290 interrupts = <0x00 0 0>; 291 interrupt-parent = <&ace_intc>; 292 dmas = <&lpgpdma0 2 293 &lpgpdma0 3>; 294 dma-names = "tx", "rx"; 295 ssp-index = <0>; 296 status = "okay"; 297 298 ssp00: ssp@0 { 299 compatible = "intel,ssp-dai"; 300 power-domains = <&io0_domain>; 301 zephyr,pm-device-runtime-auto; 302 status = "okay"; 303 reg = <0x0>; 304 }; 305 }; 306 307 ssp1: ssp@29000 { 308 compatible = "intel,ssp"; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 reg = <0x00029000 0x1000 312 0x00079C00 0x200>; 313 interrupts = <0x01 0 0>; 314 interrupt-parent = <&ace_intc>; 315 dmas = <&lpgpdma0 4 316 &lpgpdma0 5>; 317 dma-names = "tx", "rx"; 318 ssp-index = <1>; 319 status = "okay"; 320 321 ssp10: ssp@10 { 322 compatible = "intel,ssp-dai"; 323 power-domains = <&io0_domain>; 324 zephyr,pm-device-runtime-auto; 325 status = "okay"; 326 reg = <0x10>; 327 }; 328 }; 329 330 ssp2: ssp@2a000 { 331 compatible = "intel,ssp"; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 reg = <0x0002a000 0x1000 335 0x00079C00 0x200>; 336 interrupts = <0x02 0 0>; 337 interrupt-parent = <&ace_intc>; 338 dmas = <&lpgpdma0 6 339 &lpgpdma0 7>; 340 dma-names = "tx", "rx"; 341 ssp-index = <2>; 342 status = "okay"; 343 344 ssp20: ssp@20 { 345 compatible = "intel,ssp-dai"; 346 power-domains = <&io0_domain>; 347 zephyr,pm-device-runtime-auto; 348 status = "okay"; 349 reg = <0x20>; 350 }; 351 }; 352 353 mem_window0: mem_window@70200 { 354 compatible = "intel,adsp-mem-window"; 355 reg = <0x70200 0x8>; 356 offset = <0x4000>; 357 memory = <&sram0>; 358 initialize; 359 read-only; 360 }; 361 362 mem_window1: mem_window@70208 { 363 compatible = "intel,adsp-mem-window"; 364 reg = <0x70208 0x8>; 365 memory = <&sram0>; 366 }; 367 368 mem_window2: mem_window@70210 { 369 compatible = "intel,adsp-mem-window"; 370 reg = <0x70210 0x8>; 371 memory = <&sram0>; 372 }; 373 374 mem_window3: mem_window@70218 { 375 compatible = "intel,adsp-mem-window"; 376 reg = <0x70218 0x8>; 377 memory = <&sram0>; 378 read-only; 379 }; 380 381 adsp_idc: ace_idc@70400 { 382 compatible = "intel,adsp-idc"; 383 reg = <0x70400 0x0400>; 384 interrupts = <24 0 0>; 385 interrupt-parent = <&ace_intc>; 386 }; 387 388 dfpmcch: dfpmcch@71ac0 { 389 compatible = "intel,adsp-dfpmcch"; 390 reg = <0x00071ac0 0x40>; 391 }; 392 393 dfpmccu: dfpmccu@71b00 { 394 compatible = "intel,adsp-dfpmccu"; 395 reg = <0x71b00 0x100>; 396 397 hub_ulp_domain: hub_ulp_domain { 398 compatible = "intel,adsp-power-domain"; 399 bit-position = <15>; 400 #power-domain-cells = <0>; 401 }; 402 ml1_domain: ml1_domain { 403 compatible = "intel,adsp-power-domain"; 404 bit-position = <13>; 405 #power-domain-cells = <0>; 406 }; 407 ml0_domain: ml0_domain { 408 compatible = "intel,adsp-power-domain"; 409 bit-position = <12>; 410 #power-domain-cells = <0>; 411 }; 412 io3_domain: io3_domain { 413 compatible = "intel,adsp-power-domain"; 414 bit-position = <11>; 415 #power-domain-cells = <0>; 416 }; 417 io2_domain: io2_domain { 418 compatible = "intel,adsp-power-domain"; 419 bit-position = <10>; 420 #power-domain-cells = <0>; 421 }; 422 io1_domain: io1_domain { 423 compatible = "intel,adsp-power-domain"; 424 bit-position = <9>; 425 #power-domain-cells = <0>; 426 }; 427 io0_domain: io0_domain { 428 compatible = "intel,adsp-power-domain"; 429 bit-position = <8>; 430 #power-domain-cells = <0>; 431 }; 432 hub_hp_domain: hub_hp_domain { 433 compatible = "intel,adsp-power-domain"; 434 bit-position = <6>; 435 #power-domain-cells = <0>; 436 }; 437 hst_domain: hst_domain { 438 compatible = "intel,adsp-power-domain"; 439 bit-position = <4>; 440 #power-domain-cells = <0>; 441 }; 442 }; 443 444 ace_comm_widget: ace_comm_widget@71c00 { 445 compatible = "intel,adsp-communication-widget"; 446 reg = <0x00071c00 0x100>; 447 interrupts = <0x19 0 0>; 448 interrupt-parent = <&ace_intc>; 449 status = "okay"; 450 }; 451 452 shim: shim@71f00 { 453 compatible = "intel,adsp-shim"; 454 reg = <0x71f00 0x100>; 455 }; 456 457 tts: tts@72000 { 458 compatible = "intel,adsp-tts"; 459 reg = <0x72000 0x70>; 460 status = "okay"; 461 }; 462 463 ace_rtc_counter: ace_rtc_counter@72008 { 464 compatible = "intel,ace-rtc-counter"; 465 reg = <0x72008 0x0064>; 466 }; 467 468 ace_timestamp: ace_timestamp@72040 { 469 compatible = "intel,ace-timestamp"; 470 reg = <0x72040 0x0032>; 471 }; 472 473 ace_art_counter: ace_art_counter@72058 { 474 compatible = "intel,ace-art-counter"; 475 reg = <0x72058 0x0064>; 476 }; 477 478 hda_link_out: dma@72400 { 479 compatible = "intel,adsp-hda-link-out"; 480 #dma-cells = <1>; 481 reg = <0x00072400 0x20>; 482 dma-channels = <9>; 483 dma-buf-addr-alignment = <128>; 484 dma-buf-size-alignment = <32>; 485 dma-copy-alignment = <16>; 486 power-domains = <&hub_ulp_domain>; 487 zephyr,pm-device-runtime-auto; 488 status = "okay"; 489 }; 490 491 hda_link_in: dma@72600 { 492 compatible = "intel,adsp-hda-link-in"; 493 #dma-cells = <1>; 494 reg = <0x00072600 0x20>; 495 dma-channels = <10>; 496 dma-buf-addr-alignment = <128>; 497 dma-buf-size-alignment = <32>; 498 dma-copy-alignment = <16>; 499 power-domains = <&hub_ulp_domain>; 500 zephyr,pm-device-runtime-auto; 501 status = "okay"; 502 }; 503 504 hda_host_out: dma@72800 { 505 compatible = "intel,adsp-hda-host-out"; 506 #dma-cells = <1>; 507 reg = <0x00072800 0x40>; 508 dma-channels = <9>; 509 dma-buf-addr-alignment = <128>; 510 dma-buf-size-alignment = <32>; 511 dma-copy-alignment = <16>; 512 power-domains = <&hst_domain>; 513 zephyr,pm-device-runtime-auto; 514 interrupts = <13 0 0>; 515 interrupt-parent = <&ace_intc>; 516 status = "okay"; 517 }; 518 519 hda_host_in: dma@72c00 { 520 compatible = "intel,adsp-hda-host-in"; 521 #dma-cells = <1>; 522 reg = <0x00072c00 0x40>; 523 dma-channels = <10>; 524 dma-buf-addr-alignment = <128>; 525 dma-buf-size-alignment = <32>; 526 dma-copy-alignment = <16>; 527 power-domains = <&hst_domain>; 528 zephyr,pm-device-runtime-auto; 529 interrupts = <12 0 0>; 530 interrupt-parent = <&ace_intc>; 531 status = "okay"; 532 }; 533 534 adsp_host_ipc: ace_host_ipc@73000 { 535 compatible = "intel,adsp-host-ipc"; 536 status = "okay"; 537 reg = <0x73000 0x30>; 538 interrupts = <0 0 0>; 539 interrupt-parent = <&ace_intc>; 540 }; 541 542 /* This is actually an array of per-core designware 543 * controllers, but the special setup and extra 544 * masking layer makes it easier for MTL to handle 545 * this internally. 546 */ 547 ace_intc: ace_intc@7ac00 { 548 compatible = "intel,ace-intc"; 549 reg = <0x7ac00 0xc00>; 550 interrupt-controller; 551 #interrupt-cells = <3>; 552 interrupts = <4 0 0>; 553 num-irqs = <28>; 554 interrupt-parent = <&core_intc>; 555 }; 556 557 lpgpdma0: dma@7c000 { 558 compatible = "intel,adsp-gpdma"; 559 #dma-cells = <1>; 560 reg = <0x0007c000 0x1000>; 561 shim = <0x0007c800 0x1000>; 562 interrupts = <17 0 0>; 563 interrupt-parent = <&ace_intc>; 564 dma-buf-size-alignment = <4>; 565 dma-copy-alignment = <4>; 566 status = "okay"; 567 power-domains = <&hub_ulp_domain>; 568 zephyr,pm-device-runtime-auto; 569 }; 570 571 lpgpdma1: dma@7d000 { 572 compatible = "intel,adsp-gpdma"; 573 #dma-cells = <1>; 574 reg = <0x0007d000 0x1000>; 575 shim = <0x0007d800 0x1000>; 576 interrupts = <0x20 0 0>; 577 interrupt-parent = <&core_intc>; 578 dma-buf-size-alignment = <4>; 579 dma-copy-alignment = <4>; 580 status = "okay"; 581 power-domains = <&io0_domain>; 582 zephyr,pm-device-runtime-auto; 583 }; 584 585 lpgpdma2: dma@7e000 { 586 compatible = "intel,adsp-gpdma"; 587 #dma-cells = <1>; 588 reg = <0x0007e000 0x1000>; 589 shim = <0x0007e800 0x1000>; 590 interrupts = <0x25 0 0>; 591 interrupt-parent = <&core_intc>; 592 dma-buf-size-alignment = <4>; 593 dma-copy-alignment = <4>; 594 power-domains = <&io0_domain>; 595 status = "okay"; 596 zephyr,pm-device-runtime-auto; 597 }; 598 599 sha: adsp-sha@17df00 { 600 compatible = "intel,adsp-sha"; 601 reg = <0x17df00 0xd0>; 602 }; 603 604 tlb: tlb@17e000 { 605 compatible = "intel,adsp-mtl-tlb"; 606 reg = <0x17e000 0x1000>; 607 paddr-size = <12>; 608 exec-bit-idx = <14>; 609 write-bit-idx= <15>; 610 }; 611 612 timer: timer { 613 compatible = "intel,adsp-timer"; 614 syscon = <&tts>; 615 }; 616 }; 617 618 hdas { 619 #address-cells = <1>; 620 #size-cells = <0>; 621 622 hda0: hda@0 { 623 compatible = "intel,hda-dai"; 624 power-domains = <&io0_domain>; 625 zephyr,pm-device-runtime-auto; 626 status = "okay"; 627 reg = <0>; 628 }; 629 hda1: hda@1 { 630 compatible = "intel,hda-dai"; 631 power-domains = <&io0_domain>; 632 zephyr,pm-device-runtime-auto; 633 status = "okay"; 634 reg = <1>; 635 }; 636 hda2: hda@2 { 637 compatible = "intel,hda-dai"; 638 power-domains = <&io0_domain>; 639 zephyr,pm-device-runtime-auto; 640 status = "okay"; 641 reg = <2>; 642 }; 643 hda3: hda@3 { 644 compatible = "intel,hda-dai"; 645 power-domains = <&io0_domain>; 646 zephyr,pm-device-runtime-auto; 647 status = "okay"; 648 reg = <3>; 649 }; 650 hda4: hda@4 { 651 compatible = "intel,hda-dai"; 652 power-domains = <&io0_domain>; 653 zephyr,pm-device-runtime-auto; 654 status = "okay"; 655 reg = <4>; 656 }; 657 hda5: hda@5 { 658 compatible = "intel,hda-dai"; 659 power-domains = <&io0_domain>; 660 zephyr,pm-device-runtime-auto; 661 status = "okay"; 662 reg = <5>; 663 }; 664 hda6: hda@6 { 665 compatible = "intel,hda-dai"; 666 power-domains = <&io0_domain>; 667 zephyr,pm-device-runtime-auto; 668 status = "okay"; 669 reg = <6>; 670 }; 671 hda7: hda@7 { 672 compatible = "intel,hda-dai"; 673 power-domains = <&io0_domain>; 674 zephyr,pm-device-runtime-auto; 675 status = "okay"; 676 reg = <7>; 677 }; 678 hda8: hda@8 { 679 compatible = "intel,hda-dai"; 680 power-domains = <&io0_domain>; 681 zephyr,pm-device-runtime-auto; 682 status = "okay"; 683 reg = <8>; 684 }; 685 hda9: hda@9 { 686 compatible = "intel,hda-dai"; 687 power-domains = <&io0_domain>; 688 zephyr,pm-device-runtime-auto; 689 status = "okay"; 690 reg = <9>; 691 }; 692 hda10: hda@a { 693 compatible = "intel,hda-dai"; 694 power-domains = <&io0_domain>; 695 zephyr,pm-device-runtime-auto; 696 status = "okay"; 697 reg = <0x0a>; 698 }; 699 hda11: hda@b { 700 compatible = "intel,hda-dai"; 701 power-domains = <&io0_domain>; 702 zephyr,pm-device-runtime-auto; 703 status = "okay"; 704 reg = <0x0b>; 705 }; 706 hda12: hda@c { 707 compatible = "intel,hda-dai"; 708 power-domains = <&io0_domain>; 709 zephyr,pm-device-runtime-auto; 710 status = "okay"; 711 reg = <0x0c>; 712 }; 713 hda13: hda@d { 714 compatible = "intel,hda-dai"; 715 power-domains = <&io0_domain>; 716 zephyr,pm-device-runtime-auto; 717 status = "okay"; 718 reg = <0x0d>; 719 }; 720 hda14: hda@e { 721 compatible = "intel,hda-dai"; 722 power-domains = <&io0_domain>; 723 zephyr,pm-device-runtime-auto; 724 status = "okay"; 725 reg = <0x0e>; 726 }; 727 hda15: hda@f { 728 compatible = "intel,hda-dai"; 729 power-domains = <&io0_domain>; 730 zephyr,pm-device-runtime-auto; 731 status = "okay"; 732 reg = <0x0f>; 733 }; 734 hda16: hda@10 { 735 compatible = "intel,hda-dai"; 736 power-domains = <&io0_domain>; 737 zephyr,pm-device-runtime-auto; 738 status = "okay"; 739 reg = <0x10>; 740 }; 741 hda17: hda@11 { 742 compatible = "intel,hda-dai"; 743 power-domains = <&io0_domain>; 744 zephyr,pm-device-runtime-auto; 745 status = "okay"; 746 reg = <0x11>; 747 }; 748 hda18: hda@12 { 749 compatible = "intel,hda-dai"; 750 power-domains = <&io0_domain>; 751 zephyr,pm-device-runtime-auto; 752 status = "okay"; 753 reg = <0x12>; 754 }; 755 }; 756}; 757
