1/* 2 * Copyright (c) 2024 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <xtensa/xtensa.dtsi> 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "cdns,tensilica-xtensa-lx7"; 18 reg = <0>; 19 cpu-power-states = <&d0i3 &d3>; 20 i-cache-line-size = <64>; 21 d-cache-line-size = <64>; 22 }; 23 24 cpu1: cpu@1 { 25 device_type = "cpu"; 26 compatible = "cdns,tensilica-xtensa-lx7"; 27 reg = <1>; 28 cpu-power-states = <&d0i3 &d3>; 29 }; 30 31 cpu2: cpu@2 { 32 device_type = "cpu"; 33 compatible = "cdns,tensilica-xtensa-lx7"; 34 reg = <2>; 35 cpu-power-states = <&d0i3 &d3>; 36 }; 37 38 cpu3: cpu@3 { 39 device_type = "cpu"; 40 compatible = "cdns,tensilica-xtensa-lx7"; 41 reg = <3>; 42 cpu-power-states = <&d0i3 &d3>; 43 }; 44 45 cpu4: cpu@4 { 46 device_type = "cpu"; 47 compatible = "cdns,tensilica-xtensa-lx7"; 48 reg = <4>; 49 cpu-power-states = <&d0i3 &d3>; 50 }; 51 }; 52 53 power-states { 54 d0i3: idle { 55 compatible = "zephyr,power-state"; 56 power-state-name = "runtime-idle"; 57 min-residency-us = <200>; 58 exit-latency-us = <100>; 59 }; 60 /* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force. 61 * The procedure is triggered by IPC from the HOST (SET_DX). 62 */ 63 d3: off { 64 compatible = "zephyr,power-state"; 65 power-state-name = "soft-off"; 66 min-residency-us = <0>; 67 exit-latency-us = <0>; 68 status = "disabled"; 69 }; 70 }; 71 72 sram0: memory@a0020000 { 73 device_type = "memory"; 74 compatible = "mmio-sram"; 75 reg = <0xa0020000 DT_SIZE_K(4608)>; 76 }; 77 78 sram0virtual: virtualmemory@a0020000 { 79 device_type = "memory"; 80 compatible = "mmio-sram"; 81 reg = <0xa0020000 DT_SIZE_K(8192)>; 82 }; 83 84 sram1: memory@a0000000 { 85 device_type = "memory"; 86 compatible = "mmio-sram"; 87 reg = <0xa0000000 DT_SIZE_K(64)>; 88 }; 89 90 sysclk: system-clock { 91 compatible = "fixed-clock"; 92 clock-frequency = <38400000>; 93 #clock-cells = <0>; 94 }; 95 96 clkctl: clkctl { 97 compatible = "intel,adsp-shim-clkctl"; 98 adsp-clkctl-clk-wovcro = <0>; 99 adsp-clkctl-clk-ipll = <1>; 100 adsp-clkctl-freq-enc = <0xc 0x4>; 101 adsp-clkctl-freq-mask = <0x0 0x0>; 102 adsp-clkctl-freq-default = <1>; 103 adsp-clkctl-freq-lowest = <0>; 104 wovcro-supported; 105 }; 106 107 audioclk: audio-clock { 108 compatible = "fixed-clock"; 109 clock-frequency = <24576000>; 110 #clock-cells = <0>; 111 }; 112 113 pllclk: pll-clock { 114 compatible = "fixed-clock"; 115 clock-frequency = <96000000>; 116 #clock-cells = <0>; 117 }; 118 119 IMR1: memory@A1000000 { 120 compatible = "intel,adsp-imr"; 121 reg = <0xA1000000 DT_SIZE_M(16)>; 122 block-size = <0x1000>; 123 zephyr,memory-region = "IMR1"; 124 }; 125 126 soc { 127 l1ccap: l1ccap@3fe80080 { 128 compatible = "intel,adsp-l1ccap"; 129 reg = <0x3fe80080 0x4>; 130 }; 131 132 l1ccfg: l1ccfg@3fe80084 { 133 compatible = "intel,adsp-l1ccfg"; 134 reg = <0x3fe80084 0x4>; 135 }; 136 137 l1pcfg: l1pcfg@3fe80088 { 138 compatible = "intel,adsp-l1pcfg"; 139 reg = <0x3fe80088 0x4>; 140 }; 141 142 lsbpm: lsbpm@71d80 { 143 compatible = "intel,adsp-lsbpm"; 144 reg = <0x71d80 0x0008>; 145 }; 146 147 hsbpm: hsbpm@17a800 { 148 compatible = "intel,adsp-hsbpm"; 149 reg = <0x17a800 0x0008>; 150 }; 151 152 core_intc: core_intc@0 { 153 compatible = "cdns,xtensa-core-intc"; 154 reg = <0x00 0x400>; 155 interrupt-controller; 156 #interrupt-cells = <3>; 157 }; 158 159 hdamlddmic: hdamlddmic@cc0 { 160 compatible = "intel,adsp-hda-dmic-cap"; 161 reg = <0xcc0 0x40>; 162 status = "okay"; 163 }; 164 165 dmic0: dai-dmic0@10100 { 166 compatible = "intel,dai-dmic"; 167 reg = <0x10100 0x8000>; 168 shim = <0x10000>; 169 fifo = <0x0008>; 170 interrupts = <0x08 0 0>; 171 interrupt-parent = <&ace_intc>; 172 power-domains = <&hub_ulp_domain>; 173 zephyr,pm-device-runtime-auto; 174 }; 175 176 dmic1: dai-dmic1@10100 { 177 compatible = "intel,dai-dmic"; 178 reg = <0x10100 0x8000>; 179 shim = <0x10000>; 180 fifo = <0x0108>; 181 interrupts = <0x08 0 0>; 182 interrupt-parent = <&ace_intc>; 183 power-domains = <&hub_ulp_domain>; 184 zephyr,pm-device-runtime-auto; 185 }; 186 187 dmicvss: dmicvss@16000 { 188 compatible = "intel,adsp-dmic-vss"; 189 reg = <0x16000 0x2000>; 190 status = "okay"; 191 }; 192 193 sspbase: ssp_base@28000 { 194 compatible = "intel,ssp-sspbase"; 195 reg = <0x28000 0x1000>; 196 }; 197 198 hdamlssp: hdamlssp@d00 { 199 compatible = "intel,adsp-hda-ssp-cap"; 200 reg = <0xD00 0x40>; 201 status = "okay"; 202 }; 203 204 ssp0: ssp@28100 { 205 compatible = "intel,ssp"; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 reg = <0x00028100 0x1000 209 0x00079C00 0x200>; 210 i2svss = <0x00028C00 0x1000>; 211 interrupts = <0x00 0 0>; 212 interrupt-parent = <&ace_intc>; 213 dmas = <&hda_link_out 1 214 &hda_link_in 1>; 215 dma-names = "tx", "rx"; 216 ssp-index = <0>; 217 status = "okay"; 218 219 ssp00: ssp@0 { 220 compatible = "intel,ssp-dai"; 221 power-domains = <&io0_domain>; 222 zephyr,pm-device-runtime-auto; 223 reg = <0x0>; 224 status = "okay"; 225 }; 226 227 ssp01: ssp@1 { 228 compatible = "intel,ssp-dai"; 229 power-domains = <&io0_domain>; 230 zephyr,pm-device-runtime-auto; 231 reg = <0x1>; 232 status = "okay"; 233 }; 234 235 ssp02: ssp@2 { 236 compatible = "intel,ssp-dai"; 237 power-domains = <&io0_domain>; 238 zephyr,pm-device-runtime-auto; 239 reg = <0x2>; 240 status = "okay"; 241 }; 242 243 ssp03: ssp@3 { 244 compatible = "intel,ssp-dai"; 245 power-domains = <&io0_domain>; 246 zephyr,pm-device-runtime-auto; 247 reg = <0x3>; 248 status = "okay"; 249 }; 250 251 ssp04: ssp@4 { 252 compatible = "intel,ssp-dai"; 253 power-domains = <&io0_domain>; 254 zephyr,pm-device-runtime-auto; 255 reg = <0x4>; 256 status = "okay"; 257 }; 258 259 ssp05: ssp@5 { 260 compatible = "intel,ssp-dai"; 261 power-domains = <&io0_domain>; 262 zephyr,pm-device-runtime-auto; 263 reg = <0x5>; 264 status = "okay"; 265 }; 266 267 ssp06: ssp@6 { 268 compatible = "intel,ssp-dai"; 269 power-domains = <&io0_domain>; 270 zephyr,pm-device-runtime-auto; 271 reg = <0x6>; 272 status = "okay"; 273 }; 274 275 ssp07: ssp@7 { 276 compatible = "intel,ssp-dai"; 277 power-domains = <&io0_domain>; 278 zephyr,pm-device-runtime-auto; 279 reg = <0x7>; 280 status = "okay"; 281 }; 282 }; 283 284 ssp1: ssp@29100 { 285 compatible = "intel,ssp"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 reg = <0x00029100 0x1000 289 0x00079C00 0x200>; 290 i2svss = <0x00029C00 0x1000>; 291 interrupts = <0x01 0 0>; 292 interrupt-parent = <&ace_intc>; 293 dmas = <&hda_link_out 2 294 &hda_link_in 2>; 295 dma-names = "tx", "rx"; 296 ssp-index = <1>; 297 status = "okay"; 298 299 ssp10: ssp@10 { 300 compatible = "intel,ssp-dai"; 301 power-domains = <&io0_domain>; 302 zephyr,pm-device-runtime-auto; 303 reg = <0x10>; 304 status = "okay"; 305 }; 306 307 ssp11: ssp@11 { 308 compatible = "intel,ssp-dai"; 309 power-domains = <&io0_domain>; 310 zephyr,pm-device-runtime-auto; 311 reg = <0x11>; 312 status = "okay"; 313 }; 314 315 ssp12: ssp@12 { 316 compatible = "intel,ssp-dai"; 317 power-domains = <&io0_domain>; 318 zephyr,pm-device-runtime-auto; 319 reg = <0x12>; 320 status = "okay"; 321 }; 322 323 ssp13: ssp@13 { 324 compatible = "intel,ssp-dai"; 325 power-domains = <&io0_domain>; 326 zephyr,pm-device-runtime-auto; 327 reg = <0x13>; 328 status = "okay"; 329 }; 330 331 ssp14: ssp@14 { 332 compatible = "intel,ssp-dai"; 333 power-domains = <&io0_domain>; 334 zephyr,pm-device-runtime-auto; 335 reg = <0x14>; 336 status = "okay"; 337 }; 338 339 ssp15: ssp@15 { 340 compatible = "intel,ssp-dai"; 341 power-domains = <&io0_domain>; 342 zephyr,pm-device-runtime-auto; 343 reg = <0x15>; 344 status = "okay"; 345 }; 346 347 ssp16: ssp@16 { 348 compatible = "intel,ssp-dai"; 349 power-domains = <&io0_domain>; 350 zephyr,pm-device-runtime-auto; 351 reg = <0x16>; 352 status = "okay"; 353 }; 354 355 ssp17: ssp@17 { 356 compatible = "intel,ssp-dai"; 357 power-domains = <&io0_domain>; 358 zephyr,pm-device-runtime-auto; 359 reg = <0x17>; 360 status = "okay"; 361 }; 362 }; 363 364 ssp2: ssp@2a100 { 365 compatible = "intel,ssp"; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 reg = <0x0002a100 0x1000 369 0x00079C00 0x200>; 370 i2svss = <0x0002AC00 0x1000>; 371 interrupts = <0x02 0 0>; 372 interrupt-parent = <&ace_intc>; 373 dmas = <&hda_link_out 3 374 &hda_link_in 3>; 375 dma-names = "tx", "rx"; 376 ssp-index = <2>; 377 status = "okay"; 378 379 ssp20: ssp@20 { 380 compatible = "intel,ssp-dai"; 381 power-domains = <&io0_domain>; 382 zephyr,pm-device-runtime-auto; 383 reg = <0x20>; 384 status = "okay"; 385 }; 386 387 ssp21: ssp@21 { 388 compatible = "intel,ssp-dai"; 389 power-domains = <&io0_domain>; 390 zephyr,pm-device-runtime-auto; 391 reg = <0x21>; 392 status = "okay"; 393 }; 394 395 ssp22: ssp@22 { 396 compatible = "intel,ssp-dai"; 397 power-domains = <&io0_domain>; 398 zephyr,pm-device-runtime-auto; 399 reg = <0x22>; 400 status = "okay"; 401 }; 402 403 ssp23: ssp@23 { 404 compatible = "intel,ssp-dai"; 405 power-domains = <&io0_domain>; 406 zephyr,pm-device-runtime-auto; 407 reg = <0x23>; 408 status = "okay"; 409 }; 410 411 ssp24: ssp@24 { 412 compatible = "intel,ssp-dai"; 413 power-domains = <&io0_domain>; 414 zephyr,pm-device-runtime-auto; 415 reg = <0x24>; 416 status = "okay"; 417 }; 418 419 ssp25: ssp@25 { 420 compatible = "intel,ssp-dai"; 421 power-domains = <&io0_domain>; 422 zephyr,pm-device-runtime-auto; 423 reg = <0x25>; 424 status = "okay"; 425 }; 426 427 ssp26: ssp@26 { 428 compatible = "intel,ssp-dai"; 429 power-domains = <&io0_domain>; 430 zephyr,pm-device-runtime-auto; 431 reg = <0x26>; 432 status = "okay"; 433 }; 434 435 ssp27: ssp@27 { 436 compatible = "intel,ssp-dai"; 437 power-domains = <&io0_domain>; 438 zephyr,pm-device-runtime-auto; 439 reg = <0x27>; 440 status = "okay"; 441 }; 442 }; 443 444 mem_window0: mem_window@70200 { 445 compatible = "intel,adsp-mem-window"; 446 reg = <0x70200 0x8>; 447 offset = <0x4000>; 448 memory = <&sram0>; 449 initialize; 450 read-only; 451 }; 452 453 mem_window1: mem_window@70208 { 454 compatible = "intel,adsp-mem-window"; 455 reg = <0x70208 0x8>; 456 memory = <&sram0>; 457 }; 458 459 mem_window2: mem_window@70210 { 460 compatible = "intel,adsp-mem-window"; 461 reg = <0x70210 0x8>; 462 memory = <&sram0>; 463 }; 464 465 mem_window3: mem_window@70218 { 466 compatible = "intel,adsp-mem-window"; 467 reg = <0x70218 0x8>; 468 memory = <&sram0>; 469 read-only; 470 }; 471 472 adsp_idc: ace_idc@92000 { 473 compatible = "intel,adsp-idc"; 474 reg = <0x92000 0x0400>; 475 interrupts = <24 0 0>; 476 interrupt-parent = <&ace_intc>; 477 }; 478 479 dfpmcch: dfpmcch@71ac0 { 480 compatible = "intel,adsp-dfpmcch"; 481 reg = <0x00071ac0 0x40>; 482 }; 483 484 dfpmccu: dfpmccu@71b00 { 485 compatible = "intel,adsp-dfpmccu"; 486 reg = <0x71b00 0x100>; 487 488 hub_ulp_domain: hub_ulp_domain { 489 compatible = "intel,adsp-power-domain"; 490 bit-position = <15>; 491 #power-domain-cells = <0>; 492 }; 493 ml0_domain: ml0_domain { 494 compatible = "intel,adsp-power-domain"; 495 bit-position = <12>; 496 #power-domain-cells = <0>; 497 }; 498 io1_domain: io1_domain { 499 compatible = "intel,adsp-power-domain"; 500 bit-position = <9>; 501 #power-domain-cells = <0>; 502 }; 503 io0_domain: io0_domain { 504 compatible = "intel,adsp-power-domain"; 505 bit-position = <8>; 506 #power-domain-cells = <0>; 507 }; 508 hub_hp_domain: hub_hpp_domain { 509 compatible = "intel,adsp-power-domain"; 510 bit-position = <6>; 511 #power-domain-cells = <0>; 512 }; 513 hst_domain: hst_domain { 514 compatible = "intel,adsp-power-domain"; 515 bit-position = <5>; 516 #power-domain-cells = <0>; 517 }; 518 }; 519 520 shim: shim@71f00 { 521 compatible = "intel,cavs-shim"; 522 reg = <0x71f00 0x100>; 523 }; 524 525 tts: tts@72000 { 526 compatible = "intel,adsp-tts"; 527 reg = <0x72000 0x70>; 528 status = "okay"; 529 }; 530 531 ace_rtc_counter: ace_rtc_counter@72008 { 532 compatible = "intel,ace-rtc-counter"; 533 reg = <0x72008 0x0064>; 534 }; 535 536 ace_timestamp: ace_timestamp@72040 { 537 compatible = "intel,ace-timestamp"; 538 reg = <0x72040 0x0032>; 539 }; 540 541 ace_art_counter: ace_art_counter@72058 { 542 compatible = "intel,ace-art-counter"; 543 reg = <0x72058 0x0064>; 544 }; 545 546 hda_host_out: dma@72800 { 547 compatible = "intel,adsp-hda-host-out"; 548 #dma-cells = <1>; 549 reg = <0x00072800 0x40>; 550 dma-channels = <9>; 551 dma-buf-addr-alignment = <128>; 552 dma-buf-size-alignment = <32>; 553 dma-copy-alignment = <32>; 554 power-domains = <&hst_domain>; 555 zephyr,pm-device-runtime-auto; 556 interrupts = <13 0 0>; 557 interrupt-parent = <&ace_intc>; 558 status = "okay"; 559 }; 560 561 hda_host_in: dma@72c00 { 562 compatible = "intel,adsp-hda-host-in"; 563 #dma-cells = <1>; 564 reg = <0x00072c00 0x40>; 565 dma-channels = <11>; 566 dma-buf-addr-alignment = <128>; 567 dma-buf-size-alignment = <32>; 568 dma-copy-alignment = <32>; 569 power-domains = <&hst_domain>; 570 zephyr,pm-device-runtime-auto; 571 interrupts = <12 0 0>; 572 interrupt-parent = <&ace_intc>; 573 status = "okay"; 574 }; 575 576 adsp_host_ipc: ace_host_ipc@73000 { 577 compatible = "intel,adsp-host-ipc"; 578 status = "okay"; 579 reg = <0x73000 0x30>; 580 interrupts = <0 0 0>; 581 interrupt-parent = <&ace_intc>; 582 }; 583 584 hda_link_out: dma@79400 { 585 compatible = "intel,adsp-hda-link-out"; 586 #dma-cells = <1>; 587 reg = <0x00079400 0x40>; 588 dma-channels = <9>; 589 dma-buf-addr-alignment = <128>; 590 dma-buf-size-alignment = <32>; 591 dma-copy-alignment = <32>; 592 power-domains = <&hub_ulp_domain>; 593 zephyr,pm-device-runtime-auto; 594 status = "okay"; 595 }; 596 597 hda_link_in: dma@79800 { 598 compatible = "intel,adsp-hda-link-in"; 599 #dma-cells = <1>; 600 reg = <0x00079800 0x40>; 601 dma-channels = <11>; 602 dma-buf-addr-alignment = <128>; 603 dma-buf-size-alignment = <32>; 604 dma-copy-alignment = <32>; 605 power-domains = <&hub_ulp_domain>; 606 zephyr,pm-device-runtime-auto; 607 status = "okay"; 608 }; 609 610 /* This is actually an array of per-core designware 611 * controllers, but the special setup and extra 612 * masking layer makes it easier for MTL to handle 613 * this internally. 614 */ 615 ace_intc: ace_intc@94000 { 616 compatible = "intel,ace-intc"; 617 reg = <0x94000 0xc00>; 618 interrupt-controller; 619 #interrupt-cells = <3>; 620 interrupts = <4 0 0>; 621 num-irqs = <28>; 622 interrupt-parent = <&core_intc>; 623 }; 624 625 tlb: tlb@17e000 { 626 compatible = "intel,adsp-mtl-tlb"; 627 reg = <0x17e000 0x1000>; 628 paddr-size = <12>; 629 exec-bit-idx = <14>; 630 write-bit-idx= <15>; 631 }; 632 633 timer: timer { 634 compatible = "intel,adsp-timer"; 635 syscon = <&tts>; 636 }; 637 }; 638 639 hdas { 640 #address-cells = <1>; 641 #size-cells = <0>; 642 643 hda0: hda@0 { 644 compatible = "intel,hda-dai"; 645 power-domains = <&io0_domain>; 646 zephyr,pm-device-runtime-auto; 647 status = "okay"; 648 reg = <0>; 649 }; 650 hda1: hda@1 { 651 compatible = "intel,hda-dai"; 652 power-domains = <&io0_domain>; 653 zephyr,pm-device-runtime-auto; 654 status = "okay"; 655 reg = <1>; 656 }; 657 hda2: hda@2 { 658 compatible = "intel,hda-dai"; 659 power-domains = <&io0_domain>; 660 zephyr,pm-device-runtime-auto; 661 status = "okay"; 662 reg = <2>; 663 }; 664 hda3: hda@3 { 665 compatible = "intel,hda-dai"; 666 power-domains = <&io0_domain>; 667 zephyr,pm-device-runtime-auto; 668 status = "okay"; 669 reg = <3>; 670 }; 671 hda4: hda@4 { 672 compatible = "intel,hda-dai"; 673 power-domains = <&io0_domain>; 674 zephyr,pm-device-runtime-auto; 675 status = "okay"; 676 reg = <4>; 677 }; 678 hda5: hda@5 { 679 compatible = "intel,hda-dai"; 680 power-domains = <&io0_domain>; 681 zephyr,pm-device-runtime-auto; 682 status = "okay"; 683 reg = <5>; 684 }; 685 hda6: hda@6 { 686 compatible = "intel,hda-dai"; 687 power-domains = <&io0_domain>; 688 zephyr,pm-device-runtime-auto; 689 status = "okay"; 690 reg = <6>; 691 }; 692 hda7: hda@7 { 693 compatible = "intel,hda-dai"; 694 power-domains = <&io0_domain>; 695 zephyr,pm-device-runtime-auto; 696 status = "okay"; 697 reg = <7>; 698 }; 699 hda8: hda@8 { 700 compatible = "intel,hda-dai"; 701 power-domains = <&io0_domain>; 702 zephyr,pm-device-runtime-auto; 703 status = "okay"; 704 reg = <8>; 705 }; 706 hda9: hda@9 { 707 compatible = "intel,hda-dai"; 708 power-domains = <&io0_domain>; 709 zephyr,pm-device-runtime-auto; 710 status = "okay"; 711 reg = <9>; 712 }; 713 hda10: hda@a { 714 compatible = "intel,hda-dai"; 715 power-domains = <&io0_domain>; 716 zephyr,pm-device-runtime-auto; 717 status = "okay"; 718 reg = <0x0a>; 719 }; 720 hda11: hda@b { 721 compatible = "intel,hda-dai"; 722 power-domains = <&io0_domain>; 723 zephyr,pm-device-runtime-auto; 724 status = "okay"; 725 reg = <0x0b>; 726 }; 727 hda12: hda@c { 728 compatible = "intel,hda-dai"; 729 power-domains = <&io0_domain>; 730 zephyr,pm-device-runtime-auto; 731 status = "okay"; 732 reg = <0x0c>; 733 }; 734 hda13: hda@d { 735 compatible = "intel,hda-dai"; 736 power-domains = <&io0_domain>; 737 zephyr,pm-device-runtime-auto; 738 status = "okay"; 739 reg = <0x0d>; 740 }; 741 hda14: hda@e { 742 compatible = "intel,hda-dai"; 743 power-domains = <&io0_domain>; 744 zephyr,pm-device-runtime-auto; 745 status = "okay"; 746 reg = <0x0e>; 747 }; 748 hda15: hda@f { 749 compatible = "intel,hda-dai"; 750 power-domains = <&io0_domain>; 751 zephyr,pm-device-runtime-auto; 752 status = "okay"; 753 reg = <0x0f>; 754 }; 755 hda16: hda@10 { 756 compatible = "intel,hda-dai"; 757 power-domains = <&io0_domain>; 758 zephyr,pm-device-runtime-auto; 759 status = "okay"; 760 reg = <0x10>; 761 }; 762 hda17: hda@11 { 763 compatible = "intel,hda-dai"; 764 power-domains = <&io0_domain>; 765 zephyr,pm-device-runtime-auto; 766 status = "okay"; 767 reg = <0x11>; 768 }; 769 hda18: hda@12 { 770 compatible = "intel,hda-dai"; 771 power-domains = <&io0_domain>; 772 zephyr,pm-device-runtime-auto; 773 status = "okay"; 774 reg = <0x12>; 775 }; 776 }; 777}; 778
