1/* 2 * Copyright (c) 2022 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <xtensa/xtensa.dtsi> 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "cdns,tensilica-xtensa-lx7"; 18 reg = <0>; 19 cpu-power-states = <&d0i3 &d3>; 20 i-cache-line-size = <64>; 21 d-cache-line-size = <64>; 22 }; 23 24 cpu1: cpu@1 { 25 device_type = "cpu"; 26 compatible = "cdns,tensilica-xtensa-lx7"; 27 reg = <1>; 28 cpu-power-states = <&d0i3 &d3>; 29 }; 30 31 cpu2: cpu@2 { 32 device_type = "cpu"; 33 compatible = "cdns,tensilica-xtensa-lx7"; 34 reg = <2>; 35 cpu-power-states = <&d0i3 &d3>; 36 }; 37 38 cpu3: cpu@3 { 39 device_type = "cpu"; 40 compatible = "cdns,tensilica-xtensa-lx7"; 41 reg = <3>; 42 cpu-power-states = <&d0i3 &d3>; 43 }; 44 45 cpu4: cpu@4 { 46 device_type = "cpu"; 47 compatible = "cdns,tensilica-xtensa-lx7"; 48 reg = <4>; 49 cpu-power-states = <&d0i3 &d3>; 50 }; 51 52 power-states { 53 d0i3: idle { 54 compatible = "zephyr,power-state"; 55 power-state-name = "runtime-idle"; 56 min-residency-us = <200>; 57 exit-latency-us = <100>; 58 }; 59 /* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force. 60 * The procedure is triggered by IPC from the HOST (SET_DX). 61 */ 62 d3: off { 63 compatible = "zephyr,power-state"; 64 power-state-name = "soft-off"; 65 min-residency-us = <0>; 66 exit-latency-us = <0>; 67 status = "disabled"; 68 }; 69 }; 70 }; 71 72 sram0: memory@a0020000 { 73 device_type = "memory"; 74 compatible = "mmio-sram"; 75 reg = <0xa0020000 DT_SIZE_K(2816)>; 76 }; 77 78 sram0virtual: virtualmemory@a0020000 { 79 device_type = "memory"; 80 compatible = "mmio-sram"; 81 reg = <0xa0020000 DT_SIZE_K(8192)>; 82 }; 83 84 sram1: memory@a0000000 { 85 device_type = "memory"; 86 compatible = "mmio-sram"; 87 reg = <0xa0000000 DT_SIZE_K(64)>; 88 }; 89 90 sysclk: system-clock { 91 compatible = "fixed-clock"; 92 clock-frequency = <38400000>; 93 #clock-cells = <0>; 94 }; 95 96 clkctl: clkctl { 97 compatible = "intel,adsp-shim-clkctl"; 98 adsp-clkctl-clk-wovcro = <0>; 99 adsp-clkctl-clk-ipll = <1>; 100 adsp-clkctl-freq-enc = <0xc 0x4>; 101 adsp-clkctl-freq-mask = <0x0 0x0>; 102 adsp-clkctl-freq-default = <1>; 103 adsp-clkctl-freq-lowest = <0>; 104 wovcro-supported; 105 }; 106 107 audioclk: audio-clock { 108 compatible = "fixed-clock"; 109 clock-frequency = <24576000>; 110 #clock-cells = <0>; 111 }; 112 113 pllclk: pll-clock { 114 compatible = "fixed-clock"; 115 clock-frequency = <96000000>; 116 #clock-cells = <0>; 117 }; 118 119 IMR1: memory@A1000000 { 120 compatible = "intel,adsp-imr"; 121 reg = <0xA1000000 DT_SIZE_M(16)>; 122 block-size = <0x1000>; 123 zephyr,memory-region = "IMR1"; 124 }; 125 126 shim: shim@71f00 { 127 compatible = "intel,adsp-shim"; 128 reg = <0x71f00 0x100>; 129 }; 130 131 soc { 132 133 l1ccap: l1ccap@1fe80080 { 134 compatible = "intel,adsp-l1ccap"; 135 reg = <0x1fe80080 0x4>; 136 }; 137 138 l1ccfg: l1ccfg@1fe80084 { 139 compatible = "intel,adsp-l1ccfg"; 140 reg = <0x1fe80084 0x4>; 141 }; 142 143 l1pcfg: l1pcfg@1fe80088 { 144 compatible = "intel,adsp-l1pcfg"; 145 reg = <0x1fe80088 0x4>; 146 }; 147 148 hsbcap: hsbcap@71d00 { 149 compatible = "intel,adsp-hsbcap"; 150 reg = <0x71d00 0x4>; 151 }; 152 153 lsbpm: lsbpm@71d80 { 154 compatible = "intel,adsp-lsbpm"; 155 reg = <0x71d80 0x0008>; 156 }; 157 158 hsbpm: hsbpm@17a800 { 159 compatible = "intel,adsp-hsbpm"; 160 reg = <0x17a800 0x0008>; 161 }; 162 163 core_intc: core_intc@0 { 164 compatible = "cdns,xtensa-core-intc"; 165 reg = <0x00 0x400>; 166 interrupt-controller; 167 #interrupt-cells = <3>; 168 }; 169 170 hdamlddmic: hdamlddmic@cc0 { 171 compatible = "intel,adsp-hda-dmic-cap"; 172 reg = <0xcc0 0x40>; 173 status = "okay"; 174 }; 175 176 dmic0: dai-dmic0@10100 { 177 compatible = "intel,dai-dmic"; 178 reg = <0x10100 0x8000>; 179 shim = <0x10000>; 180 fifo = <0x0008>; 181 interrupts = <0x08 0 0>; 182 interrupt-parent = <&ace_intc>; 183 zephyr,pm-device-runtime-auto; 184 }; 185 186 dmic1: dai-dmic1@10100 { 187 compatible = "intel,dai-dmic"; 188 reg = <0x10100 0x8000>; 189 shim = <0x10000>; 190 fifo = <0x0108>; 191 interrupts = <0x08 0 0>; 192 interrupt-parent = <&ace_intc>; 193 zephyr,pm-device-runtime-auto; 194 }; 195 196 dmicvss: dmicvss@16000 { 197 compatible = "intel,adsp-dmic-vss"; 198 reg = <0x16000 0x2000>; 199 status = "okay"; 200 }; 201 202 sspbase: ssp_base@28000 { 203 compatible = "intel,ssp-sspbase"; 204 reg = <0x28000 0x1000>; 205 }; 206 207 hdamlssp: hdamlssp@d00 { 208 compatible = "intel,adsp-hda-ssp-cap"; 209 reg = <0xD00 0x40>; 210 status = "okay"; 211 }; 212 213 ssp0: ssp@28100 { 214 compatible = "intel,ssp"; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 reg = <0x00028100 0x1000 218 0x00079C00 0x200>; 219 i2svss = <0x00028C00 0x1000>; 220 interrupts = <0x00 0 0>; 221 interrupt-parent = <&ace_intc>; 222 dmas = <&hda_link_out 1 223 &hda_link_in 1>; 224 dma-names = "tx", "rx"; 225 ssp-index = <0>; 226 status = "okay"; 227 228 ssp00: ssp@0 { 229 compatible = "intel,ssp-dai"; 230 power-domains = <&io0_domain>; 231 zephyr,pm-device-runtime-auto; 232 status = "okay"; 233 reg = <0x0>; 234 }; 235 }; 236 237 ssp1: ssp@29100 { 238 compatible = "intel,ssp"; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 reg = <0x00029100 0x1000 242 0x00079C00 0x200>; 243 i2svss = <0x00029C00 0x1000>; 244 interrupts = <0x01 0 0>; 245 interrupt-parent = <&ace_intc>; 246 dmas = <&hda_link_out 2 247 &hda_link_in 2>; 248 dma-names = "tx", "rx"; 249 ssp-index = <1>; 250 status = "okay"; 251 252 ssp10: ssp@10 { 253 compatible = "intel,ssp-dai"; 254 power-domains = <&io0_domain>; 255 zephyr,pm-device-runtime-auto; 256 status = "okay"; 257 reg = <0x10>; 258 }; 259 }; 260 261 ssp2: ssp@2a100 { 262 compatible = "intel,ssp"; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 reg = <0x0002a100 0x1000 266 0x00079C00 0x200>; 267 i2svss = <0x0002AC00 0x1000>; 268 interrupts = <0x02 0 0>; 269 interrupt-parent = <&ace_intc>; 270 dmas = <&hda_link_out 3 271 &hda_link_in 3>; 272 dma-names = "tx", "rx"; 273 ssp-index = <2>; 274 status = "okay"; 275 276 ssp20: ssp@20 { 277 compatible = "intel,ssp-dai"; 278 power-domains = <&io0_domain>; 279 zephyr,pm-device-runtime-auto; 280 status = "okay"; 281 reg = <0x20>; 282 }; 283 }; 284 285 mem_window0: mem_window@70200 { 286 compatible = "intel,adsp-mem-window"; 287 reg = <0x70200 0x8>; 288 offset = <0x4000>; 289 memory = <&sram0>; 290 initialize; 291 read-only; 292 }; 293 294 mem_window1: mem_window@70208 { 295 compatible = "intel,adsp-mem-window"; 296 reg = <0x70208 0x8>; 297 memory = <&sram0>; 298 }; 299 300 mem_window2: mem_window@70210 { 301 compatible = "intel,adsp-mem-window"; 302 reg = <0x70210 0x8>; 303 memory = <&sram0>; 304 }; 305 306 mem_window3: mem_window@70218 { 307 compatible = "intel,adsp-mem-window"; 308 reg = <0x70218 0x8>; 309 memory = <&sram0>; 310 read-only; 311 }; 312 313 adsp_idc: ace_idc@70400 { 314 compatible = "intel,adsp-idc"; 315 reg = <0x70400 0x0400>; 316 interrupts = <24 0 0>; 317 interrupt-parent = <&ace_intc>; 318 }; 319 320 dfpmcch: dfpmcch@71ac0 { 321 compatible = "intel,adsp-dfpmcch"; 322 reg = <0x00071ac0 0x40>; 323 }; 324 325 dfpmccu: dfpmccu@71b00 { 326 compatible = "intel,adsp-dfpmccu"; 327 reg = <0x71b00 0x100>; 328 329 hub_ulp_domain: hub_ulp_domain { 330 compatible = "intel,adsp-power-domain"; 331 bit-position = <15>; 332 #power-domain-cells = <0>; 333 }; 334 ml0_domain: ml0_domain { 335 compatible = "intel,adsp-power-domain"; 336 bit-position = <12>; 337 #power-domain-cells = <0>; 338 }; 339 io1_domain: io1_domain { 340 compatible = "intel,adsp-power-domain"; 341 bit-position = <9>; 342 #power-domain-cells = <0>; 343 }; 344 io0_domain: io0_domain { 345 compatible = "intel,adsp-power-domain"; 346 bit-position = <8>; 347 #power-domain-cells = <0>; 348 }; 349 hub_hp_domain: hub_hp_domain { 350 compatible = "intel,adsp-power-domain"; 351 bit-position = <6>; 352 #power-domain-cells = <0>; 353 }; 354 hst_domain: hst_domain { 355 compatible = "intel,adsp-power-domain"; 356 bit-position = <5>; 357 #power-domain-cells = <0>; 358 }; 359 }; 360 361 tts: tts@72000 { 362 compatible = "intel,adsp-tts"; 363 reg = <0x72000 0x70>; 364 status = "okay"; 365 }; 366 367 ace_rtc_counter: ace_rtc_counter@72008 { 368 compatible = "intel,ace-rtc-counter"; 369 reg = <0x72008 0x0064>; 370 }; 371 372 373 ace_timestamp: ace_timestamp@72040 { 374 compatible = "intel,ace-timestamp"; 375 reg = <0x72040 0x0032>; 376 }; 377 378 ace_art_counter: ace_art_counter@72058 { 379 compatible = "intel,ace-art-counter"; 380 reg = <0x72058 0x0064>; 381 }; 382 383 hda_host_out: dma@72800 { 384 compatible = "intel,adsp-hda-host-out"; 385 #dma-cells = <1>; 386 reg = <0x00072800 0x40>; 387 dma-channels = <9>; 388 dma-buf-addr-alignment = <128>; 389 dma-buf-size-alignment = <32>; 390 dma-copy-alignment = <16>; 391 power-domains = <&hst_domain>; 392 zephyr,pm-device-runtime-auto; 393 interrupts = <13 0 0>; 394 interrupt-parent = <&ace_intc>; 395 status = "okay"; 396 }; 397 398 hda_host_in: dma@72c00 { 399 compatible = "intel,adsp-hda-host-in"; 400 #dma-cells = <1>; 401 reg = <0x00072c00 0x40>; 402 dma-channels = <11>; 403 dma-buf-addr-alignment = <128>; 404 dma-buf-size-alignment = <32>; 405 dma-copy-alignment = <16>; 406 power-domains = <&hst_domain>; 407 zephyr,pm-device-runtime-auto; 408 interrupts = <12 0 0>; 409 interrupt-parent = <&ace_intc>; 410 status = "okay"; 411 }; 412 413 adsp_host_ipc: ace_host_ipc@73000 { 414 compatible = "intel,adsp-host-ipc"; 415 status = "okay"; 416 reg = <0x73000 0x30>; 417 interrupts = <0 0 0>; 418 interrupt-parent = <&ace_intc>; 419 }; 420 421 hda_link_out: dma@79400 { 422 compatible = "intel,adsp-hda-link-out"; 423 #dma-cells = <1>; 424 reg = <0x00079400 0x40>; 425 dma-channels = <9>; 426 dma-buf-addr-alignment = <128>; 427 dma-buf-size-alignment = <32>; 428 dma-copy-alignment = <16>; 429 power-domains = <&hub_ulp_domain>; 430 zephyr,pm-device-runtime-auto; 431 status = "okay"; 432 }; 433 434 hda_link_in: dma@79800 { 435 compatible = "intel,adsp-hda-link-in"; 436 #dma-cells = <1>; 437 reg = <0x00079800 0x40>; 438 dma-channels = <11>; 439 dma-buf-addr-alignment = <128>; 440 dma-buf-size-alignment = <32>; 441 dma-copy-alignment = <16>; 442 power-domains = <&hub_ulp_domain>; 443 zephyr,pm-device-runtime-auto; 444 status = "okay"; 445 }; 446 447 /* This is actually an array of per-core designware 448 * controllers, but the special setup and extra 449 * masking layer makes it easier for LNL to handle 450 * this internally. 451 */ 452 ace_intc: ace_intc@7ac00 { 453 compatible = "intel,ace-intc"; 454 reg = <0x7ac00 0xc00>; 455 interrupt-controller; 456 #interrupt-cells = <3>; 457 interrupts = <4 0 0>; 458 num-irqs = <28>; 459 interrupt-parent = <&core_intc>; 460 }; 461 462 tlb: tlb@17e000 { 463 compatible = "intel,adsp-mtl-tlb"; 464 reg = <0x17e000 0x1000>; 465 paddr-size = <12>; 466 exec-bit-idx = <14>; 467 write-bit-idx= <15>; 468 }; 469 470 timer: timer { 471 compatible = "intel,adsp-timer"; 472 syscon = <&tts>; 473 }; 474 }; 475 476 hdas { 477 #address-cells = <1>; 478 #size-cells = <0>; 479 480 hda0: hda@0 { 481 compatible = "intel,hda-dai"; 482 power-domains = <&io0_domain>; 483 zephyr,pm-device-runtime-auto; 484 status = "okay"; 485 reg = <0>; 486 }; 487 hda1: hda@1 { 488 compatible = "intel,hda-dai"; 489 power-domains = <&io0_domain>; 490 zephyr,pm-device-runtime-auto; 491 status = "okay"; 492 reg = <1>; 493 }; 494 hda2: hda@2 { 495 compatible = "intel,hda-dai"; 496 power-domains = <&io0_domain>; 497 zephyr,pm-device-runtime-auto; 498 status = "okay"; 499 reg = <2>; 500 }; 501 hda3: hda@3 { 502 compatible = "intel,hda-dai"; 503 power-domains = <&io0_domain>; 504 zephyr,pm-device-runtime-auto; 505 status = "okay"; 506 reg = <3>; 507 }; 508 hda4: hda@4 { 509 compatible = "intel,hda-dai"; 510 power-domains = <&io0_domain>; 511 zephyr,pm-device-runtime-auto; 512 status = "okay"; 513 reg = <4>; 514 }; 515 hda5: hda@5 { 516 compatible = "intel,hda-dai"; 517 power-domains = <&io0_domain>; 518 zephyr,pm-device-runtime-auto; 519 status = "okay"; 520 reg = <5>; 521 }; 522 hda6: hda@6 { 523 compatible = "intel,hda-dai"; 524 power-domains = <&io0_domain>; 525 zephyr,pm-device-runtime-auto; 526 status = "okay"; 527 reg = <6>; 528 }; 529 hda7: hda@7 { 530 compatible = "intel,hda-dai"; 531 power-domains = <&io0_domain>; 532 zephyr,pm-device-runtime-auto; 533 status = "okay"; 534 reg = <7>; 535 }; 536 hda8: hda@8 { 537 compatible = "intel,hda-dai"; 538 power-domains = <&io0_domain>; 539 zephyr,pm-device-runtime-auto; 540 status = "okay"; 541 reg = <8>; 542 }; 543 hda9: hda@9 { 544 compatible = "intel,hda-dai"; 545 power-domains = <&io0_domain>; 546 zephyr,pm-device-runtime-auto; 547 status = "okay"; 548 reg = <9>; 549 }; 550 hda10: hda@a { 551 compatible = "intel,hda-dai"; 552 power-domains = <&io0_domain>; 553 zephyr,pm-device-runtime-auto; 554 status = "okay"; 555 reg = <0x0a>; 556 }; 557 hda11: hda@b { 558 compatible = "intel,hda-dai"; 559 power-domains = <&io0_domain>; 560 zephyr,pm-device-runtime-auto; 561 status = "okay"; 562 reg = <0x0b>; 563 }; 564 hda12: hda@c { 565 compatible = "intel,hda-dai"; 566 power-domains = <&io0_domain>; 567 zephyr,pm-device-runtime-auto; 568 status = "okay"; 569 reg = <0x0c>; 570 }; 571 hda13: hda@d { 572 compatible = "intel,hda-dai"; 573 power-domains = <&io0_domain>; 574 zephyr,pm-device-runtime-auto; 575 status = "okay"; 576 reg = <0x0d>; 577 }; 578 hda14: hda@e { 579 compatible = "intel,hda-dai"; 580 power-domains = <&io0_domain>; 581 zephyr,pm-device-runtime-auto; 582 status = "okay"; 583 reg = <0x0e>; 584 }; 585 hda15: hda@f { 586 compatible = "intel,hda-dai"; 587 power-domains = <&io0_domain>; 588 zephyr,pm-device-runtime-auto; 589 status = "okay"; 590 reg = <0x0f>; 591 }; 592 hda16: hda@10 { 593 compatible = "intel,hda-dai"; 594 power-domains = <&io0_domain>; 595 zephyr,pm-device-runtime-auto; 596 status = "okay"; 597 reg = <0x10>; 598 }; 599 hda17: hda@11 { 600 compatible = "intel,hda-dai"; 601 power-domains = <&io0_domain>; 602 zephyr,pm-device-runtime-auto; 603 status = "okay"; 604 reg = <0x11>; 605 }; 606 hda18: hda@12 { 607 compatible = "intel,hda-dai"; 608 power-domains = <&io0_domain>; 609 zephyr,pm-device-runtime-auto; 610 status = "okay"; 611 reg = <0x12>; 612 }; 613 }; 614}; 615
