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/Zephyr-latest/dts/bindings/flash_controller/
Datmel,sam0-nvmctrl.yaml1 description: Atmel SAM0 NVMC (Non-Volatile Memory Controller)
3 compatible: "atmel,sam0-nvmctrl"
5 include: flash-controller.yaml
8 lock-regions:
11 description: Number of lock regions
/Zephyr-latest/soc/ti/k3/am6x/m4/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
43 * Add regions here if you want to map more memory.
52 /* Lock 0 */ in am6x_mmr_unlock()
58 /* Lock 1 */ in am6x_mmr_unlock()
/Zephyr-latest/include/zephyr/arch/xtensa/
Dmpu.h4 * SPDX-License-Identifier: Apache-2.0
12 #include <xtensa/config/core-isa.h>
93 * This contains the start address, the enable bit, and the lock bit.
110 * Lock bit for this entry.
116 * - This cannot be cleared until reset.
117 * - This entry can no longer be modified.
118 * - The start address of the next entry also
121 uint32_t lock:1; member
170 * cacheable vs non-cacheable, shareable vs non-shareable.
252 /* Read-Write access permission attributes */
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Darch.h3 * SPDX-License-Identifier: Apache-2.0
48 * @ingroup arch-interface
147 * @brief Lock VECBASE if supported by hardware.
149 * The bit 0 of VECBASE acts as a lock bit on hardware supporting
178 * for regions (including MMIO registers in region zero) which want to
186 * in the same cache line (two 3-byte instructions fit in an 8-byte
/Zephyr-latest/arch/arm/core/mpu/cortex_m/
Darm_mpu_internal.h1 /* SPDX-License-Identifier: Apache-2.0
9 * Get the number of supported MPU regions.
13 uint32_t type = MPU->TYPE; in get_num_regions()
22 MPU->RNR = index; in set_region_number()
27 MPU->RNR = index; in mpu_region_get_base()
28 return MPU->RBAR & MPU_RBAR_ADDR_Msk; in mpu_region_get_base()
48 /* Lock IRQs to ensure RNR value is correct when reading RASR. */ in is_enabled_region()
53 MPU->RNR = index; in is_enabled_region()
54 rasr = MPU->RASR; in is_enabled_region()
69 /* Lock IRQs to ensure RNR value is correct when reading RASR. */ in get_region_ap()
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/Zephyr-latest/doc/hardware/peripherals/edac/
Dibecc.rst12 The In-Band Error Correction Code (IBECC) improves reliability by providing
13 error detection and correction. IBECC can work for all or for specific regions
15 not support the out-of-band ECC.
42 mode 0 there are more BIOS configuration options such as memory regions.
58 * Correctable Error (CE) - error is detected and corrected by IBECC module.
60 * Uncorrectable Error (UE) - error is detected by IBECC module and not
63 The IBECC driver provides error type for the higher-level application to
65 syndrome is not used in the IBECC driver but provided to higher-level
75 higher-level synchronization primitives. So, you cannot share anything that is
76 "protected" by a lock with an NMI, because the protection does not work. The
/Zephyr-latest/boards/native/nrf_bsim/common/cmsis/
Dcmsis_instr.h4 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
6 * SPDX-License-Identifier: Apache-2.0
11 * ARM Cortex-M CMSIS intrinsics.
17 /* Implement the following ARM intrinsics as no-op:
18 * - ARM Data Synchronization Barrier
19 * - ARM Data Memory Synchronization Barrier
20 * - ARM Instruction Synchronization Barrier
21 * - ARM No Operation
44 * Implement the following ARM intrinsics as non-exclusive accesses
46 * - STR Exclusive(8,16 & 32bit) (__STREX{B,H,W})
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/Zephyr-latest/kernel/
DKconfig.smp2 # SPDX-License-Identifier: Apache-2.0
15 bool "Use new-style _arch_switch instead of arch_swap"
20 for an SMP-aware scheduler, or if the architecture does not
46 Maximum number of multiprocessing-capable cores available to the
105 where all shared data is placed in multiprocessor-coherent
109 running on cache-incoherent architectures only. Note that
112 Code that creates kernel data structures in uncached regions
117 bool "Ticket spinlocks for lock acquisition fairness [EXPERIMENTAL]"
124 in a live-lock.
125 Ticket spinlocks provide a FIFO order of lock acquisition
Dmmu.c4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/linker/linker-defs.h>
31 * - A page frame is a page-sized physical memory region in RAM. It is a
37 * - A data page is a page-sized region of data. It may exist in a page frame,
86 printk("-"); in page_frame_dump()
160 * +--------------+ <- K_MEM_VIRT_RAM_START
161 * | Undefined VM | <- May contain ancillary regions like x86_64's locore
162 * +--------------+ <- K_MEM_KERNEL_VIRT_START (often == K_MEM_VIRT_RAM_START)
168 * +--------------+ <- K_MEM_VM_FREE_START
173 * |..............| <- mapping_pos (grows downward as more mappings are made)
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/Zephyr-latest/soc/microchip/mec/mec15xx/
Dsoc_espi_saf_v1.h4 * SPDX-License-Identifier: Apache-2.0
60 /* QMSPI descriptors 12-15 for all SPI flash devices */
64 * QMSPI descriptors 12-13 are exit continuous mode
84 * QMSPI descriptors 14-15 are poll 16-bit flash status
106 /* SAF Pre-fetch optimization mode */
112 * SAF Opcode 32-bit register value.
113 * Each byte contain a SPI flash 8-bit opcode.
117 * op0 = SPI flash write-enable opcode
127 * op0 = SPI flash read 1-4-4 continuous mode opcode
128 * op1 = SPI flash op0 mode byte value for non-continuous mode
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/Zephyr-latest/arch/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
6 # SPDX-License-Identifier: Apache-2.0
18 # Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
37 # is really only necessary for Cortex-M with ARM MPU!
173 symbols above. See the top-level CMakeLists.txt.
180 module-str = arch
186 This option tells the build system that the target system is big-endian.
187 Little-endian architecture is the default and should leave this option
195 # Hidden Kconfig option representing the default little-endian architecture
196 # This is just the opposite of BIG_ENDIAN and is used for non-negative
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/Zephyr-latest/lib/utils/
Donoff.c5 * SPDX-License-Identifier: Apache-2.0
24 * bits are manipulated by process_event() under lock, and actions
25 * cued by bit values are executed outside of lock within
48 * process_events() must re-check the overall state to confirm no
61 /* No-op event: used to process deferred changes.
71 * state (TO-ON, TO-OFF, or RESETTING).
82 * The client list can change while the manager lock is
92 * This is synthesized from EVT_RECHECK in a non-nested
94 * non-empty client (request) list.
100 * This is synthesized from EVT_RECHECK in a non-nested
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/Zephyr-latest/soc/microchip/mec/mec172x/
Dsoc_espi_saf_v2.h4 * SPDX-License-Identifier: Apache-2.0
41 * Boot-ROM OTP configuration.
70 /* QMSPI descriptors 12-15 for all SPI flash devices */
72 /* QMSPI descriptors 12-13 are exit continuous mode */
108 * QMSPI descriptors 14-15 are poll 16-bit flash status
130 /* SAF Pre-fetch optimization mode */
136 * SAF Opcode 32-bit register value.
137 * Each byte contain a SPI flash 8-bit opcode.
141 * op0 = SPI flash write-enable opcode
151 * op0 = SPI flash read 1-4-4 continuous mode opcode
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/Zephyr-latest/arch/arc/core/
Dreset.S4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/arch/arc/asm-compat/assembler.h>
49 /* lock interrupts: will get unlocked when switch to main task
124 * For scenarios where board hardware is not re-initialized between tests,
141 /* Set all MPU regions by iterating index */
169 * Non-masters wait for master core (core 0) to boot enough
/Zephyr-latest/boards/amd/kv260_r5/doc/
Dindex.rst5 This configuration provides support for the RPU, real-time processing unit on Xilinx
9 * Or as a single dual lock step unit with double the TCM size.
11 This processing unit is based on an ARM Cortex-R5 CPU, it also enables the following devices:
13 * ARM PL-390 Generic Interrupt Controller
24 +--------------+------------+----------------------+
27 | GIC | on-chip | generic interrupt |
29 +--------------+------------+----------------------+
30 | TTC | on-chip | system timer |
31 +--------------+------------+----------------------+
32 | UART | on-chip | serial port |
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/Zephyr-latest/dts/arm/atmel/
Dsamd2x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
16 adc-0 = &adc;
18 port-a = &porta;
19 port-b = &portb;
21 sercom-0 = &sercom0;
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Dsaml2x.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv6-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
17 adc-0 = &adc;
19 port-a = &porta;
20 port-b = &portb;
22 sercom-0 = &sercom0;
[all …]
Dsamc2x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
16 adc-0 = &adc0;
18 port-a = &porta;
19 port-b = &portb;
20 port-c = &portc;
[all …]
/Zephyr-latest/arch/xtensa/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
32 the core-isa.h file. This replaces the previous scheme
62 A design trick on multi-core hardware is to map memory twice
71 This specifies which 512M region (0-7, as defined by the Xtensa
79 region (0-7) contains the "uncached" mapping.
94 NOPs after failure to lock a spinlock. This gives
161 bool "Xtensa exceptions and interrupts cannot be pre-empted"
164 pre-empting low priority interrupts and exceptions.
263 Default memory type for memory regions: non-cacheable memory,
264 non-shareable, non-bufferable and interruptible.
[all …]
/Zephyr-latest/doc/hardware/arch/
Darm_cortex_m.rst3 Arm Cortex-M Developer Guide
9 This page contains detailed information about the status of the Arm Cortex-M
11 developing Zephyr applications for Arm Cortex-M-based platforms.
17 Arm Cortex-M implementation variants.
20 …---------------------------------+-----------------------------------+-----------------+---------+…
22 …---------------------------------+-----------------------------------+-----------------+---------+…
23 … | Arm v6-M | Arm v7-M | Arm v8-M …
24 …---------------------------------+-----------------------------------+-----------------+---------+…
26 …---------------------------------+-----------------------------------+-----------------+---------+…
28 …---------------------------------+-----------------------------------+-----------------+---------+…
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/Zephyr-latest/drivers/flash/
Dflash_sam0.c4 * SPDX-License-Identifier: Apache-2.0
22 BUILD_ASSERT((FLASH_WRITE_BLK_SZ % sizeof(uint32_t)) == 0, "unsupported write-block-size");
36 * Number of lock regions. The number is fixed and the region size
84 struct flash_sam0_data *ctx = dev->data; in flash_sam0_sem_take()
86 k_sem_take(&ctx->sem, K_FOREVER); in flash_sam0_sem_take()
93 struct flash_sam0_data *ctx = dev->data; in flash_sam0_sem_give()
95 k_sem_give(&ctx->sem); in flash_sam0_sem_give()
103 return -EINVAL; in flash_sam0_valid_range()
107 return -EINVAL; in flash_sam0_valid_range()
116 while (NVMCTRL->STATUS.bit.READY == 0) { in flash_sam0_wait_ready()
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/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_espi_saf.h4 * SPDX-License-Identifier: Apache-2.0
21 /* 17 protection regions */
33 /* SAF Protection region described by 4 32-bit registers. 17 regions */
232 /* SAF Protection Lock register */
535 /* Allow pre-fetch from flash devices */
572 /** @brief SAF protection regions contain 4 32-bit registers. */
596 struct mchp_espi_saf_op SAF_CS_OP[2]; /* 0x4c - 0x6b */
600 volatile uint32_t SAF_TAG_MAP[3]; /* 0x78 - 0x83 */
601 struct mchp_espi_saf_pr SAF_PROT_RG[17]; /* 0x84 - 0x193 */
635 uint32_t RSVD1[(0x2b8 - 0x01c) / 4];
/Zephyr-latest/drivers/entropy/
Dentropy_stm32.c7 * SPDX-License-Identifier: Apache-2.0
44 * - simple rng without hardware fifo and no DMA.
45 * - Variable delay between two consecutive random numbers
74 (CONFIG_ENTROPY_STM32_ISR_POOL_SIZE - 1)) == 0,
78 (CONFIG_ENTROPY_STM32_THR_POOL_SIZE - 1)) == 0,
110 struct entropy_stm32_rng_dev_data *dev_data = dev->data; in entropy_stm32_suspend()
111 const struct entropy_stm32_rng_dev_cfg *dev_cfg = dev->config; in entropy_stm32_suspend()
112 RNG_TypeDef *rng = dev_data->rng; in entropy_stm32_suspend()
128 if (clock_control_get_rate(dev_data->clock, in entropy_stm32_suspend()
129 (clock_control_subsys_t) &dev_cfg->pclken[0], in entropy_stm32_suspend()
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/Zephyr-latest/doc/hardware/porting/
Darch.rst13 * ARMv7-M ISA with Thumb2 instruction set and ARM Embedded ABI (aeabi)
33 and architecture-dependent, and thread abortion possibly as well (required).
39 architecture-specific implementation for performance reasons (required).
44 * **Fault management**: for implementing architecture-specific debug help and
47 * **Linker scripts and toolchains**: architecture-specific details will most
50 * **Memory Management and Memory Mapping**: for architecture-specific details
53 * **Stack Objects**: for architecture-specific details on memory protection
71 * If running an :abbr:`XIP (eXecute-In-Place)` kernel, copy initialized data
79 Some examples of architecture-specific steps that have to be taken:
81 * If given control in real mode on x86_32, switch to 32-bit protected mode.
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/Zephyr-latest/doc/kernel/services/threads/
Dindex.rst28 stack memory regions.
69 value -- for example, to allow device hardware used by the thread
75 re-spawned before it can be used.
91 thread self-exits, or the target thread aborts (either due to a
96 re-used for any purpose, including spawning a new thread. Note that
176 - There may need to be additional memory reserved for memory management
178 - If guard-based stack overflow detection is enabled, a small write-protected
181 - If userspace is enabled, a separate fixed-size privilege elevation stack must
183 - If userspace is enabled, the thread's stack buffer must be appropriately
188 require their regions to be of some power of two in size, and aligned to its
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