1/*
2 * Copyright (c) 2021 Argentum Systems Ltd.
3 * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <mem.h>
9#include <arm/armv6-m.dtsi>
10#include <zephyr/dt-bindings/adc/adc.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/pwm/pwm.h>
14
15/ {
16	aliases {
17		adc-0 = &adc;
18
19		port-a = &porta;
20		port-b = &portb;
21
22		sercom-0 = &sercom0;
23		sercom-1 = &sercom1;
24		sercom-2 = &sercom2;
25		sercom-3 = &sercom3;
26		sercom-4 = &sercom4;
27		sercom-5 = &sercom5;
28
29		tc-4 = &tc4;
30
31		watchdog0 = &wdog;
32	};
33
34	chosen {
35		zephyr,flash-controller = &nvmctrl;
36		zephyr,entropy = &trng;
37	};
38
39	cpus {
40		#address-cells = <1>;
41		#size-cells = <0>;
42
43		cpu0: cpu@0 {
44			compatible = "arm,cortex-m0+";
45			reg = <0>;
46
47			device_type = "cpu";
48		};
49	};
50
51	sram0: memory@20000000 {
52		compatible = "mmio-sram";
53		reg = <0x20000000 0x8000>;
54	};
55
56	id: device_id@80a00c {
57		compatible = "atmel,sam0-id";
58		reg =	<0x0080A00C 0x4>,
59			<0x0080A040 0x4>,
60			<0x0080A044 0x4>,
61			<0x0080A048 0x4>;
62	};
63
64	soc {
65		nvmctrl: nvmctrl@41004000  {
66			compatible = "atmel,sam0-nvmctrl";
67			reg = <0x41004000 0x22>;
68			interrupts = <4 0>;
69
70			#address-cells = <1>;
71			#size-cells = <1>;
72
73			lock-regions = <16>;
74
75			flash0: flash@0 {
76				compatible = "soc-nv-flash";
77				reg = <0 0x40000>;
78
79				write-block-size = <4>;
80			};
81		};
82
83		pm: pm@40000400 {
84			compatible = "atmel,saml2x-pm";
85			reg = <0x40000400 0x400>;
86			interrupts = <0 0>;
87
88			#clock-cells = <2>;
89		};
90
91		mclk: mclk@40000400 {
92			compatible = "atmel,saml2x-mclk";
93			reg = <0x40000400 0x400>;
94
95			#clock-cells = <2>;
96		};
97
98		gclk: gclk@40001800 {
99			compatible = "atmel,saml2x-gclk";
100			reg = <0x40001800 0x400>;
101
102			#clock-cells = <1>;
103		};
104
105		dmac: dmac@44000400 {
106			compatible = "atmel,sam0-dmac";
107			reg = <0x44000400 0x400>;
108			interrupts = <5 0>;
109			status = "disabled";
110
111			#dma-cells = <2>;
112		};
113
114		eic: eic@40002400 {
115			compatible = "atmel,sam0-eic";
116			reg = <0x40002400 0x24>;
117			interrupts = <3 0>;
118		};
119
120		wdog: watchdog@40001c00 {
121			compatible = "atmel,sam0-watchdog";
122			reg = <0x40001c00 0x0c>;
123			interrupts = <1 0>;
124		};
125
126		sercom0: sercom@42000000 {
127			compatible = "atmel,sam0-sercom";
128			reg = <0x42000000 0x40>;
129			status = "disabled";
130		};
131
132		sercom1: sercom@42000400 {
133			compatible = "atmel,sam0-sercom";
134			reg = <0x42000400 0x40>;
135			status = "disabled";
136		};
137
138		sercom2: sercom@42000800 {
139			compatible = "atmel,sam0-sercom";
140			reg = <0x42000800 0x40>;
141			status = "disabled";
142		};
143
144		sercom3: sercom@42000c00 {
145			compatible = "atmel,sam0-sercom";
146			reg = <0x42000C00 0x40>;
147			status = "disabled";
148		};
149
150		sercom4: sercom@42001000 {
151			compatible = "atmel,sam0-sercom";
152			reg = <0x42001000 0x40>;
153			status = "disabled";
154		};
155
156		sercom5: sercom@43000400 {
157			compatible = "atmel,sam0-sercom";
158			reg = <0x43000400 0x40>;
159			status = "disabled";
160		};
161
162		tc4: tc@43000800 {
163			compatible = "atmel,sam0-tc32";
164			reg = <0x43000800 0x34>;
165			status = "disabled";
166		};
167
168		pinctrl: pinctrl@40002800 {
169			compatible = "atmel,sam0-pinctrl";
170			ranges = <0x40002800 0x40002800 0x100>;
171
172			#address-cells = <1>;
173			#size-cells = <1>;
174
175			porta: gpio@40002800 {
176				compatible = "atmel,sam0-gpio";
177				reg = <0x40002800 0x80>;
178
179				#atmel,pin-cells = <2>;
180				#gpio-cells = <2>;
181
182				gpio-controller;
183			};
184
185			portb: gpio@40002880 {
186				compatible = "atmel,sam0-gpio";
187				reg = <0x40002880 0x80>;
188
189				#atmel,pin-cells = <2>;
190				#gpio-cells = <2>;
191
192				gpio-controller;
193			};
194		};
195
196		rtc: rtc@40002000 {
197			compatible = "atmel,sam0-rtc";
198			reg = <0x40002000 0x1c>;
199			interrupts = <2 0>;
200			status = "disabled";
201
202			clock-generator = <0>;
203		};
204
205		adc: adc@43000c00 {
206			compatible = "atmel,sam0-adc";
207			reg = <0x43000c00 0x30>;
208			status = "disabled";
209
210			#io-channel-cells = <1>;
211
212			/*
213			 * 16 MHz max, so clock it with the
214			 * 48 MHz DFLL / 2 / 2 = 12 MHz
215			 */
216			gclk = <3>;
217			prescaler = <2>;
218		};
219
220		dac: dac@42003000 {
221			compatible = "atmel,sam0-dac";
222			reg = <0x42003000 0x1a>;
223			status = "disabled";
224
225			#io-channel-cells = <0>;
226		};
227
228		trng: random@42003800 {
229			compatible = "atmel,sam-trng";
230			reg = <0x42003800 0x24>;
231			interrupts = <27 0>;
232		};
233
234		usb0: usb@41000000 {
235			compatible = "atmel,sam0-usb";
236			reg = <0x41000000 0x1000>;
237			interrupts = <6 0>;
238			status = "disabled";
239
240			num-bidir-endpoints = <8>;
241		};
242	};
243};
244
245&nvic {
246	arm,num-irq-priority-bits = <2>;
247};
248