Lines Matching +full:lock +full:- +full:regions
3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
6 # SPDX-License-Identifier: Apache-2.0
18 # Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
37 # is really only necessary for Cortex-M with ARM MPU!
173 symbols above. See the top-level CMakeLists.txt.
180 module-str = arch
186 This option tells the build system that the target system is big-endian.
187 Little-endian architecture is the default and should leave this option
195 # Hidden Kconfig option representing the default little-endian architecture
196 # This is just the opposite of BIG_ENDIAN and is used for non-negative
206 using a 64-bit address space, meaning that pointer and long types
263 allow the CPU to execute in Non-Secure (Normal) state.
268 allow certain functions to be called from the Non-Secure
273 bool "Trusted Execution: Non-Secure firmware image"
275 Select this option to enable building a Non-Secure
277 Execution. A Non-Secure firmware image will execute
278 in Non-Secure (Normal) state. Therefore, it shall not
288 Select this option to enable hardware-based platform features to
365 whose MPUs require regions to be power-of-two aligned/sized.
401 due to the supplemental run-time tables required to validate such
404 Objects allocated in this way can be freed with a supervisor-only
412 Add a "nocache" read-write memory section that is configured to
467 interrupt-related data structures to RAM instead of ROM, and
477 non-negligible amount.
602 to collect for post-mortem analysis and debug of issues.
631 of the internal architectural state (for example ARCH-level
635 firmware image is chain-loaded, for example, by a debugger
640 Note: the functionality is architecture-specific. For the
720 When selected, the architecture supports suspend-to-RAM (S2RAM).
763 Dual-redundant Core Lock-step (DCLS) topology.
825 This hidden configuration should be selected when the CPU has a d-cache.
831 incoherent cache. This applies to intra-CPU multiprocessing
837 This hidden configuration should be selected when the CPU has an i-cache.
844 If RAM starts at 0x0, the first page must remain un-mapped to catch NULL
850 It is the architecture's responsibility to mark reserved memory regions
853 Although the kernel will not disturb this RAM mapping by re-mapping the associated
856 this mapping at all; non-kernel pages will be considered free (unless marked
865 Dual-redundant Core Lock-step (DCLS) topology. For the processor that
866 supports DCLS, but is configured in split-lock mode (by default or
878 module-str = mpu
885 and size for MPU regions.
891 MPU regions to be non-overlapping with each other.
894 bool "Force MPU to be filling in background memory regions"
900 dynamic MPU regions (user thread stack, PRIV stack guard
901 and application memory domains) during context-switch. We
904 regions available for application memory domain programming.
907 An increased number of MPU regions should only be required,
913 covered by explicit MPU regions is restricted to privileged
914 code on an ARCH-specific basis. Refer to ARCH-specific
926 is present, enabled, and regions have been configured at boot for memory
933 1) All program text will be have read-only, execute memory permission
934 2) All read-only data will have read-only permission, and execution
936 3) All other RAM addresses will have read-write permission, and
950 RAM for the alignment between regions.
958 the target regions should be specified in CMakeLists.txt using
991 those platforms is dependent on the availability of the toolchain-
1016 bool "Data cache (d-cache) support"
1020 This option enables the support for the data cache (d-cache).
1023 bool "Instruction cache (i-cache) support"
1027 This option enables the support for the instruction cache (i-cache).
1030 bool "Cache double-mapping support"
1034 Double-mapping behavior where a pointer can be cheaply converted to
1037 This applies to intra-CPU multiprocessing incoherence and makes only
1048 bool "Detect d-cache line size at runtime"
1051 This option enables querying some architecture-specific hardware for
1052 finding the d-cache line size at the expense of taking more memory and
1055 If the CPU's d-cache line size is known in advance, disable this option and
1057 using the 'd-cache-line-size' property.
1060 int "d-cache line size"
1064 Size in bytes of a CPU d-cache line. If this is set to 0 the value is
1065 obtained from the 'd-cache-line-size' DT property instead if present.
1071 bool "Detect i-cache line size at runtime"
1074 This option enables querying some architecture-specific hardware for
1075 finding the i-cache line size at the expense of taking more memory and
1078 If the CPU's i-cache line size is known in advance, disable this option and
1080 using the 'i-cache-line-size' property.
1083 int "i-cache line size"
1087 Size in bytes of a CPU i-cache line. If this is set to 0 the value is
1088 obtained from the 'i-cache-line-size' DT property instead if present.
1100 Integrated on-core cache controller