4  * SPDX-License-Identifier: Apache-2.0
22 BUILD_ASSERT((FLASH_WRITE_BLK_SZ % sizeof(uint32_t)) == 0, "unsupported write-block-size");
36  * Number of lock regions.  The number is fixed and the region size
84 	struct flash_sam0_data *ctx = dev->data;  in flash_sam0_sem_take()
86 	k_sem_take(&ctx->sem, K_FOREVER);  in flash_sam0_sem_take()
93 	struct flash_sam0_data *ctx = dev->data;  in flash_sam0_sem_give()
95 	k_sem_give(&ctx->sem);  in flash_sam0_sem_give()
103 		return -EINVAL;  in flash_sam0_valid_range()
107 		return -EINVAL;  in flash_sam0_valid_range()
116 	while (NVMCTRL->STATUS.bit.READY == 0) {  in flash_sam0_wait_ready()
119 	while (NVMCTRL->INTFLAG.bit.READY == 0) {  in flash_sam0_wait_ready()
129 	NVMCTRL_INTFLAG_Type status = NVMCTRL->INTFLAG;  in flash_sam0_check_status()
132 	NVMCTRL->INTFLAG.reg = status.reg;  in flash_sam0_check_status()
134 	NVMCTRL_STATUS_Type status = NVMCTRL->STATUS;  in flash_sam0_check_status()
137 	NVMCTRL->STATUS = status;  in flash_sam0_check_status()
142 		return -EIO;  in flash_sam0_check_status()
144 		LOG_ERR("lock error at 0x%lx", (long)offset);  in flash_sam0_check_status()
145 		return -EROFS;  in flash_sam0_check_status()
148 		return -EIO;  in flash_sam0_check_status()
158  * be 16 or 32 bits. 8-bit writes to the page buffer are not allowed and
170 	NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY;  in flash_sam0_write_page()
172 	NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_PBC | NVMCTRL_CTRLB_CMDEX_KEY;  in flash_sam0_write_page()
182 	NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_WP | NVMCTRL_CTRLA_CMDEX_KEY;  in flash_sam0_write_page()
184 	NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_WP | NVMCTRL_CTRLB_CMDEX_KEY;  in flash_sam0_write_page()
194 		return -EIO;  in flash_sam0_write_page()
204 	NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_ER | NVMCTRL_CTRLA_CMDEX_KEY;  in flash_sam0_erase_row()
206 	NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_EB | NVMCTRL_CTRLB_CMDEX_KEY;  in flash_sam0_erase_row()
215 	struct flash_sam0_data *ctx = dev->data;  in flash_sam0_commit()
227 			&ctx->buf[page * FLASH_PAGE_SIZE], ROW_SIZE);  in flash_sam0_commit()
239 	struct flash_sam0_data *ctx = dev->data;  in flash_sam0_write()
261 		off_t  start    = offset % sizeof(ctx->buf);  in flash_sam0_write()
262 		off_t  base     = offset - start;  in flash_sam0_write()
263 		size_t len_step = sizeof(ctx->buf) - start;  in flash_sam0_write()
264 		size_t len_copy = MIN(len - pos, len_step);  in flash_sam0_write()
266 		if (len_copy < sizeof(ctx->buf)) {  in flash_sam0_write()
267 			memcpy(ctx->buf, (void *)base, sizeof(ctx->buf));  in flash_sam0_write()
269 		memcpy(&(ctx->buf[start]), &(pdata[pos]), len_copy);  in flash_sam0_write()
302 		return -EINVAL;  in flash_sam0_write()
307 		return -EINVAL;  in flash_sam0_write()
315 		size_t eop_len = FLASH_PAGE_SIZE - (offset % FLASH_PAGE_SIZE);  in flash_sam0_write()
326 			len -= write_len;  in flash_sam0_write()
371 		return -EINVAL;  in flash_sam0_erase()
376 		return -EINVAL;  in flash_sam0_erase()
410 		NVMCTRL->ADDR.reg = offset + CONFIG_FLASH_BASE_ADDRESS;  in flash_sam0_write_protection()
414 			NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_LR |  in flash_sam0_write_protection()
417 			NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_UR |  in flash_sam0_write_protection()
422 			NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_LR |  in flash_sam0_write_protection()
425 			NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_UR |  in flash_sam0_write_protection()
467 	struct flash_sam0_data *ctx = dev->data;  in flash_sam0_init()
469 	k_sem_init(&ctx->sem, 1, 1);  in flash_sam0_init()
474 	PM->APBBMASK.bit.NVMCTRL_ = 1;  in flash_sam0_init()
476 	MCLK->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;  in flash_sam0_init()
481 	NVMCTRL->CTRLB.bit.MANW = 1;  in flash_sam0_init()
484 	NVMCTRL->CTRLA.bit.WMODE = NVMCTRL_CTRLA_WMODE_MAN_Val;  in flash_sam0_init()